CN108550528B - 半导体器件制造方法 - Google Patents
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Abstract
本发明公开了一种半导体器件制造方法，包括：形成第一材料层，所述第一材料层包含多个氢键；在第一材料层上形成第二材料层，第二材料层的致密度大于第一材料层，其中，在形成第一材料层之后、并且在形成第二材料层之前进一步包括，执行退火以减少所述多个氢键。依照本发明的半导体器件制造方法，形成硬掩模之前对介质层退火以完全去除氢键缺陷，提高了器件的抗漏电能力。
Description
技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种减少介质层特别是低k材料薄膜中氢键缺陷的方法。
背景技术
半导体工艺中，为了绝缘隔离半导体器件与金属布线层、或者相互隔离多个金属布线层，如图1a所示，通常在接触端子(例如MOSFET的栅极或源漏接触)相连的金属连接结构例如互联布线之间通过旋涂、喷涂、丝网印刷或低温CVD工艺等形成介电常数较低的绝缘层。一种典型的绝缘层是利用TEOS作为原料沉积形成的氧化硅薄膜(也可以简称TEOS)，以用作层间绝缘层。同时，在形成金属互联过程中需要对于介质层进行光刻/刻蚀等构图工艺以形成接触孔或沟槽，为了提高孔或沟槽侧壁的垂直度，通常在软质的介质层上方形成硬掩模层(例如ONO叠层)。
然而，这些低k材料诸如TEOS的层间绝缘层的形成过程中，由于沉积工艺自身工艺特性的限制，大量氢键(-H)存在于介质层中，这将降低薄膜质量，引起器件绝缘性能降低。例如图1c所示，后续填充金属形成互联时，氢键缺陷将介质层中产生孔洞或在互联结构侧壁上产生凸起，严重时造成相邻金属互联之间短路，或者孔洞引起介质层被击穿失效。
一种通常的解决方案是在制作其他器件结构之前，例如在刻蚀接触孔之前，执行退火以修复介质层中的氢键缺陷。这些缺陷虽然能够被退火驱动远离器件端子密集区域，一定程度上降低了缺陷，但是由于介质层上方硬质的硬掩模层的阻挡，氢键缺陷无法脱离介质层，聚集在介质层顶部，同样容易造成器件失效。
发明内容
因此，本发明的目的在于克服上述缺陷，降低介质薄膜中缺陷，提高互联结构侧壁的平整度，提高器件的稳定性。
为此，本发明提供了一种半导体器件制造方法，包括：
形成第一材料层，包含氢键缺陷；
在第一材料层上形成第二材料层，第二材料层的致密度大于第一材料层，
其中，形成第一材料层之后、形成第二材料层之前进一步包括，执行退火以减少氢键缺陷。
其中，第一材料层为绝缘介质，材质为TEOS、掺碳氧化硅、掺硼氧化硅、掺磷氧化硅、掺氟氧化硅、或低k材料。
其中，第二材料层为硬掩模层、阻挡层或导电层。
其中，第二材料层为单层或多层结构。
其中，退火温度为600至900摄氏度；任选地，退火时间为10分钟至2小时。
其中，形成第一材料之后、执行退火之前进一步包括，在第一材料层上形成牺牲层，牺牲层的致密度小于第一材料层。
其中，牺牲层材质为多孔低k材料。
其中，执行退火之后、形成第二材料层之前进一步包括去除牺牲层。
其中，退火的气氛包含稀有气体或氮气。
其中，退火的气氛进一步包括含有氘或氚的气体。
依照本发明的半导体器件制造方法，形成硬掩模之前对介质层退火以完全去除氢键缺陷，提高了器件的抗漏电能力。
本发明所述目的，以及在此未列出的其他目的，在本申请独立权利要求的范围内得以满足。本发明的实施例限定在独立权利要求中，具体特征限定在其从属权利要求中。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1a显示了现有技术3D金属互联的剖视图；
图1b显示了现有技术降低介质层缺陷方法的步骤的剖视图；
图1c显示了现有技术互联结构的扫描电镜图；
图2a至图2c显示了根据本发明实施例的半导体器件制造方法的剖视图；
图3显示了根据本发明实施例的制造方法的流程图；以及
图4显示了根据本发明实施例方法制造的互联结构的扫描电镜图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了可有效提高抗漏电能力的半导体器件制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
如图3和图2a所示，形成包含氢键缺陷的第一材料层1。提供衬底，例如体硅(bulkSi)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底，例如SiGe、Si:C、SIGeC、GaN、GaAs、InP等等，以及这些物质的组合。为了与现有的IC制造工艺兼容，衬底优选地为含硅材质的衬底，例如Si、SOI、SiGe、Si:C、SiGeC等。通过LPCVD、PECVD等常规工艺，在衬底上沉积形成第一材料层1，例如绝缘介质层。第一材料层层1用于实现半导体器件之间、半导体器件与金属互联之间、或多层金属互联之间的绝缘隔离，其材质例如为氧化硅(例如TEOS)、掺碳氧化硅、掺硼氧化硅、掺磷氧化硅、掺氟氧化硅等。优选地，为了降低寄生电容，第一材料层1采用低k材料，包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。这些低k材料的沉积工艺通常是旋涂、喷涂、丝网印刷、低温CVD等低温工艺，容易在第一材料层1中残留大量的悬挂键(例如C-H键、简称氢键)缺陷，这些缺陷在后续工艺过程或者产品使用过程期间，容易吸收其他杂质或发生迁移，造成绝缘隔离效果的衰减，使得器件可靠性降低。
为此，如图3和图2b所示，在形成第一材料层1之后，不沉积任何其他后续硬质结构(例如硬掩模层)，立即执行退火，将第一材料层1中的氢键缺陷驱动向表面迁移，直至完全排出至周围环境。退火的气氛优选稀有气体或氮气等不易与衬底、第一材料层1反应的气体。进一步优选地，可以额外地添加含氘或氚(H同位素)的气体以替代H。退火温度例如600至900摄氏度，优选650至800摄氏度，最佳700摄氏度。退火时间例如10分钟至2小时，优选30分钟至90分钟，最佳60分钟。
随后，如图3和图2c所示，在第一材料层1上形成第二材料层2。形成工艺例如PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD、蒸发、溅射等，第二材料层2的硬度或致密度大于第一材料层1，例如是硬掩模层或导电层。在本发明一个优选实施例中，第二材料层2也为绝缘层，例如金属互联结构(大马士革结构)刻蚀过程中所用的硬掩模层或阻挡层，材质例如氮化硅、氮氧化硅、掺碳氮化硅、碳化硅、掺氧碳化硅、掺氟氮化硅、掺氟碳化硅等。第二材料层也可以是导电材料，例如导电金属、导电的金属氧化物、导电的金属氮化物，例如Cu、Al、W、Mo、Ti、Ta、TiN、TaN、ITO等。第二材料层可以是多个子层的堆叠，例如氮化物-氧化物-氮化物(ONO结构)，或金属氮化物-金属(例如TiN/W)。
虽然在本发明一个优选实施例中，如图3所示，形成第一材料层1之后立即执行退火，但是也可以在退火之前在第一材料层1上采用相同或类似工艺形成硬度/致密度较低(也即低于第一材料层1)的牺牲层(未示出)，例如多孔低k材料。退火过程中，由于牺牲层硬度、致密度更低，氢键被退火驱动，聚集至牺牲层中，进一步减小了第一材料层1中的缺陷密度。随后，在退火之后，执行刻蚀或CMP平坦化工艺，去除牺牲层，获得更为光滑平整的第一材料层1。
如图4的扫描电镜图所示，采用图3所述的方法，能够大幅减少介质层例如氧化硅中缺陷，后续沉积金属形成的互联结构侧壁平整。
依照本发明的半导体器件制造方法，形成硬掩模之前对介质层退火以完全去除氢键缺陷，提高了器件的抗漏电能力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (10)
1.一种半导体器件制造方法，包括：
形成第一材料层，所述第一材料层包含多个氢键；
在所述第一材料层上采用与第一材料层相同的工艺形成牺牲层，所述牺牲层的致密度小于所述第一材料层；
执行退火以减少所述多个氢键，其中氢键被退火驱动而聚集至牺牲层中；
在所述第一材料层上形成第二材料层，所述第二材料层为硬掩模层、阻挡层或导电层。
2.如权利要求1所述的半导体器件制造方法，其中，所述第一材料层为低k材料。
3.如权利要求2所述的半导体器件制造方法，其中，所述低k材料为TEOS、掺碳氧化硅、掺硼氧化硅、掺磷氧化硅、掺氟氧化硅。
4.如权利要求1所述的半导体器件制造方法，其中，所述第二材料层的致密度大于所述第一材料层。
5.如权利要求1所述的半导体器件制造方法，其中，所述第二材料层为单层或多层结构。
6.如权利要求1所述的半导体器件制造方法，其中，退火温度为600至900摄氏度，退火时间为10分钟至2小时。
7.如权利要求1所述的半导体器件制造方法，其中，所述牺牲层材质为多孔低k材料。
8.如权利要求1所述的半导体器件制造方法，其中，执行退火之后、形成所述第二材料层之前进一步包括去除所述牺牲层。
9.如权利要求1所述的半导体器件制造方法，其中，所述退火的气氛包含稀有气体或氮气。
10.如权利要求9所述的半导体器件制造方法，其中，所述退火的气氛进一步包括含有氘或氚的气体。
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