CN108541141B - Partition alignment method for conducting hole layer and circuit graphic layer - Google Patents
Partition alignment method for conducting hole layer and circuit graphic layer Download PDFInfo
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- CN108541141B CN108541141B CN201810324651.4A CN201810324651A CN108541141B CN 108541141 B CN108541141 B CN 108541141B CN 201810324651 A CN201810324651 A CN 201810324651A CN 108541141 B CN108541141 B CN 108541141B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
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Abstract
The invention discloses a partition alignment method of a via hole layer and a circuit graphic layer, which comprises the following steps: forming a rectangular PCB jointed board, wherein a plurality of PCB delivery units with the same size are arranged on the PCB jointed board, and the area of the PCB jointed board except for each PCB delivery unit is a frame area; designing a plurality of partition central positioning targets and partition graphic positioning targets at the edge of the frame area respectively; obtaining the coordinate values of each partition center positioning target and each partition graph positioning target before expansion and contraction; processing the PCB jointed board; acquiring coordinate values of the expanded and contracted central points of the shipment units; acquiring the expanded and contracted size of each delivery unit; generating program data of a plurality of through hole layers which are in one-to-one correspondence with the delivery units; and aligning and processing each through hole layer to the PCB jointed board based on the program data of each through hole layer.
Description
Technical Field
The invention belongs to the field of printed circuit board manufacturing, and particularly relates to a partition alignment method for a via hole layer and a circuit pattern layer.
Background
With the development of science and technology, the functions of electronic products are more and more abundant, so the requirement for the refinement of Printed Circuit Boards (PCBs) is higher and higher. As shown in fig. 1, a PCB generally includes a via layer (a laser-processed via layer H2 and a mechanical-processed via layer H1 that are electrically conductive after being plated with copper) and a circuit layer, and the alignment accuracy of the via layer and the circuit layer directly determines the performance of the PCB. Therefore, each large PCB manufacturer invests a lot of manpower and material resources to improve the alignment process level of the via layer and the circuit layer.
On the other hand, in order to improve the production efficiency of the PCB board and save the production cost, as shown in fig. 2, a plurality of single-product PCB boards are generally spliced into a whole large PCB jointed board, and then a pattern layer and a via hole layer are formed on the PCB jointed board, and finally the single-product PCB jointed board is cut into single products.
In the prior art, when a PCB panel is processed, a target (a target pattern for positioning and measurement, a target hole) is generally arranged at the edge of the PCB panel, and then the coordinates of the target are read to calculate the center (or the center of gravity) of the PCB panel, so as to realize the alignment of the via hole layer and the pattern layer. However, because the expansion and shrinkage (the dimension of the PCB is changed by the temperature change during the production process) ratio of the via layer and the circuit layer is not consistent, the existing alignment processing method for the jointed board is adopted, and the following significant defects exist after the PCB is aligned and laminated: the PCB single products close to the central position of the PCB jointed board have higher alignment precision (good products), while the PCB single products close to the edge position of the PCB jointed board have very low contrast precision (waste products).
In view of the above technical problems, it is necessary to develop a new alignment process for a PCB jointed board to improve the alignment precision of each PCB single product thereon and improve the yield of the PCB board.
Disclosure of Invention
The invention aims to provide a partition alignment method of a via hole layer and a circuit diagram layer, which comprises the following steps:
the method comprises the following steps that firstly, a rectangular PCB jointed board is formed, a plurality of PCB delivery units with the same size are arranged on the PCB jointed board, a subarea is formed in the area where each PCB delivery unit is located, and the area of the PCB jointed board except for each PCB delivery unit is a frame area;
step two, four partition central positioning targets and four partition graph expansion and contraction targets are respectively designed at four corners of the edge of the frame area, the preset expansion and contraction proportion of each partition central positioning target is the same as the preset expansion and contraction proportion of the center point of each goods discharging unit, and the preset expansion and contraction proportion of each partition graph expansion and contraction target is the same as the preset expansion and contraction proportion of the size of each goods discharging unit;
step three, obtaining non-expansion and contraction coordinate values of the center points of the partition center positioning targets, the partition graph expansion and contraction targets and the shipment units;
processing the jointed PCB board, wherein the jointed PCB board is subjected to expansion and shrinkage in the processing process;
fifthly, obtaining the coordinate value of each central positioning target after expansion and contraction, calculating the expansion and contraction proportion of each central positioning target based on the coordinate value of each central positioning target after expansion and contraction and the coordinate value without expansion and contraction, and then calculating the coordinate value of the central point of each shipment unit after expansion and contraction based on the expansion and contraction proportion and the coordinate value without expansion and contraction of the central point of each shipment unit;
step six, obtaining a coordinate value of each partition graph after the expansion and contraction target expands and contracts, calculating the expansion and contraction proportion of each partition graph after the expansion and contraction target expands and contracts based on the coordinate value of each partition graph after the expansion and contraction target expands and contracts and the coordinate value without the expansion and contraction, and then calculating the expansion and contraction proportion, namely the expansion and contraction proportion of each shipment unit after the expansion and contraction;
seventhly, generating program data of a plurality of through hole layers corresponding to the shipment units one by one based on the coordinate values of the center points of the shipment units after expansion and contraction obtained in the step five and preset expansion and contraction proportions of the through hole layers;
and step eight, checking that the deviation between the expansion-shrinkage proportion obtained in the step six and the preset expansion-shrinkage proportion of the via hole layer is qualified, and then performing alignment processing on the program data generated in the step seven to the PCB jointed board.
In one embodiment, the method further comprises a coordinate system construction step, wherein the coordinate system is a Cartesian coordinate system, the origin of the coordinate system is at the central position of the PCB jointed board, the X axis of the coordinate system is consistent with the long side direction of the PCB jointed board, and the Y axis of the coordinate system is consistent with the short side direction of the PCB jointed board.
In a specific embodiment, a plurality of PCB delivery units are arranged on the PCB jointed board.
Compared with the alignment method in the prior art, the invention adopts the subarea alignment method, which can ensure that the alignment precision of the single PCB positioned at each subarea of the jointed PCB board reaches a higher level, thereby solving the alignment problem of the jointed PCB board in the prior art.
Drawings
FIG. 1 is a sectional structural view of a printed wiring board;
FIG. 2 is a schematic structural view of a PCB panel;
FIG. 3 is a graph showing the ratio of variation in expansion and contraction of coordinate values of a specific point in a plane of a product in the process of uniform expansion and contraction of the plane of the product, as compared with the ratio of variation in expansion and contraction of the whole size of the plane of the product;
FIG. 4 is a graph showing the variation of expansion and contraction of the dimension of a specific area in a plane of a product in comparison with the variation of expansion and contraction of the overall dimension of the plane of the product during uniform expansion and contraction of the plane of the product;
FIG. 5 is a comparison graph of the alignment deviation generated by center comparison and the alignment deviation generated by subarea alignment in the process of uniform expansion and contraction of the product plane;
FIG. 6 is a schematic diagram illustrating a partition alignment method according to an embodiment of the present invention;
FIG. 7 is a sectional view showing a PCB board according to the second embodiment;
FIG. 8 is a schematic diagram illustrating a partition alignment method according to a second embodiment of the present invention;
FIG. 9 is a schematic diagram of outputting only one partition data according to the second embodiment;
FIG. 10 is a schematic diagram of outputting all partition data according to the second embodiment;
FIG. 11 is a diagram illustrating the alignment processing effect of the hollow layers according to the second embodiment.
Detailed Description
The present invention will be further described with reference to specific embodiments for the purpose of illustrating the spirit and objects of the present invention.
First, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
The technical conception process of the invention is as follows:
the dimension of the PCB is uniformly changed in the expansion and contraction process (namely, the expansion and contraction conditions are consistent everywhere). And for a product plane with uniformly changed size, the change ratio of the position (coordinate) of any point on the product plane is the same as the change ratio of the product size.
For example, as shown in fig. 3, there is a product with dimensions 100mm x 80mm in the coordinate system, and the coordinates of a certain point M in the product are (60, 60). If the product size shrinks by 10% due to temperature change and becomes 90mm 72, the coordinates of point M correspondingly become smaller by 10%, namely: the coordinates of the point M become (54, 54).
b. In the product plane in which the size is uniformly changed, since the expansion and contraction ratios at the respective positions are uniform, the smaller the size, the smaller the expansion and contraction amount of the region.
For example, as shown in fig. 4, there is a product with dimensions 100mm by 80mm in the coordinate system, and the dimensions of a specific area (marked by a dotted line) in the product are 50mm by 40 mm. If the product size shrinks by 10% due to temperature change to 90mm 72, the size of the feature region correspondingly shrinks by 10% to 45mm 36 mm.
Based on the objective rules of the above sections a and b, the inventor further recognized that:
c. the deviation of selecting the center of the whole PCB jointed board for alignment is larger than the deviation of selecting the subareas thereof for alignment,
as shown in the left diagram of fig. 5, when the via hole layer H having a size of 90mm x 72mm is aligned with the PCB panel pattern layer P having a size of 100mm x 80mm, the deviation b1 at the edge of the long side is 5mm, and the deviation a1 at the edge of the short side is 4 mm.
As shown in the right diagram of fig. 5, the PCB panel pattern layer P with a size of 100mm × 80mm is divided into 4 sub-areas (P1, P2, P3, P4) with a size of 50mm × 40mm on average, and then the sub-areas (P1, P2, P3, P4) are respectively aligned with four via layers (H1, H2, H3, H4) with a size of 45mm × 36mm, so that the deviation b2 at the long edge of each sub-area (e.g., P2) on the PCB panel pattern layer P and the corresponding via layer (e.g., H2) is 2.5mm, and the deviation a2 at the short edge is 2 mm.
It can be seen that, by adopting the above-mentioned partition comparison method, the alignment precision between each sub-area (P1, P2, P3, P4) on the PCB panel graphic layer P and the corresponding via hole layer (H1, H2, H3, H4) is far better than the precision of selecting the center of the whole PCB panel for alignment (prior art).
Based on the above recognition of part c, the inventors further developed the technical solution of the present invention
Example one
For convenience of description, a PCB panel composed of four PCB units is taken as an embodiment of the present invention, as shown in fig. 6: in the first embodiment, four PCB shipping units (P1, P2, P3, P4) with the same size are designed on the PCB panel, the four shipping units are all a × b in size, and the central points of the four shipping units are M1, M2, M3, and M4, respectively. The areas of the PCB panel except for four PCB shipping units (P1, P2, P3, P4) are border areas.
With reference to fig. 6, in this embodiment, the method for partitioning and aligning the via layer and the circuit pattern layer provided by the present invention includes the following steps:
step 2, acquiring non-expansion and non-expansion coordinate values of the central points of the central positioning targets (A1, A2, A3 and A4), the partition graphic expansion and contraction targets (B1, B2, B3 and B4) and the delivery units (P1, P2, P3 and P4);
step 3, processing the PCB jointed board, wherein the PCB jointed board is subjected to expansion and shrinkage in the processing process;
referring to the above description of sections a and b, the change ratios of the coordinate values before and after the expansion and contraction of the respective centering targets (a1, a2, A3 and a4) are consistent with the change ratios of the coordinate values before and after the expansion and contraction of the center points (M1, M2, M3 and M4) of the respective delivery units (P1, P2, P3 and P4); the ratio of change in coordinate values before and after the expansion and contraction of each division pattern expansion and contraction target (B1, B2, B3, B4) is the same as the ratio of change in the length B and width a of each delivery unit (P1, P2, P3, P4).
Step 4, obtaining coordinate values of the central positioning targets (A1, A2, A3 and A4) after expansion and contraction, obtaining the expansion and contraction proportion of the central positioning targets (A1, A2, A3 and A4) based on the coordinate values of the central positioning targets (A1, A2, A3 and A4) after expansion and contraction and the coordinate values of no expansion and contraction, and then calculating the coordinate values of the central points (M1, M2, M3 and M4) of the delivery units (P1, P2, P3 and P4) after expansion and contraction based on the expansion and contraction proportion and the coordinate values of the central points (M1, M2, M3 and M4) of the delivery units (P1, P2, P3 and P4);
and 5, acquiring the coordinate values of the expansion and contraction targets (B1, B2, B3 and B4) of each partition graph, acquiring the expansion and contraction proportion of each partition graph expansion and contraction target (B1, B2, B3 and B4) based on the coordinate values of the expansion and contraction targets (B1, B2, B3 and B4) of each partition graph and the non-expansion and contraction coordinate values, and then acquiring the expansion and contraction proportion, namely the expansion and contraction proportion of each delivery unit (P1, P2, P3 and P4) after expansion and contraction.
And 6, generating program processing data of corresponding four conductive via layers (H1, H2, H3 and H4) based on the coordinate values of the center points (M1, M2, M3 and M4) of the delivery units (P1, P2, P3 and P4) after expansion and shrinkage and preset expansion and shrinkage ratios of the four conductive via layers (H1, H2, H3 and H4) obtained in the step 4.
The program processing data comprises coordinates of center points of four through hole layers (H1, H2, H3 and H4) and length and width dimensions of the four through hole layers (H1, H2, H3 and H4), wherein the coordinate values of the center points of the four through hole layers (H1, H2, H3 and H4) are the same as the coordinate values of the center points (M1, M2, M3 and M4) of each delivery unit (P1, P2, P3 and P4) after expansion and contraction.
And 7, checking whether the deviation between the expansion and shrinkage proportion of the cargo units (P1, P2, P3 and P4) obtained in the fifth step and the preset expansion and shrinkage proportion of the four conductive via layers (H1, H2, H3 and H4) is qualified, and aligning and processing program processing data of the conductive via layers (H1, H2, H3 and H4) obtained in the step 6 to the PCB jointed board.
Example two
To further describe the technical solution of the present invention, the second embodiment provides a processing technology of a four-layer PCB (as shown in fig. 7), and the processing technology uses the partition alignment method of the present invention.
As shown in fig. 8, in the second embodiment, the overall size of the PCB panel is 500mm × 600mm, 8 PCB shipment units with the same size are designed on the PCB panel, the size of each of the 8 shipment units is 150mm × 100mm, and the central points of the 8 shipment units are M1, M2, M3, M4, M5, M6, M7, and M8, respectively. The area of the PCB jointed board except for the 8 PCB delivery units is a frame area.
Establishing a coordinate system by taking the center of the PCB jointed board as an origin, wherein: the direction angles (representing the included angles between the long edges and the X axis) of the three PCB delivery units on the left side are 0 degree, the direction angles of the two PCB delivery units in the middle are 90 degrees and-90 degrees respectively, and the direction angles of the three PCB delivery units on the right side are 180 degrees.
Inner layer mechanical hole location target coordinates A1(-295,245), A2(295,245), A3(295, -245), A4(-295, -245);
the expansion and contraction ratios of the inner layer mechanical hole positioning target are 1.00000 in the X direction and 1.00000 in the Y direction;
the coordinates of the inner layer mechanical hole harmomegathus target are B1(-290,245), B2(290,245), B3(290, -245), B4(-290, -245);
the inner mechanical hole layer is preset with expansion and shrinkage proportion of 1.00200 in X direction and 1.00180 in Y direction;
the inner layer pattern positions target coordinates of C1(-295,240), C2(295,240), C3(295, -240), C4(-295, -240);
the expansion and shrinkage proportion of the inner layer graph positioning target follows the measurement result (namely automatic expansion and shrinkage);
the expansion and contraction target coordinates of the inner layer graph are D1(-290,240), D2(290,240), D3(290, -240), D4(-290, -240);
the preset expansion and contraction proportion of the inner layer graph expansion and contraction target is 1.00050 in the X direction and 1.00000 in the Y direction;
shipping unit center coordinates: m1(-145,150), M2(-145, 0), M3(-145, -150), M4(0,125), M5(0, -125), M6(145,150), M7(145,0), M8(145, -150).
The method comprises the following steps: jigsaw data editing
1. The jigsaw presets 9 subareas (preferably divided by one delivery unit or divided according to requirements), the delivery unit is divided into 8 independent subareas (product areas), the center positions of the product areas are M1, M2, M3, M4, M5, M6, M7 and M8 respectively, the areas except the delivery unit are divided into 1 independent subarea (frame area), the frame area comprises a positioning target and an expansion and contraction target, and the center position of the frame area is the center of the jigsaw (namely the origin of a coordinate system).
2. Two groups of targets are respectively arranged on the hole layer and the graphic layer, one group of positioning targets positions the center of each subarea, and the other group of expansion and contraction targets measures and calculates the expansion and contraction proportion of each layer.
Step two, outputting the jointed board data
1. The data editing software has a newly added partition output function and meets the following data output requirements.
2. Partition output data requirement:
the first way is that as shown in fig. 9, only one partition data is output from 8 product areas, and the position, direction and expansion and contraction ratio of each partition are output simultaneously. And the frame area outputs data, and the target and the graph in the data are independently set with the position and the expansion and contraction proportion.
In the second mode, as shown in fig. 10, the 8 product areas output the partition data, and each partition outputs the position, the direction, and the expansion and contraction ratio. And the frame area outputs data, and the target and the graph in the data are independently set with the position and the expansion and contraction proportion.
In the second embodiment, the inner layer machining program data and the inner layer graphic machining program data are output according to the first mode, which includes the following steps:
outputting inner layer mechanical hole machining program data:
a. the frame area positioning targets have no harmomegathus coordinates A1(-295,245), A2(295,245), A3(295, -245) and A4(-295, -245), and the preset harmomegathus ratios X:1.00000 and Y:1.00000 are set in the frame area positioning targets.
b. The expansion and contraction target of the frame area has no expansion and contraction coordinates B1(-290,245), B2(290,245), B3(290, -245) and B4(-290, -245), and the expansion and contraction ratio of the expansion and contraction target of the frame area is preset X:1.00200 and Y: 1.00180.
c. The relative coordinates of the processing data coordinates of the product area 1 and the processing center coordinates M1 of the product area 1 are represented by a letter N, and the mechanical hole layer is preset with expansion and contraction ratios in the X direction 1.00200 and the Y direction 1.00180. (calculation method: N ═ (machining data coordinates-machining center coordinates));
e. product zone 2 process data attribute (machine direction 0 °, machining center M2(-145, 0));
f. product zone 3 process data attribute (machine direction 0 °, machining center M3(-145, -150));
g. product zone 4 process data attributes (machine direction 90 °, machining center M4(0, 125));
h. product zone 5 process data attributes (machine direction-90 °, machining center M5(0, -125));
i. product zone 6 process data attributes (machine direction 180 °, machining center M6(145, 150));
j. product zone 7 process data attributes (machine direction 180 °, machining center M7(145, 0));
k. the product zone 8 processes the data attributes (machine direction 180 °, machining center M8(145, -150)).
Outputting inner layer graphic processing program data:
a. frame area location target coordinates:
C1(-295,240)、C2(295,240)、C3(295,-240)、C4(-295,-240)；
b. the expansion and contraction proportion of the frame area positioning target coordinate is automatic expansion and contraction (namely, the expansion and contraction proportion follows the measurement result of the actual jointed board);
c. frame area expansion and contraction target coordinate:
D1(-290,240)、D2(290,240)、D3(290,-240)、D4(-290,-240)；
d. the expansion and contraction ratio of the expansion and contraction target coordinate in the frame area is preset:
1.00050 in X direction and 1.00000 in Y direction (automatic expansion and contraction can be set according to actual requirements);
e. the relative coordinates of the graphic processing data coordinates of the product area 1 and the processing center coordinates M1 of the product area 1 are represented by a letter Z, and the graphic layer is preset with expansion and contraction proportions (X:1.00050, Y: 1.00000).
(calculation method: Z ═ (graphic processing data coordinate-graphic processing center coordinate));
g. product zone 2 graphic processing data attribute (processing direction 0 °, processing center M2(-145, 0));
h. product zone 3 graphic processing data attribute (processing direction 0 °, processing center M3(-145, -150));
i. product zone 4 graphic processing data attributes (machine direction 90 °, machining center M4(0, 125));
j. product zone 5 graphic processing data attributes (processing direction-90 °, processing center M5(0, -125));
k. product zone 6 graphic process data attributes (machine direction 180 °, machining center M6(145, 150));
product zone 7 graphic processing data attributes (machine direction 180 °, machining center M7(145, 0));
product zone 8 graphic process data attributes (machine direction 180 °, machining center M8(145, -150)).
Step three: stage of product processing
1. Mechanical drilling:
and calculating the hole position, the positioning target position and the expansion and contraction target position of the product area according to the data provided by the processing program, and finally drilling according to the calculation result. The specific processing steps are as follows:
a. and (4) taking a copper-clad plate, processing a fixing hole, and fixing the copper-clad plate to a drilling machine.
b. The drilling machine calculates each product area according to the non-expansion-contraction coordinate of each product area machining center and the preset expansion-contraction proportion of the positioning target
Product zone processing center coordinates M1(-145,150), M2(-145, 0), M3(-145, -150), M4(0,125), M5(0, -125), M6(145,150), M7(145,0), M8(145, -150).
c. And (b) converting the relative data coordinates N of the product area 1 in the drilling data by the drilling machine according to preset expansion and contraction proportional coordinates of the machining direction and the mechanical hole layer of each product area (note that the product areas with the arrangement directions of 0 degree and 180 degrees are converted according to the X direction 1.00200 and the Y direction 1.00180, and the product areas with the arrangement directions of 90 degrees and minus 90 degrees are converted according to the X direction 1.00180 and the Y direction 1.00200), and adding the coordinates of the machining centers of the product areas obtained in the step b to obtain the final machining data coordinates of the product areas.
d. And (3) calculating the coordinates of the positioning target A1(-295,245), A2(295,245), A3(295, -245) and A4(-295, -245) according to the non-expansion and contraction coordinates of the positioning target and the preset expansion and contraction ratio of the positioning target by the drilling machine.
e. The drilling machine calculates the harmomegathus target coordinate B1(-290.58,245.441), B2(290.58,245.441), B3(290.58, -245.441), B4(-290.58, -245.441) according to the harmomegathus target harmomegathus coordinate and harmomegathus target preset harmomegathus proportion
f. And finally, re-splicing the plates by the drilling machine according to the processing data coordinates of each product area to perform drilling processing. In this embodiment, the product area has 4 mechanical holes, and the processing effect is as shown in fig. 11, where the dotted line hole is the processing position initially set, and the solid line hole is the processing position after the preset expansion and contraction.
2. Inner layer patterning
Reading the mechanical hole positioning target to position the center of each product area, reading the mechanical hole expansion and shrinkage target to determine the actual expansion and shrinkage proportion of the mechanical hole layer of the product area, judging whether the preset expanded and shrunk graph processing data is suitable or not according to the reading result, and if the preset expanded and shrunk graph processing data is suitable, recalculating the jointed board data according to the reading result of the target and processing (the automatic expansion and shrinkage is not required to be judged).
In this example, the shrinkage of the product from drilling to patterning was 0.00100 in the X direction and 0.00130 in the Y direction. The specific flow of the inner layer pattern processing is as follows:
a. reading the mechanical aperture layer positioning target by an exposure machine to obtain expansion and contraction ratio X direction 0.99900 and Y direction 0.99870, and calculating the center coordinates of a product area M1(-144.855,149.805), M2(-144.855, 0), M3(-144.855, -149.805), M4(0,124.8375), M5(0, -124.8375), M6(144.855,149.805), M7(144.855,0) and M8(144.855, -149.805);
b. the exposure machine reads the mechanical orifice layer expansion and shrinkage target to obtain the mechanical orifice layer expansion and shrinkage ratio in the X direction 1.00100 and the Y direction 1.00050, and the exposure machine judges whether the graphic processing data of the graphic layer preset expansion and shrinkage ratio in the X direction 1.00050 and the Y direction 1.00000 are suitable for the jointed board product (assumed to be suitable here).
c. The exposure machine calculates new positioning target processing coordinates C1(-294.705,239.688), C2(294.705,239.688), C3(294.705, -239.688), C4(-294.705, -239.688) according to the actual expansion and contraction ratios of the positioning targets of the mechanical hole layer in the X direction 0.99900 and the Y direction 0.99870 and the newly set positioning target coordinates C1(-295,240), C2(295,240), C3(295, -240), C4(-295, -240).
d. The exposure machine calculates new expansion and contraction target processing coordinates D1(-290.145,240), D2(290.145,240), D3(290.145, -240) and D4(-290.145, -240) according to the preset expansion and contraction ratio X direction 1.00050 and Y direction 1.00000 of the graph layer and the newly set expansion and contraction target coordinates D1(-290,240), D2(290,240), D3(290, -240) and D4(-290, -240).
e. The exposure machine converts the coordinates represented by Z in the graphic data according to the processing direction of each product area and the preset expansion and contraction ratio coordinates (note that the product areas with the arrangement directions of 0 degrees and 180 degrees are converted according to the X direction 1.00050 and the Y direction 1.00000, and the product areas with the arrangement directions of 90 degrees and 90 degrees are converted according to the X direction 1.00000 and the Y direction 1.00050), and then adds the center coordinates M1(-144.855,149.805), M2(-144.855, 0), M3(-144.855, -149.805), M4(0,124.8375), M5(0, -124.8375), M6(144.855,149.805), M7(144.855,0) and M8(144.855, -149.805) of the product areas respectively to obtain the processing coordinates of each product area.
f. And c, carrying out plate splicing processing by the exposure machine according to the coordinates calculated in c, d and e. The processing effect graph is similar to the mechanical drilling processing effect graph.
3. And the inner layer pattern forming method is repeatedly adopted in the following steps of laser drilling, outer layer pattern forming, outer layer mechanical drilling, welding-proof pattern forming, forming and the like.
What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (2)
1. A partition alignment method for a via hole layer and a circuit pattern layer is characterized by comprising the following steps:
the method comprises the following steps that firstly, a rectangular PCB jointed board is formed, a plurality of PCB delivery units with the same size are arranged on the PCB jointed board, a subarea is formed in the area where each PCB delivery unit is located, and the area of the PCB jointed board except for each PCB delivery unit is a frame area;
step two, respectively designing four partition central positioning targets and four partition graph expansion and contraction targets at four corners of the edge of the frame area, wherein the preset expansion and contraction proportion of the partition central positioning targets is the same as the preset expansion and contraction proportion of the center point of the PCB delivery unit, and the preset expansion and contraction proportion of the partition graph expansion and contraction targets is the same as the preset expansion and contraction proportion of the size of the PCB delivery unit;
step three, obtaining non-expansion and contraction coordinate values of the center points of the partition center positioning targets, the partition graph expansion and contraction targets and the shipment units;
processing the jointed PCB board, wherein the jointed PCB board is subjected to expansion and shrinkage in the processing process;
fifthly, acquiring post-expansion and contraction coordinate values of the central positioning targets, calculating the expansion and contraction proportion of the central positioning targets based on the post-expansion and contraction coordinate values of the central positioning targets and the non-expansion and contraction coordinate values, and calculating post-expansion and contraction coordinate values of the central points of the shipment units based on the expansion and contraction proportion and the non-expansion and contraction coordinate values of the central points of the shipment units;
step six, obtaining a coordinate value of each partition graph after the expansion and contraction target expands and contracts, calculating the expansion and contraction proportion of each partition graph after the expansion and contraction target expands and contracts based on the coordinate value of each partition graph after the expansion and contraction target expands and contracts and a non-expansion and contraction coordinate value, and then obtaining the expansion and contraction proportion after the expansion and contraction proportion of each shipment unit size;
seventhly, generating program data of a plurality of through hole layers corresponding to the shipment units one by one based on the coordinate values of the center points of the shipment units after expansion and contraction obtained in the step five and preset expansion and contraction proportions of the through hole layers;
and step eight, checking that the deviation between the expansion-shrinkage proportion obtained in the step six and the preset expansion-shrinkage proportion of the via hole layer is qualified, and then performing alignment processing on the program data generated in the step seven to the PCB jointed board.
2. The via hole layer and circuit pattern layer partition alignment method of claim 1, wherein: the method further comprises a coordinate system constructing step, wherein the coordinate system is a Cartesian coordinate system, the origin of the coordinate system is located at the central position of the PCB jointed board, the X axis of the coordinate system is consistent with the long side direction of the PCB jointed board, and the Y axis of the coordinate system is consistent with the short side direction of the PCB jointed board.
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| CN109596971B (en) * | 2018-11-28 | 2020-12-18 | 深圳市大族数控科技有限公司 | Alignment method of flying probe tester |
| CN111299842B (en) * | 2018-12-11 | 2022-04-05 | 深圳市百柔新材料技术有限公司 | Method for high-precision laser engraving of solder mask |
| CN109738789B (en) * | 2019-01-02 | 2021-09-21 | 深圳市大族数控科技股份有限公司 | Flying probe tester testing method and device, flying probe tester and storage medium |
| CN110896594A (en) * | 2019-09-30 | 2020-03-20 | 宜兴硅谷电子科技有限公司 | Pin-positioning-free automatic expansion and contraction drilling production method |
| CN113115518B (en) * | 2021-04-13 | 2022-07-12 | 生益电子股份有限公司 | Collapsible translation method |
| CN118171627B (en) * | 2024-05-13 | 2024-07-30 | 清河电子科技(山东)有限责任公司 | Free type four-partition alignment frame design method, device, equipment and medium |
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| JPS63311798A (en) * | 1987-06-15 | 1988-12-20 | Hitachi Ltd | Alignment mark |
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