CN108536389A - Row replacement method, device and NAND memory device based on nand flash memory - Google Patents
Row replacement method, device and NAND memory device based on nand flash memory Download PDFInfo
- Publication number
- CN108536389A CN108536389A CN201710128852.2A CN201710128852A CN108536389A CN 108536389 A CN108536389 A CN 108536389A CN 201710128852 A CN201710128852 A CN 201710128852A CN 108536389 A CN108536389 A CN 108536389A
- Authority
- CN
- China
- Prior art keywords
- data
- written
- physical address
- address
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F2003/0697—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers device management, e.g. handlers, drivers, I/O schedulers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The embodiment of the invention discloses a kind of row replacement method, device and NAND memory device based on nand flash memory, this method is applied to NAND memory device, the storage device includes core array, redundant array, core array latch, redundant array latch and bad address latch, bad address latch stores bad address search table, the column address badly arranged in bad address search table storage core array；This method includes：When writing data, the physical address of data to be written is obtained；According to the physical address of data to be written and bad address search table, judge whether row corresponding with the physical address of data to be written damage in core array；When judging damage, redundant array is written by redundant array latch according to the data that the physical address of data to be written is written into.The embodiment of the present invention can improve the speed of read-write.
Description
Technical field
The present embodiments relate to memory technology more particularly to a kind of row replacement method, devices based on nand flash memory
And NAND memory device.
Background technology
Nand flash memory is one kind of Flash memories, belongs to nonvolatile semiconductor memory.Nand flash memory includes many numbers
According to block, each data block is made of lots of memory unit, for reading and writing data.
In nand flash memory, in order to deal with defective workmanship, it is ensured that the reliability of nand flash memory, it usually needs in core array
Place redundant array in side.It, can be with superfluous if the physical address chosen corresponding core array damage when reading and writing data
Remaining array replaces.Specifically, when there is data write-in, need first data to be written to be loaded into the physical address with core array
In corresponding latch, if the corresponding row damage of the physical address (such as bit line open circuit or short circuit) in core array, then
Data to be written are transferred in the latch of corresponding redundant array in latch, finally the physical address (namely core
Bad column address in array) corresponding latch write as " 1 ", that is, it resets.When data to be read, need first redundant array
Data are transferred to by the latch of redundant array in the corresponding latch of the bad column address of core array, then again from
The corresponding latch of bad column address transmission data outward.
It follows that whether write operation or read operation, damage has all been used in row replacement process and has arranged corresponding latch
For device as transfer, process is cumbersome, influences the read or write speed of memory.
Invention content
The embodiment of the present invention provides a kind of row replacement method, device and NAND memory device based on nand flash memory, with solution
Certainly the prior art needs to use the corresponding latch of damage row in then influence memory read/write speed when replacing into ranks
The problem of.
In a first aspect, an embodiment of the present invention provides a kind of row replacement method based on nand flash memory, is deposited applied to NAND
Equipment is stored up, the storage device includes core array, redundant array, core array latch and redundant array latch, wherein
The storage device further includes bad address latch, and bad address search table, the bad ground are stored in the bad address latch
The column address of bad row in the core array is stored in the look-up table of location；
Correspondingly, the method includes：
When writing data, the physical address of data to be written is obtained；
According to the physical address of the data to be written and the bad address search table, judge in core array with it is to be written
Whether the corresponding row of physical address of data damage；
When judging damage, the data being written into according to the physical address of the data to be written pass through redundant array
Redundant array is written in latch；
When reading data, the physical address of data to be read is obtained；
According to the physical address of the data to be read and the bad address search table, judge in core array with it is to be read
Whether the corresponding row of physical address of data damage；
When judging damage, according to the physical address of the data to be read, corresponding row read number from redundant array
According to, and exported by redundant array latch.
Further, the physical address according to the data to be written and the bad address search table, judge core
Whether row corresponding with the physical address of data to be written damage in array, including：
Exclusive or is done into whole bad address in the physical address of the data to be written and the bad address search table respectively
Operation is judged as that the corresponding row of the physical address of data to be written in core array do not damage if operation result is 1,
It is on the contrary then be judged as damaging；
The physical address according to the data to be read and the bad address search table, judge in core array with wait for
Whether the corresponding row of physical address for reading data damage, including：
Exclusive or is done into whole bad address in the physical address of the data to be read and the bad address search table respectively
Operation is judged as in core array that row corresponding with the physical address of data to be read do not damage if operation result is 1
It is bad, it is on the contrary then be judged as damaging.
Further, the method further includes：
When writing data, when judge in core array it is corresponding with the physical address of data to be written row do not damage
When, according to the physical address of the data to be written, described in the data write-in being written by the core array latch
Core array；
When reading data, when judge in core array it is corresponding with the physical address of data to be read row do not damage
When, according to the physical address of the data to be read, corresponding row read data from the core array, and pass through the core
Heart array latch exports.
Second aspect, an embodiment of the present invention provides a kind of row alternative based on nand flash memory are deposited applied to NAND
Equipment is stored up, the storage device includes core array, redundant array, core array latch and redundant array latch, wherein
The storage device further includes bad address latch, and bad address search table, the bad ground are stored in the bad address latch
The column address of bad row in the core array is stored in the look-up table of location；
Correspondingly, described device includes：
Physical address acquisition module, the physical address for obtaining data to be written when writing data, or reading data
When obtain the physical address of data to be read；
Row damage judgment module, is used for the physical address according to the data to be written and the bad address search table, sentences
Whether row corresponding with the physical address of data to be written damage in disconnected core array, or according to the object of the data to be read
Address and the bad address search table are managed, judges whether row corresponding with the physical address of data to be read damage in core array
It is bad；
First module for reading and writing, for when row damage judgment module judge damage when, according to the object of the data to be written
Redundant array, or the object according to the data to be read is written by redundant array latch in the data that reason address is written into
It manages address corresponding row from redundant array and reads data, and exported by redundant array latch.
Further, the row damage judgment module is specifically used for：
By the physical address and the bad address search table of the physical address of the data to be written or data to be read
In whole bad address do XOR operation respectively, if operation result is 1, be judged as in core array and data to be written
Physical address or the corresponding row of the physical address of data to be read do not damage, on the contrary then be judged as damaging.
Further, described device further includes：
Second module for reading and writing, for when row damage judgment module judge not damage when, according to the data to be written
Physical address, the core array is written in the data being written by the core array latch, or according to described
The physical address of data to be read corresponding row from the core array read data, and pass through the core array latch
Output.
The third aspect, an embodiment of the present invention provides a kind of NAND memory device, the storage device includes firmware, core
Array, redundant array, core array latch and redundant array latch, wherein the storage device further includes bad address lock
Storage is stored with bad address search table in the bad address latch, the core array is stored in the bad address search table
The column address of middle bad row；
Correspondingly, the firmware includes the row alternative based on nand flash memory as described above.
The embodiment of the present invention by reading data or when writing data, by the physical address of data to be read or to be written and
Bad address search table come judge in core array it is corresponding row whether damage, and when judge damage when, according to it is described physically
Data to be read or to be written are read from redundant array or are written redundant array by location, avoid the core when reading and writing data
Damage in array arranges corresponding latch as transfer, to accelerate the speed of read-write operation.
Description of the drawings
Figure 1A is a kind of flow chart of the row replacement method based on nand flash memory in the embodiment of the present invention one；
Figure 1B is a kind of flow chart of the row replacement method based on nand flash memory in the embodiment of the present invention one；
Fig. 2 is a kind of structural schematic diagram of the row alternative based on nand flash memory in the embodiment of the present invention two；
Fig. 3 is a kind of structural schematic diagram of NAND memory device in the embodiment of the present invention three.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Figure 1A and Figure 1B is a kind of flow chart for row replacement method based on nand flash memory that the embodiment of the present invention one provides,
The present embodiment is applicable to the case where row based on nand flash memory are replaced, and is applied to NAND memory device, the storage device packet
Core array, redundant array, core array latch and redundant array latch are included, this method can be based on NAND sudden strains of a muscle by having
The device for the row replacement function deposited executes, which may be used software and/or the mode of hardware is realized, for example, storage is set
Standby firmware.
The method that the embodiment of the present invention one provides specifically includes：
S110, when writing data, obtain the physical address of data to be written.
Specifically, nand flash memory is one kind of flash memories, belong to non-volatile memory device.Storage device it is main
Function is storage program and various data, and can high speed, be automatically completed the accesses of program or data.NAND memory device includes
Multiple memory cells, read-write data manipulation is that corresponding memory cell is positioned according to physical address.
Specifically, when writing data, acquisition is written into data and is written to corresponding physical address in nand flash memory.
S120, the physical address according to data to be written and bad address search table, judge in core array with number to be written
According to physical address it is corresponding row whether damage.
Wherein, the storage device further includes bad address latch, and bad address search is stored in the bad address latch
Table, the bad address search table are stored with the column address of bad row in core array, and the evil idea is classified as bad row when chip manufacture,
The producing cause of the bad row can be due to bad row caused by manufacturing process, can also be caused bad for reasons of cost
Row.Can be that a latch stores a bit column address, a column address is stored with latch group when realization.
Specifically, the physical address for being written into data is compared with the address in bad address search table, and then judge
Whether the corresponding row of physical address of data to be written damage.
Optionally, the physical address according to data to be written and bad address search table, judge in core array with wait for
Whether the corresponding row of physical address of write-in damage, including：
XOR operation is done in the whole bad address being written into the physical address and bad address search table of data respectively, if fortune
It is 1 to calculate result, then is judged as that the corresponding row of the physical address of data to be written in core array do not damage, on the contrary then judge
For damage；
Wherein, the XOR operation belongs to logical operation.Its algorithm is：If a, two values of b differ, exclusive or
As a result it is 1；If a, two values of b are identical, exclusive or result is 0.
Specifically, if the physical address of data to be written is identical as a certain bad address in bad address search table, occur
The case where operation result is 0 is judged as that the physical address of data to be written in core array is corresponding and shows damage；If to be written
The physical address of data is all different with the whole bad address in bad address search table, then operation result is 1, is judged as core
The corresponding row of the physical address of data to be written do not damage in array.
S130, when judge damage when, pass through redundancy battle array according to the data that the physical address of data to be written is written into
Redundant array is written in row latch.
Wherein, the function of the redundant array is after finding row damage, then the data being written into are transferred to redundancy battle array
In row, to ensure the validity of storage device.
Specifically, after damage is fallen out in judgement, there is no need to be written into data to be written in the corresponding latch of bad row,
The data being directly written into according to the physical address of data to be written are first written redundant array latch and redundant array are written again,
Save the time of write operation.It avoids the occurrence of in the feelings for not knowing whether the corresponding row of the corresponding physical address of data to be written damage
Under condition, it is first written into data write-in latch, then data to be written are transferred in corresponding redundant array, to which simplification is write
The process of operation improves the speed for writing data.
Further, the method further includes：When writing data, when judging the object in core array with data to be written
When the corresponding row in reason address do not damage, according to the physical address of data to be written, it will be waited for by the core array latch
The core array is written in the data of write-in.
Wherein, one of the effect of the latch is caching, and data are conveyed by chip interface PAD, but once simultaneously
It will not all pass, can not write direct in core array, therefore first be written in latch by several times, after all writing, then lead to
Cross latch write-in core array.
Specifically, when judging that row corresponding with the physical address of data to be written do not damage in core array, root
According to the physical address of data to be written, core array latch is first write data into, then will be to be written by core array latch
The data write-in core array entered.
S140, when reading data, obtain the physical address of data to be read.
Wherein, reading data manipulation is carried out according to row, and each row are all corresponding, and there are one physical address.
Specifically, when reading data, obtains and data to be read are written to corresponding physical address in nand flash memory.
S150, the physical address according to data to be read and bad address search table, judge in core array with continue access
According to physical address it is corresponding row whether damage.
Specifically, the physical address of data to be read is compared with the address in bad address search table, and then judge
Whether the corresponding row of physical address of data to be read damage.
Optionally, the physical address according to data to be read and bad address search table, judge in core array with wait for
Whether the corresponding row of physical address for reading data damage, including：
XOR operation is done into whole bad address in the physical address of data to be read and bad address search table respectively, if fortune
It is 1 to calculate result, then is judged as in core array that row corresponding with the physical address of data to be read do not damage, on the contrary then sentence
Break as damage.
Specifically, if the physical address of data to be read is identical as a certain bad address in bad address search table, occur
The case where operation result is 0 is judged as that the physical address of data to be read in core array is corresponding and shows damage；If to be read
The physical address of data is all different with the whole bad address in bad address search table, then operation result is 1, is judged as core
The corresponding row of the physical address of data to be read do not damage in array.
S160, when judging damage, the corresponding row reading from redundant array according to the physical address of data to be read
Data, and exported by redundant array latch.
Specifically, after damage is fallen out in judgement, it is directly corresponding from redundant array according to the physical address of data to be read
Row read data, and exported by redundant array latch, save the time of read operation.
Optionally, when reading data, when judge in core array it is corresponding with the physical address of data to be read row do not have
When having damage, according to the physical address of data to be read, corresponding row read data from core array, and pass through core array
Latch exports.
Specifically, when reading data, when judging that row corresponding with the physical address of data to be read do not have in core array
When having damage, according to the physical address of data to be read, corresponding row read data from core array, by digital independent to right
In the latch answered, then exported by the core array latch.
The embodiment of the present invention by reading data or when writing data, read by band or the physical address of data to be written with
Bad address search table come judge in core array it is corresponding row whether damage, and when judge damage when, according to it is described physically
Data to be read or to be written are read or are written redundant array from redundant array by location, avoid the core when reading and writing data
Damage in heart array arranges corresponding latch as transfer, to accelerate the speed of read-write operation.
Embodiment two
Fig. 2 is a kind of structural schematic diagram of the row alternative based on nand flash memory in the embodiment of the present invention two, is applied to
NAND memory device, the storage device include that core array, redundant array, core array latch and redundant array latch
Device, the storage device further include bad address latch, and bad address search table is stored in the bad address latch, described bad
The column address of bad row in the core array is stored in address search table；
Correspondingly, the device specifically includes：
Physical address acquisition module 210, the physical address for obtaining data to be written when writing data, or reading
According to when obtain the physical address of data to be read；
Row damage judgment module 220, is used for the physical address according to the data to be written and the bad address search table,
Judge whether row corresponding with the physical address of data to be written damage in core array, or according to the data to be read
Physical address and the bad address search table judge whether row corresponding with the physical address of data to be read damage in core array
It is bad；
First module for reading and writing 230, for when row damage judgment module judge damage when, according to the data to be written
The redundant array is written by the redundant array latch in the data that physical address is written into, or is continued according to described
The physical address for evidence of fetching corresponding row from redundant array read data, and are exported by the redundant array latch.
Further, the row damage judgment module 220 is specifically used for：
By the physical address and the bad address search table of the physical address of the data to be written or data to be read
In whole bad address do XOR operation respectively, if operation result is 1, be judged as in core array and data to be written
Physical address or the corresponding row of the physical address of data to be read do not damage, on the contrary then be judged as damaging.
Further, described device further includes：
Second module for reading and writing, for when row damage judgment module judge not damage when, according to the data to be written
Physical address, the core array is written in the data being written by the core array latch, or according to described
The physical address of data to be read corresponding row from the core array read data, and pass through the core array latch
Output.
Data block processing unit provided in an embodiment of the present invention based on nand flash memory can perform any embodiment of the present invention
The data block processing method based on nand flash memory provided, has the corresponding function module of execution method and advantageous effect.
Embodiment three
Fig. 3 is a kind of structural schematic diagram of NAND memory device in the embodiment of the present invention three, as shown, including firmware
31, bad address latch 32, core array 33, redundant array 34, core array latch 35 and redundant array latch 36, Gu
Part 31 is latched with bad address latch 32, core array 33, redundant array 34, core array latch 35 and redundant array respectively
Device 36 connects.
Wherein, it is stored with bad address search table in bad address latch 32, core array is stored in the bad address search table
The column address of bad row in 33；Bad address latch 32 can have multiple, the column address of each bad row of latch storage one；Core
Array 33 is for storing data；Redundant array 34 is used for when bad row occurs in core array, and core array is replaced by arranging to replace
Store data.
Correspondingly, firmware 31 includes the row alternative based on nand flash memory described in above-described embodiment, specifically include：
Physical address acquisition module, the physical address for obtaining data to be written when writing data, or reading data
When obtain the physical address of data to be read；
Row damage judgment module, is used for the physical address according to the data to be written and the bad address search table, sentences
Whether row corresponding with the physical address of data to be written damage in disconnected core array, or according to the object of the data to be read
Address and the bad address search table are managed, judges whether row corresponding with the physical address of data to be read damage in core array
It is bad；
First module for reading and writing, for when row damage judgment module judge damage when, according to the object of the data to be written
The redundant array is written by the redundant array latch in the data that reason address is written into, or according to described to be read
The physical address of data corresponding row from redundant array read data, and are exported by the redundant array latch.
Further, the row damage judgment module is specifically used for：
By the physical address and the bad address search table of the physical address of the data to be written or data to be read
In whole bad address do XOR operation respectively, if operation result is 1, be judged as in core array and data to be written
Physical address or the corresponding row of the physical address of data to be read do not damage, on the contrary then be judged as damaging.
Further, the storage device further includes core array corresponding with the core array and redundant array respectively
Latch and redundant array latch；
Correspondingly, described device further includes：
Second module for reading and writing, for when row damage judgment module judge not damage when, according to the data to be written
Physical address, the core array is written in the data being written by the core array latch, or according to described
The physical address of data to be read corresponding row from the core array read data, and pass through the core array latch
Output.
What the executable any embodiment of the present invention of NAND memory device provided in an embodiment of the present invention provided is dodged based on NAND
The row replacement method deposited, by when reading data or writing data, passing through physical address and the bad ground of data to be read or to be written
Location look-up table come judge in core array it is corresponding row whether damage, and when judge damage when, according to the physical address will
Data to be read or to be written read or are written redundant array from redundant array, avoid the core array when reading and writing data
In damage arrange corresponding latch as transfer, to accelerate the speed of read-write operation.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (7)
1. a kind of row replacement method based on nand flash memory is applied to NAND memory device, the storage device includes core battle array
Row, redundant array, core array latch and redundant array latch, which is characterized in that
The storage device further includes bad address latch, and bad address search table is stored in the bad address latch, described
The column address of bad row in the core array is stored in bad address search table；
Correspondingly, the method includes：
When writing data, the physical address of data to be written is obtained；
According to the physical address of the data to be written and the bad address search table, judge in core array with data to be written
Physical address it is corresponding row whether damage；
When judging damage, the data being written into according to the physical address of the data to be written pass through the redundant array
The redundant array is written in latch；
When reading data, the physical address of data to be read is obtained；
According to the physical address of the data to be read and the bad address search table, judge in core array with data to be read
Physical address it is corresponding row whether damage；
When judging damage, according to the physical address of the data to be read, corresponding row read data from redundant array,
And it is exported by the redundant array latch.
2. according to the method described in claim 1, it is characterized in that,
The physical address according to the data to be written and the bad address search table, judge in core array with it is to be written
Whether the corresponding row of physical address of data damage, including：
XOR operation is done into whole bad address in the physical address of the data to be written and the bad address search table respectively,
If operation result is 1, be judged as that the corresponding row of the physical address of data to be written in core array do not damage, it is on the contrary then
It is judged as damaging；
The physical address according to the data to be read and the bad address search table, judge in core array with it is to be read
Whether the corresponding row of physical address of data damage, including：
XOR operation is done into whole bad address in the physical address of the data to be read and the bad address search table respectively,
If operation result is 1, it is judged as in core array that row corresponding with the physical address of data to be read do not damage, it is on the contrary
Then it is judged as damaging.
3. method according to claim 1 or 2, which is characterized in that the method further includes：
When writing data, when judging that row corresponding with the physical address of data to be written do not damage in core array, root
According to the physical address of the data to be written, the core battle array is written by the data that the core array latch is written into
Row；
When reading data, when judging that row corresponding with the physical address of data to be read do not damage in core array, root
According to the physical address of the data to be read, corresponding row read data from the core array, and pass through the core array
Latch exports.
4. a kind of row alternative based on nand flash memory is applied to NAND memory device, the storage device includes core battle array
Row, redundant array, core array latch and redundant array latch, which is characterized in that the storage device further includes bad ground
Location latch is stored with bad address search table in the bad address latch, the core is stored in the bad address search table
The column address of bad row in array；
Correspondingly, described device includes：
Physical address acquisition module, the physical address for obtaining data to be written when writing data, or obtained when reading data
Take the physical address of data to be read；
Row damage judgment module, is used for the physical address according to the data to be written and the bad address search table, judges core
Whether row corresponding with the physical address of data to be written damage in heart array, or physically according to the data to be read
Location and the bad address search table judge whether row corresponding with the physical address of data to be read damage in core array；
First module for reading and writing, for when row damage judgment module judge damage when, physically according to the data to be written
The redundant array is written by the redundant array latch in the data that location is written into, or according to the data to be read
Physical address from redundant array corresponding row read data, and pass through the redundant array latch and export.
5. device according to claim 4, which is characterized in that the row damage judgment module is specifically used for：
It will be in the physical address of the data to be written or the physical address and the bad address search table of data to be read
All XOR operation is done in bad address respectively, if operation result is 1, is judged as the physics with data to be written in core array
The corresponding row of the physical address of address or data to be read do not damage, on the contrary then be judged as damaging.
6. device according to claim 4 or 5, which is characterized in that described device further includes：
Second module for reading and writing, for when row damage judgment module judge not damage when, according to the object of the data to be written
Address is managed, the core array is written by the data that the core array latch is written into, or continue according to described
The physical address for evidence of fetching corresponding row from the core array read data, and defeated by the core array latch
Go out.
7. a kind of NAND memory device, the storage device includes firmware, core array, redundant array, core array latch
With redundant array latch, which is characterized in that the storage device further includes bad address latch, in the bad address latch
It is stored with bad address search table, the column address of bad row in the core array is stored in the bad address search table；
Correspondingly, the firmware includes the row alternative based on nand flash memory as described in any one of claim 4-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710128852.2A CN108536389A (en) | 2017-03-06 | 2017-03-06 | Row replacement method, device and NAND memory device based on nand flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710128852.2A CN108536389A (en) | 2017-03-06 | 2017-03-06 | Row replacement method, device and NAND memory device based on nand flash memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108536389A true CN108536389A (en) | 2018-09-14 |
Family
ID=63489756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710128852.2A Pending CN108536389A (en) | 2017-03-06 | 2017-03-06 | Row replacement method, device and NAND memory device based on nand flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108536389A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312319A (en) * | 2018-12-12 | 2020-06-19 | 北京兆易创新科技股份有限公司 | Data replacement method and device |
| CN113127238A (en) * | 2019-12-30 | 2021-07-16 | 北京懿医云科技有限公司 | Method, apparatus, medium, and device for exporting data from database |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040019763A1 (en) * | 2002-07-29 | 2004-01-29 | Vinod Lakhani | Column/row redundancy architecture using latches programmed from a look up table |
| CN101421797A (en) * | 2006-03-24 | 2009-04-29 | 桑迪士克股份有限公司 | Non-volatile memory and method with redundancy data buffered in remote buffer circuits |
| CN102779096A (en) * | 2012-07-11 | 2012-11-14 | 山东华芯半导体有限公司 | Page, block and face-based three-dimensional flash memory address mapping method |
| CN103064795A (en) * | 2012-12-31 | 2013-04-24 | 华为技术有限公司 | Control method of memory device and relevant device |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| CN105677246A (en) * | 2015-12-31 | 2016-06-15 | 北京兆易创新科技股份有限公司 | NAND flash memory data reading method and device and NAND flash memory |
| CN106057246A (en) * | 2016-06-03 | 2016-10-26 | 北京兆易创新科技股份有限公司 | Method for replacing defective pixel units in non-volatile memory |
-
2017
- 2017-03-06 CN CN201710128852.2A patent/CN108536389A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040019763A1 (en) * | 2002-07-29 | 2004-01-29 | Vinod Lakhani | Column/row redundancy architecture using latches programmed from a look up table |
| CN101421797A (en) * | 2006-03-24 | 2009-04-29 | 桑迪士克股份有限公司 | Non-volatile memory and method with redundancy data buffered in remote buffer circuits |
| CN102779096A (en) * | 2012-07-11 | 2012-11-14 | 山东华芯半导体有限公司 | Page, block and face-based three-dimensional flash memory address mapping method |
| CN103064795A (en) * | 2012-12-31 | 2013-04-24 | 华为技术有限公司 | Control method of memory device and relevant device |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| CN105677246A (en) * | 2015-12-31 | 2016-06-15 | 北京兆易创新科技股份有限公司 | NAND flash memory data reading method and device and NAND flash memory |
| CN106057246A (en) * | 2016-06-03 | 2016-10-26 | 北京兆易创新科技股份有限公司 | Method for replacing defective pixel units in non-volatile memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312319A (en) * | 2018-12-12 | 2020-06-19 | 北京兆易创新科技股份有限公司 | Data replacement method and device |
| CN111312319B (en) * | 2018-12-12 | 2022-03-01 | 北京兆易创新科技股份有限公司 | Data replacement method and device |
| CN113127238A (en) * | 2019-12-30 | 2021-07-16 | 北京懿医云科技有限公司 | Method, apparatus, medium, and device for exporting data from database |
| CN113127238B (en) * | 2019-12-30 | 2024-02-09 | 北京懿医云科技有限公司 | Method and device for exporting data in database, medium and equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4062247B2 (en) | Semiconductor memory device | |
| US8656252B2 (en) | Memory controller and non-volatile storage device | |
| US8127071B2 (en) | Semiconductor memory device and block management method of the same | |
| KR100674544B1 (en) | Memory card and semiconductor device | |
| CN107885614A (en) | A kind of data processing method and data processing equipment based on memory | |
| US9104588B2 (en) | Circuits, apparatuses, and methods for address scrambling | |
| CN106653085A (en) | Storage device, memory system having the same, and operating method thereof | |
| US6633999B1 (en) | Integrated circuit with on-chip data checking resources | |
| CN111078462B (en) | Data verification method and circuit | |
| CN108536389A (en) | Row replacement method, device and NAND memory device based on nand flash memory | |
| US9230692B2 (en) | Apparatuses and methods for mapping memory addresses to redundant memory | |
| CN104969198A (en) | Data path integrity verification | |
| US8560891B2 (en) | EDRAM macro disablement in cache memory | |
| US8694838B2 (en) | Cache memory, processor, and production methods for cache memory and processor | |
| US10043588B2 (en) | Memory device | |
| CN108665941A (en) | Row restorative procedure, device and NAND memory device based on nand flash memory | |
| CN107766174A (en) | Electronic-controlled installation and its information storage means | |
| WO2024077825A1 (en) | Data storage method and apparatus based on ethash algorithm, device, and storage medium | |
| JP2014186772A (en) | Semiconductor memory device, controller, and memory system | |
| US20130067141A1 (en) | Data writing method, and memory controller and memory storage apparatus using the same | |
| KR102024661B1 (en) | Nonvolatile memory device and method of reading data thereof | |
| KR20110010381A (en) | Semiconductor memory device comprising self repair operation and self repair method thereof | |
| US8325546B2 (en) | Method and system for processing a repair address in a semiconductor memory apparatus | |
| WO2021232259A1 (en) | 3d nand flash memory device and integration method thereof | |
| CN108153616A (en) | A kind of storage chip startup program detection method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180914 |
|
| RJ01 | Rejection of invention patent application after publication |