CN111312319B - Data replacement method and device - Google Patents
Data replacement method and device Download PDFInfo
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- CN111312319B CN111312319B CN201811521158.8A CN201811521158A CN111312319B CN 111312319 B CN111312319 B CN 111312319B CN 201811521158 A CN201811521158 A CN 201811521158A CN 111312319 B CN111312319 B CN 111312319B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The invention discloses a method and a device for data replacement, which relate to the field of nonvolatile memories, and the method comprises the following steps: the decoder receives a first address sent by an upper computer, the first address comprises a high-order address and a low-order address, the redundancy control circuit matches the high-order address and sends the high-order address to the redundancy replacement circuit after matching, the redundancy address latch circuit matches the low-order address and decodes the low-order address at the same time, and the redundancy replacement circuit reads out redundancy storage unit data corresponding to the first address and sends the redundancy storage unit data to the data replacement circuit. The method and the device for replacing the data have the advantages that the data address is advanced in the decoder, so that the reading operation time when the storage unit fails is the same as that when the storage unit is normal, and the efficiency of the nonvolatile memory is improved.
Description
Technical Field
The present invention relates to the field of non-volatile memories, and more particularly, to a method and apparatus for data replacement.
Background
In the design of the existing nonvolatile memory, in order to avoid yield reduction caused by damage caused by defects, a redundancy circuit is designed in the nonvolatile memory, the redundancy circuit comprises a redundancy storage unit, a redundancy control circuit and a redundancy replacement circuit, and the redundancy storage unit can replace a storage unit module with a fault in the nonvolatile memory by adopting the redundancy control circuit and the redundancy replacement circuit.
The redundant memory cells can be read, programmed, and erased as normal memory cells. When some memory cells fail, the redundant memory cells can be enabled, when the redundant control circuit records the address of the failed memory cell, and when the nonvolatile memory accesses the failed regular memory cell, the redundant control circuit switches the corresponding operation to the redundant memory cell.
The read operation of the current nonvolatile memory is a high-speed process, and the frequency of a CLOCK (CLOCK) for performing the read operation is above 120 MHz. In the prior art, during the read and verify operations of the nonvolatile memory, the redundancy control circuit matches the current address with the address of the replaced failed memory cell, and after the current address is matched with the address of the replaced failed memory cell, the redundancy replacement circuit is started to replace the data information to be replaced. This data replacement and transmission path includes: the redundancy control circuit comprises matching logic of the redundancy control circuit, decoding logic of a replacement address, data replacement logic and a transmission delay path. The sum of the four delays is longer, and the normal DATA transmission path only includes the DATA BUS (DATA BUS) transmission path and DATA replacement.
Comparing the two paths, it can be seen that the path delay of the redundancy replacement is much longer than that of the normal data transmission path, and in order to guarantee the data transmission time, the path delay time of the redundancy replacement must be carefully evaluated in the chip design to ensure that the normal read and verify operations are not affected, but this adds complexity and workload to the circuit design, and the stability is not good.
Disclosure of Invention
In view of the above problems, the present invention provides a method and an apparatus for data replacement, which solve the problems in the prior art that a nonvolatile memory needs to design a complex circuit to ensure that the path delay time of redundancy replacement is substantially the same as the normal read and verify operation time, and the stability is not good.
The embodiment of the invention provides a data replacement method, which is applied to a nonvolatile memory, wherein the nonvolatile memory comprises a decoder, a data replacement circuit, a redundancy control circuit, a redundancy replacement circuit, a redundancy address latch circuit and a redundancy storage unit, and the method comprises the following steps:
the decoder receives a first address sent by an upper computer, wherein the first address is an address of data to be read, and comprises a high-order address and a low-order address;
the redundancy control circuit matches the high-order address and sends the high-order address to the redundancy replacement circuit after matching;
the redundancy replacement circuit decodes the high-order address and reads out the data of the redundancy storage unit corresponding to the high-order address according to the high-order address decoding;
after a first preset time, the decoder sends an updating enabling signal to the redundant address latch circuit, wherein the updating enabling signal is used for updating the address of the redundant address latch circuit;
the redundancy address latch circuit performs low-order address matching according to the updating enabling signal, performs low-order address decoding at the same time, and sends a matching signal and the low-order address decoding to the redundancy replacement circuit after matching;
the redundancy replacement circuit decodes according to the low-order address, and selects replacement data corresponding to the low-order address from the read redundancy storage unit data corresponding to the high-order address;
the redundancy replacement circuit sends the low order address matching signal and the replacement data to the data replacement circuit.
Optionally, before the decoder receives the first address sent by the upper computer, the method further includes:
when data reading operation is carried out for the first time, the decoder receives an address of data to be read for the first time and sends the address to the redundancy control circuit, and meanwhile, the decoder carries out address advance operation, wherein the address advance operation refers to that the address is advanced by a preset bit after the address of the data to be read for the first time is sent, so that when the decoder starts to output the data to be read for the first time, the address of the data to be read for the first time in the decoder starts to change by the preset bit;
the redundancy control circuit carries out address matching of data to be read for the first time, and sends an address to the redundancy replacement circuit after the address matching;
the redundancy replacement circuit decodes according to the address of the data required to be read for the first time, reads out the data of the redundancy storage unit corresponding to the address of the data required to be read for the first time, and sends the data to the data replacement circuit.
Optionally, the nonvolatile memory further includes a data bus and a storage unit, and after the redundancy replacement circuit sends the low address matching signal and the replacement data to the data replacement circuit, the method further includes:
the data replacement circuit performs data replacement on data corresponding to a first address, which has been read out, in the data bus, the data replacement being to replace data in a memory cell corresponding to the replacement data address with the replacement data.
Optionally, the redundancy control circuit matches the upper address, and the method includes:
the redundancy control circuit carries out address matching on the high-order address of the first address in the decoder, and if the high-order address is not matched correctly, the redundancy control circuit continues to match the high-order address of the second address.
Optionally, the redundant address latch circuit performs low address matching according to the update enable signal, and the method includes:
and the redundant address latch circuit performs low-order address matching according to the updating enabling signal, and if the low-order address is not matched correctly, the redundant address latch circuit continues to match the next low-order address.
Optionally, the redundancy control circuit performs address matching of data to be read for the first time, and the method includes:
and the redundancy control circuit performs address matching of data required to be read for the first time, and if the address matching is incorrect, the redundancy control circuit does not send an address to the redundancy replacement circuit.
The embodiment of the invention also provides a data replacement device, which is applied to a nonvolatile memory, wherein the nonvolatile memory comprises a decoder, a data replacement circuit, a redundancy control circuit, a redundancy replacement circuit, a redundancy address latch circuit and a redundancy storage unit, and the device comprises:
the decoder is used for receiving a first address sent by an upper computer, wherein the first address is an address of data to be read, and comprises a high-order address and a low-order address;
the high-order matching sending module is used for matching the high-order address by the redundancy control circuit and sending the high-order address to the redundancy replacement circuit after matching;
a high-order decoding read module for decoding the high-order address of the redundancy replacement circuit and reading the data of the redundancy storage unit corresponding to the high-order address according to the high-order address decoding;
the enabling module is used for sending an updating enabling signal to the redundant address latch circuit after the decoder is in a first preset time, and the updating enabling signal is used for updating the address of the redundant address latch circuit;
the low-order matching decoding sending module is used for the redundant address latch circuit to carry out low-order address matching according to the updating enabling signal, simultaneously carry out low-order address decoding, and send a matching signal and the low-order address decoding to the redundant replacement circuit after matching;
a selection replacement module for the redundancy replacement circuit decoding according to the low-order address and selecting the replacement data corresponding to the low-order address from the read redundancy storage unit data corresponding to the high-order address;
a sending module, configured to send the low-order address matching signal and the replacement data to the data replacement circuit by the redundancy replacement circuit.
Optionally, the apparatus further comprises:
the advanced address module is used for receiving an address of data to be read for the first time by the decoder when data reading operation is performed for the first time, sending the address to the redundancy control circuit, and performing address advanced operation by the decoder at the same time, wherein the address advanced operation refers to that the address is advanced by a preset bit after the address of the data to be read for the first time is sent, so that the address of the data to be read for the first time in the decoder is changed by the preset bit when the data to be read for the first time is output by the decoder;
the matching sending module is used for the redundancy control circuit to carry out address matching of data required to be read for the first time and sending the address to the redundancy replacement circuit after matching;
and the decoding reading replacement module is used for decoding the redundant replacement circuit according to the address of the data required to be read for the first time, reading out the data of the redundant storage unit corresponding to the address of the data required to be read for the first time, and sending the data to the data replacement circuit.
Optionally, the apparatus further comprises:
and the replacement module is used for performing data replacement on the read data corresponding to the first address in the data bus by the data replacement circuit, wherein the data replacement is to replace the data in the storage unit corresponding to the replacement data address with the replacement data.
Compared with the prior art, the method and the device for data replacement provided by the invention have the advantages that by optimizing the circuit design and adopting the data address advancing operation, the high order of the data address in the next period is verified when the data in the current period is output, and only the low order address is needed to be verified when the data in the next period is output, so that the total delay time of redundancy replacement is basically equal to the transmission delay time of a normal path.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of a data replacement method of the present invention;
FIG. 2 is a flow chart of steps prior to step 101 of a data replacement method of the present invention;
FIG. 3 is another flow chart of a data replacement method step 103 of the present invention;
FIG. 4 is another flow chart of a data replacement method step 105 of the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of the present invention;
FIG. 6 is a block diagram of a data substitution device of the present invention;
fig. 7 is another block diagram of a data replacement device of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Referring to fig. 1, a flowchart of a data replacement method is shown, where the method is applied to a nonvolatile memory, where the nonvolatile memory includes a decoder, a data replacement circuit, a redundancy control circuit, a redundancy replacement circuit, a redundancy address latch circuit, and a redundancy memory cell, and a specific method of data replacement may include the following steps:
step 101: the decoder receives a first address sent by the upper computer, wherein the first address is an address of data to be read, and the first address comprises a high-order address and a low-order address.
Referring to fig. 5, in an embodiment of the present invention, a nonvolatile memory includes a decoder 10, a redundancy control circuit 20, a redundancy replacement circuit 30, a redundancy address latch circuit 40, a redundancy memory cell 50, a memory cell array 60, a redundancy data selection unit 70, a data replacement circuit 80, a data bus 90, and a data selection unit 100, where the decoder 10 is used for decoding an address of data that is necessary for a user to perform a read or verify operation, the data address enters the decoder 10 and is decoded by the decoder 10, the data address includes a high address and a low address, and the redundancy control circuit 20 stores an address of a failed memory cell in the memory cell array 60, for example, a memory cell failure of addresses 08H, 18H, and 28H in the memory cell array 60, and then the redundancy control circuit 20 stores 08H, 28H, and b, 18H, 28H, the redundancy control circuit 20 is used to monitor the address in the decoder 10 and match the high address, and send the address to the redundancy replacement circuit 30 after matching, the redundancy replacement circuit 30 is used to decode the address and send it to the redundancy data selection unit 70 after decoding, the redundancy data selection unit 70 selects the data corresponding to the high address in the redundancy storage unit 50 according to the high address, and waits for the result of matching the low address, the redundancy address Latch circuit 40 is a Latch (Latch) arranged in the redundancy replacement circuit, the Latch can match and decode the low address, the Latch also stores the three addresses 08H, 18H, 28H, the redundancy address Latch circuit 40 matches and decodes the low address and sends it to the redundancy data selection unit 70, the redundancy data selection unit 70 selects the data according to the data address, among the selected data corresponding to the higher address, the data corresponding to the lower address is selected, the data is sent to the data replacement circuit 80, the data replacement circuit 80 performs data replacement, and the data in the memory cell array 60 corresponding to the desired read data address is replaced with the data in the redundant memory cell 50 corresponding to the desired read data address. The embodiment of the present invention does not specifically limit the operation manner and the connection manner of each component or circuit in the nonvolatile memory.
Optionally, referring to fig. 2, before step 101, the method for data replacement further includes the following steps:
step 1001: when data reading operation is carried out for the first time, the decoder receives an address of data to be read for the first time, the redundancy control circuit carries out address matching on the decoder, and meanwhile, the decoder carries out address advancing operation, wherein the address advancing operation refers to that the address is advanced by a preset bit after the address of the data to be read for the first time is sent, so that when the data to be read for the first time is output by the decoder, the address of the data to be read for the first time in the decoder is changed by the preset bit.
Step 1002: the redundancy control circuit performs address matching of data to be read for the first time, and sends the address to the redundancy replacement circuit after the address matching.
Step 1003: the redundancy replacement circuit decodes the address of the data required to be read for the first time, reads out the data of the redundancy memory cell corresponding to the address, and sends the data to the data replacement circuit.
Referring to fig. 5, in the embodiment of the present invention, when performing a first data reading operation, because the read circuit of the nonvolatile memory for performing the read operation has a read module, when data is not output yet, the first read operation is complete, that is, when performing the first data reading operation, all data to be read is read onto the data bus 90, waiting for the data replacement circuit 80 to perform data replacement, the redundancy control circuit 20 monitors and matches addresses in the decoder, sends the addresses to the redundancy replacement circuit 30 after matching, the redundancy replacement circuit 30 decodes the addresses, sends the addresses to the redundancy data selection unit 70 after decoding, the redundancy data selection unit 70 selects in the redundancy storage unit 50 according to the addresses, reads data of the addresses, transmits the data to the data replacement circuit 80, performs data replacement by the data replacement circuit 80, and then outputs the data, when the required data is output, the data address in the decoder 10 is advanced to the preset bit, the preset bit is obtained by dividing the bit number of the nonvolatile memory by 8 in the invention, for example, the nonvolatile memory is 32 bits, the advanced preset bit is 4, the nonvolatile memory is 16 bits, the advanced preset bit is 2, the 32-bit nonvolatile memory is taken as an example, the data output mode is that the data output is carried out by taking 16 bytes as a unit, namely, one group is set from 00H to 0FH, the CLK (clock period of the read operation) set by the nonvolatile memory is changed from 00H to 0FH, one CLK time is changed by one bit address, the next group is set from 10H to 1FH, and the data output is carried out by one bit address, when the output data address is 00H in the first read operation, the address in the decoder 10 is 04H, and the data output address and the change of the address in the decoder 10 are read by the CLK set by the nonvolatile memory (read operation) after that the data output address and the address change are changed Clock cycles of operation) that the address in decoder 10 has read 0FH when the data output reads address 0 BH. The embodiment of the invention does not specifically limit the working mode of the decoder for leading the preset bit and the specific number of the preset bit.
Step 102: the redundancy control circuit matches the high-order address within a first preset time, and sends the high-order address to the redundancy replacement circuit after matching.
Referring to fig. 5, in the embodiment of the present invention, when the address in the decoder goes to 10H, the redundancy control circuit 20 matches the upper address 1 of the addresses 10H to 1FH in the decoder 10 for four CLK times, and sends the addresses 10H to 1FH to the redundancy replacement circuit 30 after address matching. The embodiment of the present invention does not specifically limit the specific manner of address matching for the redundancy control circuit 20.
Optionally, referring to fig. 3, step 102 may further include the steps of:
step 102 a: the redundancy control circuit carries out address matching on the high-order address of the first address in the decoder, and if the high-order address is not matched correctly, the redundancy control circuit will continue to match the high-order address of the second address.
Referring to FIG. 5, in the embodiment of the present invention, the redundancy control circuit 20 matches the addresses of the addresses 10H-13H in the decoder 10, but the address matching is incorrect, it is determined that the memory cell where the data address 10H-13H is located does not fail, the data to be read is read from the memory cell corresponding to the address 10H-13H in the memory cell array 60, and the redundancy control circuit 20 continues to wait for the high-order bits of the matching addresses 20H-2 FH. The embodiment of the present invention does not specifically limit the specific manner of address matching for the redundancy control circuit 20.
Step 103: the redundancy replacement circuit decodes the upper address, and reads out the data of the redundancy memory cell corresponding to the upper address based on the decoding of the upper address.
Referring to fig. 5, in the embodiment of the present invention, after receiving the address of 10H to 1FH, the redundancy replacement circuit 30 decodes the address, and sends the decoded address to the redundancy data selection unit 70, and the redundancy data selection unit 70 selects the data corresponding to the address of 10H to 1FH in the redundancy memory unit 50 according to the data address, reads the data, and waits for the data of the selected lower address. The embodiment of the present invention does not specifically limit the specific manner of decoding by the redundancy replacement circuit 30, and the specific manner of selecting data by the redundancy data selection unit 70.
Step 104: and after the first preset time, the decoder sends an updating enabling signal to the redundant address latch circuit, and the updating enabling signal is used for updating the address of the redundant address latch circuit.
Referring to fig. 5, in the embodiment of the present invention, when the address of the decoder 10 is read to 13H, the address of the data output is shifted to 0FH, and at this time, the data of the first group of addresses 00H to 0FH is all output, and at this time, the address in the decoder 10 is changed from 0FH to 10H, four CLK times have elapsed, and when the address in the decoder 10 is read to 13H, the decoder 10 sends a refresh enable signal to the redundant address latch circuit 40, the enable signal being used to make the redundant address latch circuit 40 match the lower bits 0 to F in the 10H to 1FH addresses in the decoder 10, and after one CLK time, the address in the decoder 10 is read to 14H, the address of the data output is shifted to 10H, and since the data redundancy replacement circuit 30 of the 10H to 1FH addresses has already been read, the redundant address latch circuit 40 only needs to perform matching and decoding of the lower bits 0 to F. The embodiment of the present invention does not specifically limit the specific manner in which the decoder 10 sends the enable signal, and the specific function of the enable signal.
Step 105: the redundant address latch circuit performs low-order address matching according to the update enabling signal, performs low-order address decoding at the same time, and sends a matching signal and the low-order address decoding to the redundant replacement circuit after matching.
Referring to fig. 5, in the embodiment of the present invention, the redundant address latch circuit 40 receives the refresh enable signal when the address of the decoder 10 reads 13H, after a CLK time, the redundant address latch circuit 40 starts to match the lower bits 0 to F in the addresses 10H to 1FH and performs address decoding in parallel, and after completion, the address matching signal and the lower address decoding in the addresses 10H to 1FH are sent to the redundant replacement circuit 30. The embodiment of the present invention does not specifically limit the address matching and decoding manner of the redundant address latch circuit 40.
Optionally, referring to fig. 4, step 105 may further include the steps of:
step 105 a: the redundant address latch circuit matches the low-order address according to the updating enabling signal, and if the low-order address is not matched correctly, the redundant address latch circuit will continue to match the next low-order address.
Referring to FIG. 5, in the embodiment of the present invention, the redundant address latch circuit 40 starts to match the lower bits 0-F of the addresses 10H-1 FH, but if the address matching is not correct, the next lower address matching is continued. For example, if the lower address 0 does not match, the lower address 1 is matched, and if the lower address 1 does not match, the matching 2 is continued until the correct lower address is matched.
Step 106: the redundancy replacement circuit decodes the lower address and selects replacement data corresponding to the lower address from among the read redundant memory cell data corresponding to the upper address.
Referring to fig. 5, in the embodiment of the present invention, the redundancy replacement circuit 20 receives the lower address decoding, selects the data corresponding to the lower address from the read data of the addresses 10H to 1FH, for example, if the lower address is 8, the selected replacement data is 18H. The embodiment of the present invention does not specifically limit the specific manner of selecting the replacement data by the redundancy control circuit 20.
Step 107: the redundancy replacement circuit sends the lower address matching signal and the replacement data to the data replacement circuit.
Referring to fig. 5, in the embodiment of the present invention, the redundancy replacement circuit 30 sends the low address matching signal and the replacement data to the data replacement circuit 80, and the data replacement circuit 80 performs data replacement to replace the data of the memory cell in the memory cell array 60 corresponding to the replacement data address with the data of the redundant memory cell 50 corresponding to the replacement data address, for example: if the replacement data address is 18H, the data replacement circuit 80 replaces the data of the memory cell at address 18H in the memory cell array 60 with the data of the memory cell at address 18H in the redundant memory cell 50. The embodiment of the present invention does not specifically limit the specific manner in which the data replacement circuit 80 replaces data.
For example, as shown in fig. 5, in the design scheme of this embodiment, the nonvolatile memory includes a decoder 10, a redundancy control circuit 20, a redundancy replacement circuit 30, a redundancy address latch circuit 40, a redundancy memory cell 50, a memory cell array 60, a redundancy data selection unit 70, a data replacement circuit 80, a data bus 90 and a data selection unit 100, where the decoder 10 is used for address decoding of the nonvolatile memory, when a user performs a read or verify operation, an address of data is necessary, the data address enters the decoder and is decoded by the decoder, the data address includes a high bit address and a low bit address, the redundancy control circuit 20 stores an address of a failed memory cell in the memory cell array 60, for example, a memory cell failure of addresses 08H, 18H and 28H in the memory cell array 60, the redundancy control circuit 20 stores three addresses 08H, 18H, 28H, the redundancy control circuit 20 monitors the address in the decoder 10 and matches the address with the higher address, the address is sent to the redundancy replacement circuit 30 after matching, the redundancy replacement circuit 30 decodes the address and sends the decoded address to the redundancy data selection unit 70, the redundancy data selection unit 70 selects the data corresponding to the higher address in the redundancy storage unit 50 according to the higher address, and waits for the result of the lower address matching, the redundancy address Latch circuit 40 is a Latch (Latch) provided in the redundancy replacement circuit, the Latch can match and decode the lower address, the Latch also stores three addresses 08H, 18H, 28H, the redundancy address Latch circuit 40 sends the lower address matching and decoded redundancy data selection unit 70, the redundant data selection unit 70 selects data corresponding to a lower address from the selected data corresponding to a higher address according to a data address, sends the data to the data replacement circuit 80, the data replacement circuit 80 performs data replacement, replaces the data in the memory cell array 60 corresponding to a desired read data address with the data in the redundant memory cell 50 corresponding to the desired read data address, if the memory cell corresponding to the desired read data address does not have a failure, a normal read operation is that the decoder 10 receives the data address, decodes the data, sends the decoded data to the data bus 90, the data bus 90 sends the address decoded data to the data selection unit 100, the data selection unit 100 selects the data corresponding to the address from the memory cell array 60, sends the data to the data bus 90, the data bus 90 sends the data to the data replacement circuit 80, and then outputting the data.
For example, a 32-bit nonvolatile memory, which outputs data in a manner of outputting data in 16 bytes, that is, in a set of 00H to 0FH, changes addresses from 00H to 0FH by a CLK (clock cycle of read operation) set in the nonvolatile memory, generally, one CLK is about 5 ns, one CLK changes one bit address for data output every CLK time, and in a next set of 10H to 1FH, one CLK changes one bit address for data output every CLK time, and the address in the decoder is also read by one CLK changing one bit address every time, and when the data is read for the first time, since the read circuit of the nonvolatile memory for the read operation has a read module, the first read operation is complete when the data is not output yet, that is, when the data is read for the first time, all the read data is read onto the data bus 90, waiting for the data replacement circuit 80 to perform data replacement, the decoder 10 sends data addresses 00H-0 FH to the redundancy control circuit 20, the redundancy control circuit 20 performs address matching, after matching, the addresses 00H-0 FH are sent to the redundancy replacement circuit 30, the redundancy replacement circuit 30 decodes the addresses, after decoding, the addresses are sent to the redundancy data selection unit 70, the redundancy data selection unit 70 selects in the redundancy storage unit 50 according to the addresses 00H-0 FH, reads data of the addresses, transmits the data to the data replacement circuit 80, the data replacement circuit 80 performs data replacement, and then outputs the data, at this time, when the data of the addresses 00H-0 FH are output, the data address in the decoder 10 is already advanced by 04H, namely, after the first reading operation, when the output data starts to output the address 00H, the address in the decoder 10 is 04H, and the change of the data output address and the address in the decoder 10 is set in the CLK time of 5 ns time set by the nonvolatile memory In doing so, the address is raised by one bit every 5 ns, i.e., when the data is output to the address 0BH, the address in the decoder 10 has read 0FH, which takes 55 ns. When the first required read data output is read to 0CH, the address in the decoder 10 is read to 10H, i.e. the address received in the decoder 10 is the data group address 10H-1 FH required to be read in the next read cycle.
When the address in the decoder reaches 10H, the redundancy control circuit 20 matches the upper address 1 in the addresses 10H to 1FH in the decoder 10 within 4 CLK times, that is, within 20 ns, the address matching sends the 10H to 1FH address to the redundancy replacement circuit 30, the redundancy replacement circuit 30 decodes the address, the redundancy replacement circuit 30 reads the data of the addresses 10H to 1FH from the redundancy memory cell 50, the output data address reaches 0FH after 20 ns, and the address in the decoder 10 reaches 13H, it is understood that the redundancy control circuit 20 matches the upper address 1 in the addresses 10H to 13H within 20 ns, but the address matching is not correct, it is determined that the memory cell in which the data address 10H to 13H is located does not fail, the data of the addresses 10H to 13H is read from the memory cell array 60 corresponding to the addresses 10H to 13H, waiting for the result of the lower address decoding.
When the address of the decoder 10 reads 13H, the address of the data output is shifted to 0FH, and the data of the first group of addresses 00H to 0FH is completely output, and when the address reads 13H in the decoder 10, the decoder 10 sends a refresh enable signal to the redundant address latch circuit 40, the enable signal being used for the redundant address latch circuit 40 to match the lower bits 0 to F in the 10H to 1FH addresses in the decoder 10, and when the address of the decoder 10 is shifted to 14H after one CLK time, i.e., 5 ns, the address of the data output is shifted to 10H, and since the data redundancy replacement circuit 30 of the 10H to 1FH addresses has already read, the redundant address latch circuit 40 only needs to match and decode the lower bits 0 to F. The redundant address latch circuit 40 receives the refresh enable signal when the address of the decoder 10 reads 13H, and after 5 ns, the redundant address latch circuit 40 starts to match the lower bits 0 to F in the addresses 10H to 1FH and performs address decoding in parallel, and after completion, sends the address matching signal and the lower bit address decoding in the addresses 10H to 1FH to the redundant replacement circuit 30, and it can be understood that the redundant address latch circuit 40 starts to match the lower bits 0 to F in the addresses 10H to 1FH, but the address matching is incorrect, and then continues to perform the next lower bit address matching. For example, if the lower address 0 does not match, the lower address 1 is matched, and if the lower address 1 does not match, the matching 2 is continued until the correct lower address is matched, for example, if the lower address is 8, until the correct lower address is matched, the lower address 8 is matched until the correct lower address is 8, then the redundancy address latch circuit 40 sends the lower address 8 to the redundancy replacement circuit 20, because the data of the addresses 10H to 1FH already exists in the redundancy replacement circuit 20, the data of 18H is selected from the addresses 10H to 1FH after the lower address 8 is received as replacement data, and then the address 18H data is sent to the data replacement circuit 80, and the data replacement circuit 80 replaces the data of the memory cell of the address 18H in the memory cell array 60 with the data of the memory cell of the address 18H in the redundancy memory cell 50 according to the data of the address 18H.
Continuing the above process, when the address in the decoder 10 is read to 20H, the output data address is proceeded to 1CH, that is, the address received in the decoder 10 is the data group address 20H-2 FH to be read in the next reading cycle, when the address in the decoder is proceeded to 20H, the redundancy control circuit 20 matches the upper address 2 in the addresses 20H-2 FH in the decoder 10 within 4 CLK times, that is, within 20 ns, sends the address 20H-2 FH to the redundancy replacement circuit 30 after the address matching, the redundancy replacement circuit 30 decodes the address, the redundancy replacement circuit 30 reads the data of the addresses 20H-2 FH from the redundancy storage unit 50, the output data address is proceeded to 1FH after 20 ns, the address in the decoder 10 is proceeded to 23H, it can be understood that the redundancy control circuit 20 performs the matching of the upper address 1 in the addresses 20H-23H within 20 ns, however, if the address matches incorrectly, it is determined that the memory cells in which the data addresses 20H to 23H are located do not fail, and the data of the addresses 20H to 23H are read from the memory cells corresponding to the addresses 20H to 23H in the memory cell array 60, and the result of decoding the lower address is waited for.
When the address of the decoder 10 is read to 23H, the address of the data output is 1FH, and the data of the second group of addresses 10H to 1FH is completely output, when the address in the decoder 10 is read to 13H, the decoder 10 sends a refresh enable signal to the redundant address latch circuit 40, the enable signal is used for enabling the redundant address latch circuit 40 to match the lower bits 0 to F in the addresses 20H to 2FH in the decoder 10, and when the address in the decoder 10 is read to 24H after one CLK time, namely 5 ns, the address of the data output is 20H, because the data redundancy replacement circuit 30 of the addresses 20H to 2FH has already read, the redundant address latch circuit 40 only needs to match and decode the lower bits 0 to F. The redundant address latch circuit 40 receives the refresh enable signal when the address of the decoder 10 reads 23H, and after 5 ns, the redundant address latch circuit 40 starts to match the low bits 0 to F in the addresses 20H to 2FH and performs address decoding in parallel, and after completion, sends the address matching signal and the low bit address decoding in the addresses 20H to 2FH to the redundant replacement circuit 30, and it can be understood that the redundant address latch circuit 40 starts to match the low bits 0 to F in the addresses 20H to 2FH, but the address matching is incorrect, and then continues to perform the next low bit address matching. For example, if the lower address 0 does not match, the lower address 1 is matched, and if the lower address 1 does not match, the matching 2 is continued until the correct lower address is matched, for example, if the lower address is 8, until the correct lower address is matched, and until the correct lower address is 8, the redundancy address latch circuit 40 sends the lower address 8 to the redundancy replacement circuit 20, because the data of the addresses 20H to 2FH already exists in the redundancy replacement circuit 20, the data of 28H is selected from the addresses 20H to 2FH as replacement data after the lower address 8 is received, and then the data of the address 28H is sent to the data replacement circuit 80, and the data replacement circuit 80 replaces the data of the memory cell of the address 28H in the memory cell array 60 with the data of the memory cell of the address 28H in the redundancy memory cell 50 according to the data of the address 28H.
The above process is repeated until the data to be read is completely read, the operation of data address advance is adopted, so that when the data is output in the current period, the high order of the data address in the next period is verified, when the data is output in the next period, only the verification of the low order address is needed, the total delay time of redundancy replacement is basically equal to the transmission delay time of a normal path, in addition, in the actual design of the Layout (Layout) of the nonvolatile memory circuit, the redundancy address latch circuit 40 is designed to be close to the data replacement circuit 80 in the physical position, and the delay of the physical transmission path can be reduced.
It should be noted that, because the manufacturing process quality of the components adopted by the nonvolatile memory is different, the working states that can be achieved may differ, and the data is obtained through a large number of simulation experiments under the condition that the general manufacturing process is satisfied, and does not represent the indexes of all the nonvolatile memories. The embodiment of the present invention does not specifically limit the specific time for executing the read operation data and the specific number of leading addresses.
Referring to fig. 6, there is shown a block diagram of a data replacement apparatus comprising:
the receiving module 310 is configured to receive a first address sent by an upper computer, where the first address is an address of data to be read, and the first address includes a high-order address and a low-order address;
the high-order matching sending module 320 is used for the redundancy control circuit to match the high-order address and send the high-order address to the redundancy replacement circuit after matching;
a high-order decoding read module 330, configured to decode a high-order address by the redundancy replacement circuit, and read out data of the redundancy memory cell corresponding to the high-order address according to the high-order address decoding;
the enable module 340 is configured to send, after a first preset time, an update enable signal to the redundant address latch circuit, where the update enable signal is used to update an address of the redundant address latch circuit;
a low-order matching decoding sending module 350, configured to perform low-order address matching and low-order address decoding simultaneously by the redundant address latch circuit according to the update enable signal, and send the matching signal and the low-order address decoding to the redundant replacement circuit after matching;
a selection replacement module 360, configured to select, by the redundancy replacement circuit, replacement data corresponding to the lower address from the read redundant memory cell data corresponding to the higher address according to the decoding of the lower address;
and a sending module 370, configured to send the low address matching signal and the replacement data to the data replacement circuit by the redundancy replacement circuit.
Optionally, referring to fig. 7, the apparatus further includes:
the address look-ahead module 380 is configured to, when data reading operation is performed for the first time, receive an address of data to be read for the first time by a decoder, perform address matching on the decoder by the redundancy control circuit, and perform address look-ahead operation on the decoder at the same time, where the address look-ahead operation refers to that after the address of the data to be read for the first time is sent, the address is advanced by a preset bit, so that when the data to be read for the first time starts to be output by the decoder, the address of the data to be read for the first time in the decoder starts to change by the preset bit;
a matching sending module 390, configured to perform address matching on data to be read for the first time by the redundancy control circuit, and send the address to the redundancy replacement circuit after matching;
and a decoding reading sending module 400, configured to decode by the redundancy replacement circuit according to the address of the data to be read for the first time, read out the data of the redundancy memory cell corresponding to the address, and send the data to the data replacement circuit.
And a replacement module 410, configured to perform data replacement on the data corresponding to the first address, which has been read out from the data bus by using the data replacement circuit, where the data replacement is to replace the data in the memory cell corresponding to the replacement data address with replacement data.
Through the embodiment, when a user performs reading operation, the circuit design is optimized, the data address is subjected to the operation of data address advance, so that the high order of the data address in the next period is verified when the data in the current period is output, and only the low order address is verified when the data in the next period is output, so that the total delay time of redundancy replacement is basically equal to the transmission delay time of a normal path, and the efficiency of the reading operation of the nonvolatile memory is ensured.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The method and apparatus for data replacement provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in detail herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. A method of data replacement, which is applied to a nonvolatile memory including a decoder, a data replacement circuit, a redundancy control circuit, a redundancy replacement circuit, a redundancy address latch circuit, and a redundancy memory cell, the method comprising:
the decoder receives a first address sent by an upper computer, wherein the first address is an address of data to be read, and comprises a high-order address and a low-order address;
the redundancy control circuit matches the high-order address within a first preset time, and sends the high-order address to the redundancy replacement circuit after matching;
the redundancy replacement circuit decodes the high-order address and reads out the data of the redundancy storage unit corresponding to the high-order address according to the high-order address decoding;
after a first preset time, the decoder sends an updating enabling signal to the redundant address latch circuit, wherein the updating enabling signal is used for updating the address of the redundant address latch circuit;
the redundancy address latch circuit performs low-order address matching according to the updating enabling signal, performs low-order address decoding at the same time, and sends a matching signal and the low-order address decoding to the redundancy replacement circuit after matching;
the redundancy replacement circuit decodes according to the low-order address, and selects replacement data corresponding to the low-order address from the read redundancy storage unit data corresponding to the high-order address;
the redundancy replacement circuit sends the low-order address matching signal and the replacement data to the data replacement circuit;
when data reading operation is carried out for the first time, the decoder receives an address of data to be read for the first time, the redundancy control circuit carries out address matching on the decoder, and meanwhile, the decoder carries out address advance operation, wherein the address advance operation refers to that after the address of the data to be read for the first time is sent, the address is advanced by a preset bit, so that when the decoder starts to output the data to be read for the first time, the address of the data to be read for the first time in the decoder starts to change by the preset bit;
the redundancy control circuit carries out address matching of data to be read for the first time, and sends an address to the redundancy replacement circuit after the address matching;
the redundancy replacement circuit decodes according to the address of the data required to be read for the first time, reads out the data of the redundancy storage unit corresponding to the address of the data required to be read for the first time, and sends the data to the data replacement circuit.
2. The method of claim 1, wherein the non-volatile memory further comprises a data bus and a memory cell, and wherein after the redundancy replacement circuit sends the lower address match signal and the replacement data to the data replacement circuit, the method further comprises:
the data replacement circuit performs data replacement on data corresponding to a first address, which has been read out, in the data bus, the data replacement being to replace data in a memory cell corresponding to the replacement data address with the replacement data.
3. The method of claim 1, wherein the redundancy control circuit matches the upper address, the method comprising:
the redundancy control circuit carries out address matching on the high-order address of the first address in the decoder, and if the high-order address is not matched correctly, the redundancy control circuit continues to match the high-order address of the second address.
4. The method of claim 1, wherein the redundant address latch circuit performs low address matching according to the refresh enable signal, the method comprising:
and the redundant address latch circuit performs low-order address matching according to the updating enabling signal, and if the low-order address is not matched correctly, the redundant address latch circuit continues to match the next low-order address.
5. The method of claim 1, wherein the redundancy control circuit performs address matching of first required read data, the method comprising:
and the redundancy control circuit performs address matching of data required to be read for the first time, and if the address matching is incorrect, the redundancy control circuit does not send an address to the redundancy replacement circuit.
6. An apparatus for data replacement, which is applied to a nonvolatile memory including a decoder, a data replacement circuit, a redundancy control circuit, a redundancy replacement circuit, a redundancy address latch circuit, a redundancy memory cell, and a memory cell array, the apparatus comprising:
the decoder is used for receiving a first address sent by an upper computer, wherein the first address is an address of data to be read, and comprises a high-order address and a low-order address;
the high-order matching sending module is used for matching the high-order address by the redundancy control circuit and sending the high-order address to the redundancy replacement circuit after matching;
a high-order decoding read module for decoding the high-order address of the redundancy replacement circuit and reading the data of the redundancy storage unit corresponding to the high-order address according to the high-order address decoding;
the enabling module is used for sending an updating enabling signal to the redundant address latch circuit after the decoder is in a first preset time, and the updating enabling signal is used for updating the address of the redundant address latch circuit;
the low-order matching decoding sending module is used for the redundant address latch circuit to carry out low-order address matching according to the updating enabling signal, simultaneously carry out low-order address decoding, and send a matching signal and the low-order address decoding to the redundant replacement circuit after matching;
a selection replacement module for the redundancy replacement circuit decoding according to the low-order address and selecting the replacement data corresponding to the low-order address from the read redundancy storage unit data corresponding to the high-order address;
a sending module, configured to send the low-order address matching signal and the replacement data to the data replacement circuit by the redundancy replacement circuit;
the redundancy control circuit is used for performing address matching on the decoder and performing address look-ahead operation on the decoder at the same time, wherein the address look-ahead operation refers to that the address is advanced by a preset bit after the address of the first data to be read is sent, so that the address of the first data to be read in the decoder is changed by the preset bit when the first data to be read is output by the decoder;
the matching sending module is used for the redundancy control circuit to carry out address matching of data required to be read for the first time and sending the address to the redundancy replacement circuit after matching;
and the decoding reading sending module is used for decoding by the redundancy replacing circuit according to the address of the data required to be read for the first time, reading out the data of the redundancy storage unit corresponding to the address of the data required to be read for the first time, and sending the data to the data replacing circuit.
7. The apparatus of claim 6, further comprising:
and the replacement module is used for performing data replacement on the read data corresponding to the first address in the data bus by the data replacement circuit, wherein the data replacement is to replace the data in the storage unit corresponding to the replacement data address with the replacement data.
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