WO2024077825A1

WO2024077825A1 - Data storage method and apparatus based on ethash algorithm, device, and storage medium

Info

Publication number: WO2024077825A1
Application number: PCT/CN2023/076138
Authority: WO
Inventors: 杨媛媛; 刘明; 李彦; 石昊明; 闫超
Original assignee: 声龙(新加坡)私人有限公司
Priority date: 2022-10-09
Filing date: 2023-02-15
Publication date: 2024-04-18
Also published as: CN115292114A; CN115292114B

Abstract

The present application provides a data storage method and apparatus based on an ETHASH algorithm, a device, and a storage medium. The ETHASH algorithm is run on the basis of a chip, the chip comprises a plurality of memory blocks, and each memory block comprises a plurality of memory cells. The method comprises: testing a plurality of memory cells of a memory block to obtain a test result; classifying the plurality of memory cells into a first memory cell and a second memory cell according to the test result, wherein the first memory cell is a memory cell which passes the test, and the second memory cell is a memory cell which does not pass the test; acquiring cache data and storing the cache data into the first memory cell; and acquiring directed acyclic graph data according to the cache data, and storing the directed acyclic graph data into the first memory cell and/or the second memory cell.

Description

Data storage method, device, equipment and storage medium based on ETHASH algorithm

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese patent application number "202211225068.0" filed on October 9, 2022, with application name "Data storage method, device, equipment and storage medium based on ETHASH algorithm". The entire contents of the Chinese patent application are incorporated by reference into this application.

Technical Field

The present application relates to the field of semiconductor chip storage, and more specifically, to a data storage method, device, equipment and storage medium based on the ETHASH algorithm.

Background technique

Proof of Work (POW) is a process where a user performs some appropriately time-consuming complex calculations and obtains an answer, and the answer can be quickly verified by the service provider. The commonly used calculation method is hash calculation (ETHASH). First, you need to find a random value to input into the ETHASH algorithm, and the result obtained is lower than a threshold based on a specific difficulty value, namely the hash value. Since the ETHASH algorithm has nothing to do with the speed of calculation, but is related to the memory size of the computer that executes the ETHASH algorithm, the computer chip needs to have high-bandwidth, large-capacity and near-memory computing (NMC) functions.

At present, the design methods used for chips with large capacity are: 1) using a large number of dynamic random access memory (DRAM); 2) using advanced packaging technology, such as high bandwidth memory (HBM) or vertically stacking silicon wafers or bare crystals into the same package device (3DIC). Because the chips designed in this way have the common characteristics of a large number of storage units and a high storage density. However, due to the limitations of chip manufacturing process, the yield of storage units is low, resulting in a low overall yield of the chip. In order to solve the problem of low storage yield, memory repair is generally used. The method is to design redundant rows and columns in the storage block. When there are damaged rows or columns in the test storage block, they are replaced with redundant rows and columns. However, the redundancy that can be added by memory repair is limited, and the more storage units contained in the storage block, the higher the probability of bad blocks.

Technical Solutions

Some embodiments of the present application provide a data storage method, apparatus, device and storage medium based on the ETHASH algorithm that can at least partially solve the above-mentioned problems existing in the prior art.

According to one aspect of the present application, a data storage method based on an ETHASH algorithm is provided, wherein the ETHASH algorithm is based on chip operation, wherein the chip includes multiple storage blocks, each of which includes multiple storage units, and may include: testing multiple storage units of the storage block and obtaining test results; classifying the multiple storage units according to the test results, dividing them into a first storage unit and a second storage unit, wherein the first storage unit is a storage unit that passes the test, and the second storage unit is a storage unit that fails the test; obtaining cache data, and storing the cache data in the first storage unit; and The directed acyclic graph data is acquired based on the received data, and the directed acyclic graph data is stored in the first storage unit and/or the second storage unit.

In one embodiment of the present application, the method may further include: obtaining the number of the second storage units contained in the storage block and comparing it with a predetermined computing power value; in response to the number of the second storage units contained in the storage block exceeding the predetermined computing power value, performing an ETHASH operation on the directed acyclic graph data stored in the storage block and obtaining an operation result; and based on the operation result, determining a rejection rate of the storage block, if the rejection rate of the storage block is less than a preset value, the storage block is used for data storage, if the rejection rate of the storage block is greater than or equal to the preset value, the storage block is not used for data storage, wherein the rejection rate is the ratio of the number of data whose operation results are greater than a specific difficulty value to the number of overall data of the operation results.

In one embodiment of the present application, the step of obtaining cache data and storing the cache data in the first storage unit may include: obtaining a training number, wherein the training number is a ratio of the number of storage blocks to the training length; performing training based on the ETHASH algorithm and the training number to obtain a seed; calculating the length of the cache data; calculating the cache data based on the seed and the length of the cache data; and allocating storage space of the first storage unit for storage according to the cache data, and recording a storage address table of the cache data.

In one embodiment of the present application, the step of obtaining directed acyclic graph data based on the cache data may include: reading the cache data according to a storage address table of the cache data; calculating the length of the directed acyclic graph data; and calculating the directed acyclic graph data based on the length of the directed acyclic graph data and the read cache data.

In one embodiment of the present application, the storage space X of the cache data in the storage unit may satisfy: M*D*64/65≤X≤M*D-1, where M is the number of storage units that pass the test in the storage block, and D is the storage space address depth of the storage unit.

In one embodiment of the present application, the storage space Y of the directed acyclic graph data in the storage unit may satisfy: M*D*64/65≤Y≤L*D*64/65, wherein M is the number of storage units that pass the test in the storage block, D is the storage space address depth of the storage unit, and L is the number of storage units that store the directed acyclic graph data.

In one embodiment of the present application, the step of testing the storage area of the chip and obtaining the test result may include: writing initial test data into the storage unit, wherein the initial test data includes a known pseudo-random sequence; and reading the data of the storage unit, and comparing the read data of the storage unit with the initial test data, if the read data of the storage unit is the same as the initial test data, the test result of the storage unit is passed, and if the read data of the storage unit is different from the initial test data, the test result of the storage unit is failed.

In one embodiment of the present application, after the plurality of storage units are classified and processed according to the test results and divided into the first storage unit and the second storage unit, the method may further include: performing error checking and correction on the data stored in the second storage unit; and comparing the corrected data with the initial test data, and if the corrected data is the same as the initial test data, reclassifying the second storage unit. to the first storage unit.

On the other hand, the present application provides a data storage device based on the ETHASH algorithm, wherein the ETHASH algorithm is run based on a chip, wherein the chip includes multiple storage blocks, each of which includes multiple storage units, and may include: a testing module, used to test the multiple storage units of the storage block and obtain test results; a classification module, used to classify the multiple storage units according to the test results, and divide them into a first storage unit and a second storage unit, wherein the first storage unit is a storage unit that has passed the test, and the second storage unit is a storage unit that has not passed the test; a cache data acquisition and storage module, used to acquire cache data and store the cache data in the first storage unit; and a directed acyclic graph data acquisition and storage module, used to acquire the directed acyclic graph data according to the cache data, and store the directed acyclic graph data in the first storage unit and/or the second storage unit.

On the other hand, the present application provides an electronic device, which may include: a processor, suitable for executing a computer program; and a computer-readable storage medium, in which the computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, it implements any of the above methods.

In yet another aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, wherein the computer program enables a computer to execute any one of the above methods.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

FIG1 is a flow chart of a data storage method 1000 based on the ETHASH algorithm according to an embodiment of the present application;

FIG2 is a flow chart of a testing method according to an exemplary embodiment of the present application;

FIG3 is a flow chart of a method for re-dividing the second storage unit according to an exemplary embodiment of the present application;

FIG4 is a flow chart of a method for calculating cache data according to an exemplary embodiment of the present application;

FIG5 is a flow chart of a method for calculating directed acyclic graph data according to an exemplary embodiment of the present application;

FIG6A is a schematic diagram of a storage block according to an exemplary embodiment of the present application;

FIG6B is a schematic diagram of a storage block according to another exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a data storage device 2000 based on the ETHASH algorithm according to an exemplary embodiment of the present application; and

FIG. 8 is a schematic structural diagram of an electronic device 800 according to an exemplary embodiment of the present application.

Detailed ways

In order to better understand the present application, each aspect of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another. It is used to distinguish the characteristics without indicating any limitation on the characteristics.

It should also be understood that the terms "comprises", "including", "having", "includes" and/or "comprising", when used in this specification, indicate the presence of the stated features, elements and/or components, but do not exclude the presence or addition of one or more other features, elements, components and/or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including technical terms and scientific terms) used in this article have the same meaning as commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that terms (such as terms defined in commonly used dictionaries) should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formalized manner unless explicitly defined in this article.

It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

The features, principles and other aspects of the present application are described in detail below.

FIG1 is a flow chart of a data storage method 1000 based on the ETHASH algorithm according to an embodiment of the present application. The ETHASH algorithm is based on chip operation, the chip includes multiple storage blocks, each storage block includes multiple storage units, as shown in FIG1, the data storage method 1000 based on the ETHASH algorithm may include:

Step S100: testing multiple storage units of a storage block and obtaining test results;

Step S200: classifying the plurality of storage units according to the test results into first storage units and second storage units, wherein the first storage units are storage units that have passed the test and the second storage units are storage units that have not passed the test;

Step S300: Acquire cache data and store the cache data in a first storage unit; and

Step S400: Obtain directed acyclic graph data according to the cache data, and store the directed acyclic graph data in the first storage unit and/or the second storage unit.

The various steps of the data storage method 1000 based on the ETHASH algorithm will be described in detail below.

Step S100

The chip manufacturing process is very complicated, and it has to go through dozens or even hundreds of process procedures such as doping, oxidation, photolithography, and etching, involving various chemical, physical, and mechanical processes. Therefore, during the chip manufacturing process, a certain amount of bad memory blocks will appear. Even if the chip is intact, after a large amount of data is stored, the memory blocks in the chip may also become bad.

In an exemplary embodiment of the present application, the storage area of the chip is first tested and the test results are obtained, wherein the storage area includes multiple storage blocks, and each storage block includes multiple storage cells. Exemplarily, the test of the storage area of the chip includes a testability technology test (Design For Test, referred to as DFT), confirming whether the storage blocks and storage cells of the storage area of the chip are intact, and storing the test results. FIG. 2 is a flow chart of a test method according to an exemplary embodiment of the present application. As shown in FIG. 2, the test method includes the following steps:

Step S110: writing initial test data into a storage unit in a storage area, wherein the initial test data includes A known pseudo-random sequence;

Step S120: Read the data of the storage cell and compare the data read from the storage cell with the initial test data. If the data read from the storage cell is the same as the initial test data, the test result of the storage cell is passed; if the data read from the storage cell is different from the initial test data, the test result of the storage cell is failed.

Exemplarily, the initial test data is a known pseudo-random sequence, such as 01101001. The initial test data is written into the storage unit, and then the data of the storage unit is read, and the data of the read storage unit is compared with the initial test data. If the data of the read storage unit is the same as the initial test data, that is, the read data is 01101001, then the test result of the storage unit is considered to be passed; if the data of the read storage unit is different from the initial test data, then the test result of the storage unit is considered to be failed. Among them, the test of the storage area can be tested based on the storage unit as a unit, and then the test result of the storage block is further obtained according to the test results of the storage units contained in each storage block. It can be known to those skilled in the art that the test method of the present application and the pseudo-random sequence in the test process are exemplary descriptions, and the present application is not limited to this.

According to an exemplary embodiment of the present application, by testing the storage units of the storage block, it can be determined whether the tested storage units are intact, so as to subsequently allocate storage units to cache data and directed acyclic graph data according to the test results.

Step S200

In an exemplary embodiment of the present application, in step S200, multiple storage units can also be classified according to the test results and divided into a first storage unit and a second storage unit, wherein the first storage unit is a storage unit that passes the test and the second storage unit is a storage unit that fails the test.

After the plurality of storage units are classified and processed according to the test results, the second storage unit can also be re-divided by correcting the data of the second storage unit. FIG3 is a flow chart of a method for re-dividing the second storage unit according to an exemplary embodiment of the present application. As shown in FIG3, the method for re-dividing the second storage unit includes the following steps:

Step S210: performing error checking and correction on the data stored in the second storage unit;

Step S220: Compare the corrected data with the initial test data. If the corrected data is the same as the initial test data, re-divide the second storage unit into the first storage unit.

Since the data transmission rate begins to adopt the double data rate (DDR) transmission method, the DDR method uses the rising and falling edges of the selection signal (Data strobe signal, DQS) to sample the data signal (Data signal, DQ), that is, to read the data. Therefore, data reading errors may occur due to delays, which are not reading errors caused by damage to the storage unit. They can be recovered later through error checking and correction (Error Correcting Code, ECC). Exemplarily, after a plurality of storage units are classified and divided into a first storage unit and a second storage unit, error checking and correction are performed on the data stored in the second storage unit, and the corrected data is compared with the initial test data. If the corrected data is the same as the initial test data, it is considered that the second storage unit has passed the test, and the second storage unit is reclassified into the first storage unit. It can be known to those skilled in the art that error checking and correction of the second storage unit is an exemplary description, and other methods can also be used. For example, performing memory repair on the storage block where the second storage unit is located, etc., which is not limited in this application.

According to an exemplary embodiment of the present application, multiple storage units are classified and processed according to the test results, divided into a first storage unit and a second storage unit, and then the storage data of the second storage unit is error checked and corrected. If the second storage unit can pass the test after correction, the second storage unit is re-divided into the first storage unit, thereby maximizing the available storage area in the memory and improving the utilization rate of the storage unit.

Step S300

In step S300, cache data is obtained and stored in the first storage unit. FIG4 is a flow chart of a method for calculating cache data according to an exemplary embodiment of the present application. In an exemplary embodiment of the present application, as shown in FIG4, calculating cache data (cache) includes the following steps:

Step S310: Obtain the number of training times, where the number of training times is the ratio of the number of storage blocks to the training length;

Step S330: Perform training based on the ETHASH algorithm and the number of training times to obtain a seed;

Step S350: Calculate the length of the cached data;

Step S370: Calculating cache data based on the seed and the length of the cache data; and

Step S390: Allocate storage space of the first storage unit according to the cache data for storage, and record a storage address table of the cache data.

In the process of calculating the cache data, the current training times (epochs) are first calculated according to the number of storage blocks (block number) configured in the chip, where the training times are the ratio of the number of storage blocks to the training length (ETHASH epoch length). For example, the value of ETHASH epoch length is 30000, that is, the subsequent cache data will be changed once every 30000 storage blocks.

Then, training is performed based on the ETHASH algorithm and the number of training times to obtain a seed. For example, the initial value of the seed is set to 0, and then an iterative operation is performed based on the ETHASH algorithm according to the number of training times obtained in step S310, wherein the ETHASH algorithm may be SHA3_256, and a final seed may be obtained, for example, data with a length of 256 bits may be obtained as a seed.

Furthermore, the length of the cached data can be calculated according to the number of configured storage blocks and the ETHASH algorithm. The length of the cached data obtained by different training times is different, that is, the number of iterations of the subsequent calculation is related to the length of the cached data. Then the cached data is calculated based on the seed and the length of the cached data. For example, based on the ETHASH algorithm, the seed and the length of the cached data are subjected to modulus, SHA3_512 or XOR and other related operations to obtain the calculation result of the cached data (cache).

Then, storage space of the first storage unit is allocated for storage according to the cache data, and a storage address table of the cache data is recorded. Since the cache data (cache) is the intermediate data for calculating the directed acyclic graph data (dag), the storage and reading of the cache data (cache) cannot be erroneous, which requires that the storage unit storing the cache data (cache) must be intact. In step S100 and step S200, the first storage unit has been tested, and the first storage unit storing the cache data (cache) is guaranteed to be intact, so the cache data (cache) is only stored in the first storage unit. Figure 6A is a schematic diagram of a storage block according to an exemplary embodiment of the present application. As shown in Figure 6A, The storage block includes N storage units, wherein cache data and/or directed acyclic graph data can be stored in N-1 units. Exemplarily, cache data (cache) is only stored in the storage unit that passes the test, and if storage unit 3 fails the test, cache data (cache) data is not stored in storage unit 3, i.e., in storage unit 1, storage unit 2 ... storage unit N-1, the storage unit that passes the test is the first storage unit, and the storage unit that fails the test is the second storage unit. Further, the storage space of cache data (cache) is configured according to the divided first storage unit. If the number of storage units that pass the test in the storage block is M, i.e., the number of first storage units is M, wherein the storage space address depth of each storage unit is D, then the cache data in the storage space X of the storage unit satisfies: M*D*64/65≤X≤M*D-1. At the same time, the storage address table of the cache data is recorded, i.e., the corresponding physical address of the storage space for storing the cache data (cache) is configured, so that the cache data (cache) can be called according to the storage address table of the cache data when the directed acyclic graph data is subsequently calculated.

Step S400

In step S400, directed acyclic graph data can also be obtained according to the cache data, and the directed acyclic graph data is stored in the first storage unit and the second storage unit. FIG. 5 is a flow chart of a method for calculating directed acyclic graph data according to an exemplary embodiment of the present application. In an exemplary embodiment of the present application, as shown in FIG. 5, calculating directed acyclic graph data (dag) includes the following steps:

Step S320: reading cache data according to the storage address table of cache data;

Step S340: Calculate the length of the directed acyclic graph data;

Step S360: Calculating the directed acyclic graph data based on the length of the directed acyclic graph data and the read cache data; and

Step S380: Allocate storage space of the first storage unit and the second storage unit for storage according to the directed acyclic graph data.

In the process of calculating directed acyclic graph data, first read the cache data according to the storage address table of the cache data in step S390. Then, the length of the directed acyclic graph data can be calculated according to the number of configured storage blocks and the ETHASH algorithm, and the length of the directed acyclic graph data obtained by different training times is different, that is, the number of iterations of subsequent calculations is related to the length of the directed acyclic graph data. Then the directed acyclic graph data is calculated based on the length of the directed acyclic graph data and the cache data read, for example, based on the ETHASH algorithm, the length of the directed acyclic graph data and the cache data read are subjected to remainder, SHA3_512 or XOR and other related operations, and the calculation result of the directed acyclic graph data (dag) can be obtained.

In an exemplary embodiment of the present application, the storage space of the first storage unit and the second storage unit can also be allocated for storage according to the directed acyclic graph data (dag). According to the characteristics of the ETHASH algorithm, the hash value calculated based on the directed acyclic graph data (dag) can have a certain rejection rate, so the first storage unit and the second storage unit can store the directed acyclic graph data (dag).

In an exemplary embodiment of the present application, FIG6A is a schematic diagram of a storage block according to an exemplary embodiment of the present application. As shown in FIG6A , the storage block includes N storage units, wherein N-1 units can store cache data and/or directed acyclic graph data. Exemplarily, in storage unit 1, storage unit 2, ... storage unit N-1, by The storage unit tested is the first storage unit, and the storage unit that fails the test is the second storage unit. The storage space of the directed acyclic graph data (dag) is configured according to the divided first storage unit and/or second storage unit. If the number of storage units that pass the test in the storage block is M, that is, the number of first storage units is M, wherein the storage space address depth of each storage unit is D, the number of storage units storing directed acyclic graph data is L, and the storage space Y of the directed acyclic graph data in the storage unit satisfies: M*D*64/65≤Y≤L*D*64/65. Exemplarily, in the first storage unit, the address depth of the storage space of the cache data is the same, that is, the storage space of the cache data is located at one end of the first storage unit, which is convenient for the storage and reading of the cache data and improves the computing efficiency. FIG. 6B is a schematic diagram of a storage block according to another exemplary embodiment of the present application. As shown in FIG. 6B, the storage block includes N storage units, wherein cache data and/or directed acyclic graph data can be stored in N-1 units. Exemplarily, in storage unit 1, storage unit 2 ... storage unit N-1, the storage unit that passes the test is the first storage unit, and the storage unit that fails the test is the second storage unit. The storage space of the directed acyclic graph data (dag) is configured according to the divided first storage unit and/or second storage unit. If the number of storage units that pass the test in the storage block is M, that is, the number of first storage units is M, wherein the storage space address depth of each storage unit is D, the number of storage units storing directed acyclic graph data is L, and the storage space Y of the directed acyclic graph data in the storage unit satisfies: M*D*64/65≤Y≤L*D*64/65. Exemplarily, in the first storage unit, the address depth of the storage space of the cached data is different, that is, the storage space of the cached data is located in the designated storage space of the first storage unit, and the storage space can be allocated according to the specific circumstances.

According to an exemplary embodiment of the present application, based on the characteristics of cache data (cache) and directed acyclic graph data (dag), storage space of the storage unit is configured for the two types of data respectively, the cache data is only stored in the first storage unit, and the directed acyclic graph data is stored in the first storage unit and the second storage unit, thereby improving the utilization rate of the storage unit, that is, improving the chip's ability to store data, and to a certain extent increasing the chip's yield and computing power.

In an exemplary embodiment of the present application, the performance of the storage block can also be further determined by the hash value calculated by the directed acyclic graph data (dag) in the storage block. First, the number of second storage units contained in each storage block is obtained based on step S200. If the number of second storage units contained in a single storage block exceeds the predetermined value of computing power, the directed acyclic graph data stored in the storage block is ETHASH operated, and the operation result, i.e., the hash value, is obtained. When the operation result is greater than a specific difficulty value (also referred to as a target value, target), it is regarded as a rejection, so the rejection rate can be further calculated based on the number of data whose operation result is greater than the specific difficulty value and the number of overall data of the operation result, wherein the rejection rate is the ratio of the number of data whose operation result is greater than the specific difficulty value to the number of overall data of the operation result. If the rejection rate of the storage block is less than the preset value, the storage block stores data normally; if the rejection rate of the storage block is greater than or equal to the preset value, the storage block is not used for data storage, wherein the specific difficulty value and the preset value can be adjusted according to the computing power of the chip.

According to an exemplary embodiment of the present application, the performance of the storage block is tested again based on the number of second storage units contained in each storage block and the rejection rate of the storage block, thereby improving the utilization rate of the storage block, that is, improving the chip's ability to store data, and to a certain extent increasing the chip's yield and computing power.

On the other hand, the present application provides a data storage device 2000 based on the ETHASH algorithm. FIG7 is a schematic diagram of a data storage device 2000 based on the ETHASH algorithm according to an exemplary embodiment of the present application. As shown, the data storage device 2000 includes: a test module 2100, a classification module 2200, a cache data acquisition and storage module 2300, and a directed acyclic graph data acquisition and storage module 2400. Among them, the test module 2100 is used to test multiple storage units of the storage block and obtain test results. The classification module 2200 is used to classify the multiple storage units according to the test results, and divide them into a first storage unit and a second storage unit, wherein the first storage unit is a storage unit that has passed the test, and the second storage unit is a storage unit that has not passed the test. The cache data acquisition and storage module 2300 is used to acquire cache data and store the cache data in the first storage unit. The directed acyclic graph data acquisition and storage module 2400 is used to acquire directed acyclic graph data according to the cache data, and store the directed acyclic graph data in the first storage unit and/or the second storage unit.

The present application also provides an electronic device and a computer-readable storage medium. FIG8 is a schematic diagram of the structure of an electronic device 800 according to an exemplary embodiment of the present application. As shown in FIG8 , the electronic device 800 includes at least a processor 810 and a computer-readable storage medium 820. Among them, the processor 810 and the computer-readable storage medium 820 can be connected via a bus or other means. The computer-readable storage medium 820 is used to store a computer program 821, and the computer program 821 includes computer instructions. The processor 810 is used to execute the computer instructions stored in the computer-readable storage medium 820. The processor 810 is the computing core and control core of the electronic device 800, which is suitable for implementing one or more computer instructions, and is specifically suitable for loading and executing one or more computer instructions to implement the corresponding method flow or corresponding function.

As an example, the processor 810 may also be referred to as a central processing unit (CPU). The processor 810 may include, but is not limited to, a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

As an example, the computer-readable storage medium 820 may be a dynamic random access memory (DRAM), a high-speed RAM memory, or a non-volatile memory (Non-Volatile Memory), such as at least one disk memory; optionally, it may also be at least one computer-readable storage medium 820 located away from the aforementioned processor 810. Specifically, the computer-readable storage medium 820 includes, but is not limited to: a volatile memory and/or a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (SDRAM), and so on. Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Link Dynamic Random Access Memory (SLDRAM) and Direct Rambus RAM (DR RAM).

In one implementation, the electronic device 800 may be the chip 800 shown in FIG8 ; the computer readable storage medium 820 stores computer instructions; the processor 810 loads and executes the computer instructions stored in the computer readable storage medium 820 to implement the corresponding steps in the method embodiment shown in FIG1 . In a specific implementation, the computer instructions in the computer readable storage medium 820 are loaded by the processor 810 and the corresponding steps are executed, which will not be described here to avoid repetition.

According to another aspect of the present application, an embodiment of the present application further provides a computer-readable storage medium 820 (Memory), which is a memory device in the electronic device 800 for storing programs and data. For example, a computer-readable storage medium 820. It can be understood that the computer-readable storage medium 820 here can include both the built-in storage medium in the electronic device 800 and the extended storage medium supported by the electronic device 800. The computer-readable storage medium 820 provides a storage space, which stores the operating system of the electronic device 800. In addition, one or more computer instructions suitable for being loaded and executed by the processor 810 are also stored in the storage space, and these computer instructions can be one or more computer programs 821 (including program codes).

The electronic device 800 may further include: a transceiver 830, which may be connected to the processor 810 or the computer-readable storage medium 820. The computer-readable storage medium 820 may control the transceiver 830 to communicate with other devices. Specifically, information or data may be sent to other devices, or information or data sent by other devices may be received. The transceiver 830 may include a transmitter and a receiver, and may further include an antenna, and the number of antennas may be one or more.

According to another aspect of the present application, a computer program product or a computer program is provided, the computer program product or the computer program including computer instructions, the computer instructions being stored in a computer-readable storage medium 820. For example, a computer program 821. At this time, the electronic device 800 may be a computer, the processor 810 reads the computer instructions from the computer-readable storage medium 820, and the processor 810 executes the computer instructions, so that the computer executes the data storage method based on the ETHASH algorithm provided in the above-mentioned various optional manners.

In other words, when implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process of the embodiment of the present application is run in whole or in part or the function of the embodiment of the present application is implemented. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center.

The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of application involved in the present application is not limited to the technical features formed by a specific combination of the above technical features. The technical solutions should also include other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the application concept. For example, the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

A data storage method based on an ETHASH algorithm, wherein the ETHASH algorithm is based on a chip operation, wherein the chip includes a plurality of storage blocks, each of which includes a plurality of storage units, including:

Testing a plurality of storage units of the storage block and obtaining test results;

Classify the plurality of storage units according to the test result into a first storage unit and a second storage unit, wherein the first storage unit is a storage unit that has passed the test, and the second storage unit is a storage unit that has not passed the test;

Acquire cache data, and store the cache data in the first storage unit; and

The directed acyclic graph data is acquired according to the cache data, and the directed acyclic graph data is stored in the first storage unit and/or the second storage unit.
The method according to claim 1, wherein the method further comprises:

Obtaining the number of the second storage units included in the storage block, and comparing the number with a predetermined computing power value;

In response to the number of the second storage units included in the storage block exceeding the predetermined computing power value, performing an ETHASH operation on the directed acyclic graph data stored in the storage block, and obtaining an operation result; and

Based on the operation result, a rejection rate of the storage block is determined. If the rejection rate of the storage block is less than a preset value, the storage block is used for data storage. If the rejection rate of the storage block is greater than or equal to the preset value, the storage block is not used for data storage. The rejection rate is the ratio of the number of data whose operation results are greater than a specific difficulty value to the number of overall data of the operation results.
The method according to claim 1, wherein the step of obtaining cache data and storing the cache data in the first storage unit comprises:

Obtaining a training number, wherein the training number is a ratio of the number of storage blocks to a training length;

Perform training based on the ETHASH algorithm and the training times to obtain a seed;

Calculating the length of the cached data;

Calculating the cached data based on the seed and the length of the cached data; and

The storage space of the first storage unit is allocated according to the cache data for storage, and a storage address table of the cache data is recorded.
The method according to claim 3, wherein the step of obtaining directed acyclic graph data according to the cache data comprises:

Reading the cache data according to the storage address table of the cache data;

Calculating the length of the directed acyclic graph data; and

The directed acyclic graph data is calculated based on the length of the directed acyclic graph data and the read cache data.
The method according to claim 1, wherein the storage space X of the cache data in the storage unit satisfies:
M*D*64/65≤X≤M*D-1,

Wherein, M is the number of storage units that pass the test in the storage block, and D is the storage space address depth of the storage unit.
The method according to claim 1, wherein the directed acyclic graph data in the storage space Y of the storage unit satisfies:
M*D*64/65≤Y≤L*D*64/65,

Among them, M is the number of storage units that pass the test in the storage block, D is the storage space address depth of the storage unit, and L is the number of storage units that store the directed acyclic graph data.
The method according to claim 1, wherein the step of testing the storage area of the chip and obtaining the test result comprises:

Writing initial test data into the storage unit, wherein the initial test data includes a known pseudo-random sequence; and

The data of the storage unit is read, and the data of the storage unit is compared with the initial test data. If the data of the storage unit is the same as the initial test data, the test result of the storage unit is passed; if the data of the storage unit is different from the initial test data, the test result of the storage unit is failed.
The method according to claim 7, wherein after classifying the plurality of storage units into first storage units and second storage units according to the test results, the method further comprises:

performing error checking and correction on the data stored in the second storage unit; and

The corrected data is compared with the initial test data, and if the corrected data is the same as the initial test data, the second storage unit is re-divided into the first storage unit.
A data storage device based on an ETHASH algorithm, wherein the ETHASH algorithm is run on a chip, wherein the chip includes a plurality of storage blocks, each of which includes a plurality of storage units, including:

A test module, used for testing a plurality of storage units of the storage block and obtaining a test result;

A classification module, used for classifying the plurality of storage units according to the test result into first storage units and second storage units, wherein the first storage units are storage units that have passed the test, and the second storage units are storage units that have not passed the test;

a cache data acquisition and storage module, configured to acquire cache data and store the cache data in the first storage unit; and

A directed acyclic graph data acquisition and storage module, used to acquire the directed acyclic graph data according to the cache data The directed acyclic graph data is stored in the first storage unit and/or the second storage unit.
An electronic device, comprising:

a processor adapted to execute a computer program; and

A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by the processor, the method according to any one of claims 1 to 8 is implemented.
A computer-readable storage medium for storing a computer program, wherein the computer program enables a computer to execute the method according to any one of claims 1 to 8.