CN115083504B - Chip self-inspection method and chip - Google Patents
Chip self-inspection method and chip Download PDFInfo
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
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Abstract
A chip self-checking method and a chip are provided, the chip comprises a self-checking module and a storage module, and the chip self-checking method comprises the following steps: the self-checking module receives externally input address configuration parameter information and data configuration parameter information; the self-checking module determines a storage module to be detected according to the address configuration parameter information; the self-checking module performs data filling on the storage module according to the data configuration parameter information; the self-checking module sends a reading request to a storage module to be detected and receives data returned by the reading request; and the self-checking module compares whether the data returned by the read request is the same as the filled data, and determines whether the detection of the storage module is passed according to the comparison result. The storage module which works abnormally in the chip can be accurately positioned, so that the fault of the chip is conveniently checked, and the rejection rate of the chip is reduced.
Description
Technical Field
The embodiment of the disclosure relates to but is not limited to the technical field of chip design, and particularly relates to a chip self-inspection method and a chip.
Background
With the continuous development of chip processes, the number of units integrated in a chip is increasing, but due to the limitation of chip manufacturing processes, the yield of the units integrated in the chip is problematic.
Therefore, how to provide a chip self-inspection method is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the disclosure provides a chip self-checking method, wherein the chip comprises a self-checking module and a storage module, and the chip self-checking method comprises the following steps:
the self-checking module receives externally input address configuration parameter information and data configuration parameter information;
the self-checking module determines a storage module to be detected according to the address configuration parameter information;
the self-checking module performs data filling on the storage module according to the data configuration parameter information;
the self-checking module sends a reading request to a storage module to be detected and receives data returned by the reading request;
and the self-checking module compares whether the data returned by the read request is the same as the filled data, and determines whether the detection of the storage module is passed according to the comparison result.
The embodiment of the disclosure further provides a chip, which includes a self-test module and a storage module, wherein the self-test module uses the chip self-test method according to any one of the embodiments of the disclosure to detect the storage module.
According to the chip self-checking method and the chip, the storage modules are detected through the self-checking module according to the externally input address configuration parameter information and data configuration parameter information, whether any one of the storage modules in the chip works normally can be accurately detected, the storage module which works abnormally in the chip can be accurately positioned, chip faults can be conveniently checked, the storage module which has a problem can be closed according to the self-checking result, the chip can still work continuously, and the rejection rate of the chip is reduced.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
Fig. 1 is a schematic flow chart diagram of a chip self-inspection method according to an exemplary embodiment of the disclosure;
FIG. 2 is a schematic diagram of a chip according to an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a crossbar switch according to an exemplary embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating an address arrangement of a memory module according to an exemplary embodiment of the disclosure;
5-8 are diagrams illustrating four read request access addresses according to an exemplary embodiment of the disclosure;
FIG. 9 is a schematic diagram of a data filling method according to an exemplary embodiment of the disclosure;
fig. 10 to 13 are schematic diagrams of four crossbar defects according to exemplary embodiments of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present disclosure belongs. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and the equivalent thereof, but does not exclude other elements or items.
The embodiment of the disclosure provides a chip self-inspection method, wherein the chip comprises a self-inspection module and a storage module, and as shown in fig. 1, the chip self-inspection method comprises the following steps:
step 101: the self-checking module receives externally input address configuration parameter information and data configuration parameter information;
step 102: the self-checking module determines a storage module to be detected according to the address configuration parameter information;
step 103: the self-checking module performs data filling on the storage module according to the data configuration parameter information;
step 104: the self-checking module sends a reading request to a storage module to be detected and receives data returned by the reading request;
step 105: and the self-checking module compares whether the data returned by the reading request is the same as the filled data or not, and determines whether the storage module passes the detection or not according to the comparison result.
According to the chip self-checking method disclosed by the embodiment of the invention, whether any one storage module in the chip works normally can be accurately detected, so that the storage module which works abnormally in the chip can be accurately positioned, the fault of the chip can be conveniently checked, and the storage module which has a problem can be closed subsequently according to the self-checking result, so that the chip can still work continuously, and the rejection rate of the chip is reduced.
In step 105, when the self-checking module compares whether the data returned by the read request is the same as the filled data, the filled data can be obtained by: by performing the calculation based on the configuration parameter information using the same calculation procedure as in step 103, the padded data can be obtained.
In the embodiment of the disclosure, the self-checking module is used for detecting production defects of the storage module and/or the crossbar switch, and comprises two basic functions of detection data generation and detection data comparison.
In some exemplary embodiments, as shown in fig. 2, the chip further comprises a Crossbar (CB) comprising M first interfaces (ingress) and N second interfaces (egress), one second interface being connected to one memory module, at least one first interface being connected to one self-test module, the crossbar comprising one or more layers of a fully connected network.
In the embodiment of the present disclosure, the mxn crossbar includes full-communication paths from M first interfaces to N second interfaces. The self-test module may instantiate at any one or more of the first interface 0 to the first interface M-1.
Illustratively, as shown in fig. 3, the crossbar includes 3 fully-connected networks, the 0 th layer includes 5 6 × 6 sub-crossbars CB0_6 × 0 to CB0_6 × 4, the 1 st layer includes 6 5 × 5 sub-crossbars CB1_5 × 5 to CB1_5 × 5, the 2 nd layer includes 30 1 × 26 sub-crossbars CB2_1 × 26 0 to CB2_1 × 26, and the three sub-crossbars constitute 30 × 780 crossbars.
In some exemplary embodiments, each memory module includes D addresses, D is a natural number greater than 1, and the addresses 0 to N × D-1 are consecutive, and the xth address of the memory module is an address N × y + x, x is a natural number between 0 and N-1, and y is a natural number between 0 and D-1.
In the embodiment of the disclosure, addresses are arranged for the memory modules connected to the crossbar switch, and each address corresponds to one data position of one memory module. As shown in FIG. 4, D is the number of addresses inside each memory module, and the address N D-1 is the last address, with consecutive intermediate addresses. The data of the memory module in the dotted line frame of fig. 4 is referred to as a row of data, i.e., the same row of all memory modules is collectively referred to as a common row D. According to the chip self-inspection method disclosed by the embodiment of the disclosure, by transversely arranging the addresses, when a certain storage module is damaged, because the addresses in the storage module are discontinuous, a situation that a series of addresses are all bad does not occur for a continuous address space, and thus the bad influence caused by damage of the storage module can be reduced.
Although the embodiment of the present disclosure is described by taking address horizontal layout as an example, it should be noted that the chip self-checking method of the embodiment of the present disclosure is also applicable to the case of address vertical layout, when the address vertical layout is performed, the xth address of the memory module x is the address x × D + y, x is a natural number between 0 and N-1, and y is a natural number between 0 and D-1.
In some exemplary embodiments, the externally input address configuration parameters include: detecting a starting address start _ addr, an address jump small step addr _ step, a small step time addr _ seg, an address jump large step addr _ seg _ step and a total detection time step _ num.
The detection starting address start _ addr is used for identifying the starting address of the self-detection storage module, and can be any address between 0 and N x D-1; the address jump small step addr _ step is used for identifying a step value between addresses of the storage modules to be detected in the jump range of each round of small step times; the address jump large step addr _ seg _ step is used for identifying a step value between the address of the memory module to be detected after each round of small step number detection is completed and the address of the currently detected memory module when the total detection number is greater than the small step number.
The self-checking module can flexibly configure the detection position by setting the following address configuration parameters and combining different address configuration parameters.
Detecting the start address start _ addr: the starting address of the self-test detection can be any address between 0 and N x D-1.
Address jump small step addr _ step: and (3) small stepping of an address jump of the access request, and adding the address jump small stepping addr _ step on the basis of the last address when the self-test module sends the access request each time.
Small step number addr _ seg: and taking the address jump small step addr _ step as the interval stepping times, and performing a large step after the jump times reach the small step times addr _ seg.
Address jump large step addr _ seg _ step: and after the small stepping times addr _ seg are carried out for the small stepping times, the access request address can carry out one-time jump according to the interval. The upper limit of the parameter is N × D, and if the parameter is configured to be N × D, the access request after the step jump from the current address is the current address.
Total number of detection times step _ num: and total detection times of the access addresses.
In the embodiment of the disclosure, when accessing the address N × D-1, if the address is added by 1, the next access address is address 0.
In the disclosed embodiment, if address a is accessed, stepping N × D, the next request is still a.
In some exemplary embodiments, step 102 comprises:
the self-checking module compares the value of the small stepping times with the value of the total detection times;
when the value of the small stepping times is larger than or equal to the value of the total detection times, the self-checking module determines that the number of rounds to be detected is one round, the initial address of the storage module to be detected in the round is the value of the detection initial address, the stepping values among the addresses of the storage modules to be detected in the round are the values of address jump small stepping, and the times to be detected in the round are the values of the total detection times;
when the value of the small stepping times is smaller than the value of the total detection times, the self-checking module determines that the number of turns to be detected is n turns, wherein n =8968, the total detection times/the small stepping times of 8969; \\ 8968; \ 8969h indicates an operator for rounding upwards, the start address of the memory module to be detected in the first turn is the value of the detection start address, the start address of the memory module to be detected in the ith turn is the sum of the address of the last detected memory module in the ith-1 turn and the value of the address jump large stepping, and i is a natural number between 2 and n; the step value between the addresses of the memory modules to be detected in each round is the value of the address jump small step; the number of times to be detected in the first n-1 round is a value of the number of small steps, the number of times to be detected in the nth round is m, and m = the total number of times to be detected- (n-1) × the number of small steps.
When the chip self-inspection method provided by the embodiment of the disclosure is actually used, the situation that the value of the small stepping times is larger than the value of the total inspection times generally does not occur.
In some exemplary embodiments, the chip self-test method further includes:
the self-checking module is provided with N flag bits, and each flag bit is used for identifying whether the detection of partial addresses in one storage module or the detection of all addresses in one storage module passes or not.
The following four sets of address configuration parameters are taken as an example to illustrate the chip self-test method according to the embodiment of the disclosure.
Example 1: taking the address configuration parameters shown in table 1 as an example, the self-checking module determines, according to the address configuration parameters shown in table 1, the number of times of detection and the memory module to be detected as follows: the data 1 pass of the 0 th row of the N memory modules is detected, as shown in fig. 5, the destination address of the 0 th read request is the 0 th row of data of the memory module 0, the destination address of the 1 st read request is the 0 th row of data of the memory module 1, \ 8230; \ 8230;, and the destination address of the N-1 th read request is the 0 th row of data of the memory module N-1. Of all the N flag bits, a bit of 1 indicates that the row 0 function of the corresponding memory module is not defective, and a bit of 0 indicates that the row 0 function of the corresponding memory module is defective.
TABLE 1
| |
0 |
| |
1 |
| addr_seg | N |
| addr_seg_step | Don’t care |
| step_num | N |
Example 2: taking the address configuration parameters shown in table 2 as an example, the self-checking module determines the detection times and the storage module to be detected according to the address configuration parameters shown in table 2 as follows: the data P pass of all addresses is detected, as shown in FIG. 6, the destination address of the 0 th read request is the 0 th row data of the memory module 0, the destination address of the 1 st read request is the 0 th row data of the memory module 1, \8230 \ 8230;, the destination address of the Nth read request is the 1 st row data of the memory module 0, \8230;, the destination address of the Nth D-1 read request is the D-1 th row data of the memory module N-1, \8230;, the destination address of the (P-1) N D read request is the 0 th row data of the memory module 0, \\ 8230;, the destination address of the P \\ N _ D-1 read request is the D-1 th row data of the memory module N-1. And the bit of 1 in all the N flag bits indicates that all the data functions of the corresponding memory module are not defective, and the bit of 0 indicates that at least one address of all the address functions of the corresponding memory module is defective.
TABLE 2
| |
0 |
| |
1 |
| addr_seg | N* |
| addr_seg_step | |
| 1 | |
| step_num | P*N*D |
Example 3: taking the address configuration parameters shown in table 3 as an example, the self-checking module determines the detection times and the storage module to be detected according to the address configuration parameters shown in table 3 as follows: as shown in FIG. 7, the destination address of the 0 th read request is the J-th row data of the memory module 0, the destination address of the 1 st read request is the J-th row data of the memory module 1, \8230 \ 8230;, the destination address of the N-1 th read request is the J-th row data of the memory module N-1, the destination address of the Nth read request is the J-th row data of the memory module 0, \8230;, the destination address of the 2 Nth read request is the J-th row data of the memory module 0, \8230;, the destination address of the (K-1) _ N read request is the J-th row data of the memory module 0, and the destination address of the (K-1) _ N +1 read request is the J-th row data of the memory module 1, \\ 8230;, and the destination address of the K-1) _ N +1 th read request is the J-th row data of the memory module 1. And a bit of 1 in all the N flag bits indicates that the J-th row data function of the corresponding memory module is not defective, and a bit of 0 indicates that the J-th row data function of the corresponding memory module is defective.
TABLE 3
| start_addr | J* |
| addr_step | |
| 1 | |
| addr_seg | N |
| addr_seg_step | N*（D-1）+1 |
| step_num | K*N |
Example 4: taking the address configuration parameters shown in table 4 as an example, the self-checking module determines, according to the address configuration parameters shown in table 4, the detection times and the storage module to be detected as follows: all address data in the memory module X are detected for 1 pass, as shown in fig. 8, the destination address of the 0 th read request is the 0 th line data of the memory module X, the destination address of the 1 st read request is the 1 st line data of the memory module X, \8230;, and the destination address of the D-1 th read request is the D-1 th line data of the memory module X. The flag bit X is 1, which indicates that all address data functions of the memory module X are not defective, and the flag bit X is 0, which indicates that at least one address data function of all address data of the memory module X is defective.
TABLE 4
| start_addr | X |
| addr_step | N |
| addr_seg | D |
| addr_seg_step | Don’t care |
| step_num | D |
In some exemplary embodiments, the data configuration parameter information includes start padding data and data padding steps, the data padded at the address a is { start padding data + data padding step a }, and a is a natural number between 0 and N × D-1.
In some exemplary embodiments, when the value of the externally input start padding data is less than the bit width of the data stored in the address of each memory module, the chip self-test method further includes:
the self-checking module is according to at least one of the following methods: high-order complement 0 and high-order complement 1, copying and splicing the externally input initial filling data, and performing data bit expansion on the initial filling data, wherein the bit of the expanded initial filling data is equal to the bit width of the data stored in the address of each storage module.
In the embodiment of the disclosure, the self-checking module can flexibly configure the data excitation value by setting the data configuration parameter information and the combination of different parameters.
Start padding data start _ data: the data padding is extended E times and then padded to address 0 (E is a fixed value, the extension is designed to save the bit width of the parameter, and here, copy and splice are performed on the externally input initial padding data as an example, but the embodiment of the present disclosure does not limit this.
Data padding step data _ step: the step of data padding is used to calculate the data of each address padding, and the data of the address i is padded is { E { start _ data + data _ step × i } } (syntax of verilog programming language).
For example, assuming that each address of the storage device stores 1024 bits of data and the starting padding data start _ data bit width is 32 bits, E =32, i.e. it needs to be extended 32 times. As shown in fig. 9, 1024bit data {32 located 32' h5a5a5a } } (syntax of verilog programming language) is stored into the address 0 of the storage module 0, wherein 32' h5a5a5a represents the 16-system number 5a5a5a of 32bit, and {32 parent 32' h5a5a5a5a } represents that 32 copies of 5a5a5a5a are spliced into 1024bit data.
The following three sets of data configuration parameters are taken as an example to illustrate the chip self-test method according to the embodiment of the disclosure.
Example 5: taking the data configuration parameters shown in table 5 as an example, the self-checking module expands the address value as the storage data according to the data configuration parameters shown in table 5.
TABLE 5
| start_data | 32’h0 |
| data_step | 1 |
Example 6: taking the data arrangement parameter shown in Table 6 as an example, the self-inspection module stores all of 32' h5a5a5a5a } in all the addresses according to the data arrangement parameter shown in Table 6.
TABLE 6
| start_data | 32’ |
| data_step | |
| 0 |
Example 7: taking the data configuration parameters shown in table 7 as an example, the self-test module stores data (random combination) of all addresses according to the data configuration parameters shown in table 7.
TABLE 7
| start_data | 32’ ha0b1c2d3 |
| data_step | 123 |
In some exemplary embodiments, the self-test module performs data filling on the storage module according to the data configuration parameter information, and the data filling includes any one of the following:
the self-checking module performs data filling on all addresses of all storage modules according to the data configuration parameter information;
the self-checking module performs data filling on all addresses of the storage module to be detected according to the data configuration parameter information;
and the self-checking module performs data filling on the address to be detected of the storage module to be detected according to the data configuration parameter information.
In some exemplary embodiments, the self-test module performs multiple sets of tests on the memory module to be tested, the multiple sets of tests including: the method comprises the steps of performing write 0 detection on each bit of each address, performing write 1 detection on each bit of each address, performing write 0 first and then write 1 detection on each bit of each address, and performing write 1 first and then write 0 detection on each bit of each address. Through the detection of the multiple groups, the error reasons of the storage module can be accurately positioned.
In some exemplary embodiments, the read request of the introspection module supports multithreading, and T threads can be started simultaneously and concurrently detected, where T is a natural number greater than 1.
In some exemplary embodiments, the self-test module performs the self-test on the storage module using the following self-test procedures:
1) Filling storage module
According to the value expansion of the start _ data/data _ step, filling the memory module (for example, the memory module can be a DRAM), wherein the address 0 is filled with the start _ data + data _ step 0, the address 1 is filled with the start _ data + data _ step 1, the address N is filled with the start _ data + data _ step N, and all the memory modules are filled (default expansion).
In other exemplary embodiments, the address of the memory module to be detected may also be determined according to the value of the address configuration parameter, and the address of the memory module to be detected is only subjected to data padding, which is not limited by the embodiment of the present disclosure.
2) Sending read requests to specified addresses
The self-checking module starts to send the read request from start _ addr, when the number of the requests reaches addr _ seg, the address is requested to be increased by addr _ seg _ step, otherwise, the address is requested to be increased by addr _ step until the number of the requests reaches step _ num, and the read request is stopped to be sent.
This process may be multi-threaded concurrent.
3) Comparison of self-test results
And comparing the returned data rdata with expected data calculated in the self-checking module, wherein the same data indicates that the check passes and the different data indicates that the check fails. If a certain access request is not returned after exceeding the preset time (wait _ delay), the address detection of the access request is also failed.
4) Self-test result recording
The self-checking module comprises N result flag bits with 1bit, wherein the value of each result flag bit is 1 to indicate that the detection is passed, and 0 to indicate that the detection is failed.
In some exemplary embodiments, the chip self-test method further includes:
and the self-checking module determines whether a connection network in the cross switch and a path between the second interface and the storage module are communicated or not according to the detection result of the storage module.
For example, assume that the crossbar is 30 × 780, layer 0: 5 6 × 6 sub-crossbars; layer 1: 6 5 × 5 sub-crossbars; layer 2: 30 1 × 26 sub-crossbars; a storage module: 780, the following sets of crossbar defects are taken as an example (assuming that there are no defects in all memory modules) to illustrate the chip self-test method according to the embodiments of the present disclosure.
Example 8: as shown in fig. 10, it is assumed that the crossbar defect position is the 26 th exit position of the layer 2 sub-crossbar CB2_1 × 26 0, i.e., the fork (X) position in fig. 10.
When the self-checking is performed, the position of the self-checking module may be located at any entrance (i.e. a first interface) of the cross bar switch, the self-checking module detects the access condition of a path from the entrance (i.e. the first interface) of the cross bar switch to all exits (i.e. a second interface) of the cross bar switch, and the detection results of all the self-checking modules are as follows:
780 flag bits: the 26 th bit is 0, and the others are 1.
Example 9: as shown in fig. 11, it is assumed that the crossbar defect position is a position between the 1 st outlet of the 1 st-layer sub-crossbar CB1_5 × 5 0 and the 1 st inlet of the 2 nd-layer sub-crossbar CB2_1 × 26 0, i.e., a position of a fork (X) in fig. 11.
When the self-checking is performed, the position of the self-checking module may be located at any entrance (i.e. a first interface) of the cross bar switch, the self-checking module detects the access condition of a path from the entrance (i.e. the first interface) of the cross bar switch to all exits (i.e. a second interface) of the cross bar switch, and the detection results of all the self-checking modules are as follows:
780 flag bits: { {754 carbide 1'b1} }, {26 carbide 1' b0} }.
According to the chip self-checking method, whether a connection network in the cross switch and a path between the second interface and the storage module are communicated or not is determined according to the detection result of the storage module, so that the production defects of the cross switch can be detected, the chip faults can be conveniently checked, the storage module with the problems or the storage module connected with the part of the cross switch with the problems can be closed according to the self-checking result, the chip can still continue to work, and the rejection rate of the chip is reduced.
The embodiment of the disclosure further provides a chip, which includes a self-test module and a storage module, wherein the self-test module uses the chip self-test method according to any embodiment of the disclosure to detect the storage module.
In some exemplary embodiments, the self-checking module includes a plurality of self-checking modules, the chip further includes a crossbar switch, the crossbar switch includes M first interfaces and N second interfaces, one second interface is connected to one storage module, at least one first interface is connected to one self-checking module, and the chip is configured to determine whether a path between the self-checking module and the first interface, a connection network in the crossbar switch, and a path between the second interface and the storage module are connected according to positions of the plurality of self-checking modules and detection results of the plurality of self-checking modules.
Illustratively, still with the crossbar switch 30 × 780, layer 0: 5 6 × 6 sub-crossbars; layer 1: 6 5 × 5 sub-crossbars; layer 2: 30 1 × 26 sub-crossbars; a storage module: 780 as an example, the following sets of crossbar defects are taken as examples (assuming that there are no defects in all memory modules) to illustrate the chip self-test method of the embodiment of the present disclosure.
Example 10: as shown in fig. 12, it is assumed that the crossbar defect position is a position between the 2 nd outlet of the 0 th sub-crossbar CB0_6 × 6 0 and the 1 st inlet of the 1 st sub-crossbar CB1_5 × 5, i.e., a position of a fork (X) in fig. 12.
When the self-test is performed, the self-test modules located at all the inlets (i.e. the first interface) of the sub-crossbar CB0_6 × 6 0 detect the access condition of the paths from the inlet of the crossbar to all the outlets (i.e. the second interface) of the crossbar, and the detection result is as follows:
780 flag bits: { {520 cemented 1' b1} }, {130 cemented 1' b0} }, {130 cemented 1' b1} }.
The self-test module located outside all the inlets (i.e. the first interface) of the sub-crossbar CB0_6 x 6 0 detects the access condition of the path from the inlet of the crossbar to all the outlets (i.e. the second interface) of the crossbar, and the detection result is as follows:
780 flag bits: all 1.
Example 11: as shown in fig. 13, it is assumed that the crossbar defect position is the 1 st entry position of the 0 th sub-crossbar CB0_6 × 6 0, i.e., the fork (X) position in fig. 13.
When the self-test is performed, the self-test module located at the first inlet (i.e. the first interface) of the sub-crossbar CB0_6 × 6 0 detects the access condition of the path from the inlet (i.e. the first interface) of the crossbar to all outlets (i.e. the second interface) of the crossbar, and the detection result is as follows:
780 flag bits: all 0 s.
The self-test module located outside the first inlet (i.e. the first interface) of the sub-crossbar CB0_6 × 6 0 detects the access of the path from the inlet (i.e. the first interface) of the crossbar to all the outlets (i.e. the second interface) of the crossbar, and the detection result is:
780 flag bits: all 1.
The self-checking module of the embodiment of the disclosure can instantiate the function of checking any address of the interface accessing the N memory modules at any one or more positions in the M first interfaces of the crossbar switch. In addition, the self-checking module of the embodiment of the disclosure can perform multi-thread detection, and improve the detection speed. By configuring address configuration parameter information and data configuration parameter information, the self-checking module of the embodiment of the disclosure can send out any value within a detection excitation range; continuous detection can be initiated on any specified address; repeated detection can be initiated on any specified storage module; the whole address depth of the memory module connected with the crossbar switch can be covered; any address arrangement mode in the memory module can be tested.
In the description of the embodiments of the present disclosure, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, a fixed connection, a detachable connection, or an integral connection unless otherwise explicitly stated or limited; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure, and that the scope of the present disclosure shall be limited only by the terms of the appended claims.
Claims (9)
1. A chip self-checking method is characterized in that the chip comprises a self-checking module, a cross switch and a storage module, the cross switch comprises M first interfaces and N second interfaces, one second interface is connected with one storage module, at least one first interface is connected with one self-checking module, the cross switch comprises one or more layers of fully-connected networks, and the chip self-checking method comprises the following steps:
the self-checking module receives externally input address configuration parameter information and data configuration parameter information;
the self-checking module determines a storage module to be detected according to the address configuration parameter information;
the self-checking module carries out data filling on the storage module according to the data configuration parameter information;
the self-checking module sends a reading request to a storage module to be detected and receives data returned by the reading request;
the self-checking module compares whether the data returned by the read request is the same as the filled data, and determines whether the detection of the storage module is passed according to the comparison result;
and the self-checking module determines whether the fully-connected network in the cross switch and the path between the second interface and the storage module are communicated or not according to the detection result of the storage module.
2. The chip self-test method according to claim 1, wherein the address configuration parameters comprise: detecting a starting address, small address jump steps, small step times, large address jump steps and total detection times; the self-checking module determines the storage module to be detected according to the address configuration parameter information, and the method comprises the following steps:
the self-checking module compares the value of the small stepping times with the value of the total detection times;
when the value of the small stepping times is larger than or equal to the value of the total detection times, the self-detection module determines that the number of rounds to be detected is one round, the initial address of the storage module to be detected in the round is the value of the detection initial address, the stepping value between the addresses of the storage modules to be detected in the round is the value of the address jump small stepping, and the times to be detected in the round is the value of the total detection times;
when the value of the small stepping times is smaller than the value of the total detection times, the self-detection module determines that the number of turns to be detected is n turns, wherein n =/8968the total detection times/the small stepping times/896980, \68 \ 896983;, which represents an operator of rounding-up, the starting address of the memory module to be detected in the first turn is the value of the detection starting address, the starting address of the memory module to be detected in the ith turn is the sum of the address of the last detected memory module in the ith-1 turn and the value of the address jump large stepping, and i is a natural number between 2 and n; the step value between the addresses of the memory modules to be detected in each round is the value of the address jump small step; the number of times to be detected in the first n-1 round is a value of the number of small steps, the number of times to be detected in the nth round is m, and m = the total number of times to be detected- (n-1) × the number of small steps.
3. The chip self-test method according to claim 1, wherein the number of the memory modules is N, each of the memory modules includes D addresses, D is a natural number greater than 1, the addresses 0 to N x D-1 are consecutive, the xth address of the memory module is an address N x y + x, x is a natural number between 0 and N-1, and y is a natural number between 0 and D-1.
4. The method according to claim 3, wherein the data configuration parameter information comprises start padding data and data padding step, the data padded at address a is { start padding data + data padding step a }, and a is a natural number between 0 and N D-1.
5. The chip self-test method according to claim 3, further comprising:
the self-checking module is provided with N flag bits, and each flag bit is used for identifying whether the detection of partial addresses or all addresses in one storage module passes or not.
6. The chip self-test method according to claim 3, wherein the self-test module performs data filling on the storage module according to data configuration parameter information, and the method includes any one of the following steps:
the self-checking module performs data filling on all addresses of all the storage modules according to data configuration parameter information;
the self-checking module performs data filling on all addresses of the storage module to be detected according to the data configuration parameter information;
and the self-checking module performs data filling on the address to be detected of the storage module to be detected according to the data configuration parameter information.
7. The chip self-test method according to claim 1, wherein the self-test module performs a plurality of sets of tests on each address of the memory module to be tested, the plurality of sets of tests including: the method comprises the steps of performing write 0 detection on each bit of each address, performing write 1 detection on each bit of each address, performing write 0 first and then write 1 detection on each bit of each address, and performing write 1 first and then write 0 detection on each bit of each address.
8. A chip comprising a self-test module, a cross bar switch and a memory module, wherein the cross bar switch comprises M first interfaces and N second interfaces, one second interface is connected to one memory module, at least one first interface is connected to one self-test module, the cross bar switch comprises one or more layers of fully connected networks, and the self-test module tests the memory module using the chip self-test method according to any one of claims 1 to 7.
9. The chip according to claim 8, wherein the self-test modules comprise a plurality of self-test modules, and the chip is configured to determine whether paths between the self-test modules and the first interface, a fully-connected network in the cross-bar switch, and paths between the second interface and the storage module are connected according to positions of the self-test modules and detection results of the self-test modules.
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| CN202210865999.0A CN115083504B (en) | 2022-07-22 | 2022-07-22 | Chip self-inspection method and chip |
| PCT/CN2023/101921 WO2024016939A1 (en) | 2022-07-22 | 2023-06-21 | Chip self-checking method and chip |
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| CN115292114B (en) * | 2022-10-09 | 2022-12-09 | 中科声龙科技发展（北京）有限公司 | Data storage method, device, equipment and storage medium based on ETHASH algorithm |
| CN115328718B (en) * | 2022-10-17 | 2023-08-01 | 中科声龙科技发展（北京）有限公司 | Method for controlling on-chip computing system, on-chip computing system and chip |
| CN117711473B (en) * | 2024-02-06 | 2024-05-14 | 南京扬贺扬微电子科技有限公司 | Self-checking data management system and method based on memory device |
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| CN107808685B (en) * | 2017-11-28 | 2020-10-30 | 聚辰半导体股份有限公司 | Programming failure self-detection circuit and method for non-contact card chip |
| CN113496746B (en) * | 2020-04-03 | 2024-05-14 | 澜起科技股份有限公司 | Apparatus and method for detecting defect of memory module and memory system |
| CN115083504B (en) * | 2022-07-22 | 2022-11-01 | 中科声龙科技发展（北京）有限公司 | Chip self-inspection method and chip |
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