CN106356102B - ATE digital test system and self-checking method thereof - Google Patents
ATE digital test system and self-checking method thereof Download PDFInfo
- Publication number
- CN106356102B CN106356102B CN201610867908.1A CN201610867908A CN106356102B CN 106356102 B CN106356102 B CN 106356102B CN 201610867908 A CN201610867908 A CN 201610867908A CN 106356102 B CN106356102 B CN 106356102B
- Authority
- CN
- China
- Prior art keywords
- self
- address
- memory
- checking
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses an ATE digital test system and a self-checking method thereof. The invention effectively solves the problem that the traditional self-checking mode does not verify, the graph used for self-checking comprises special instructions except one, such as circulation, jump, block circulation and the like, then monitors the running track of the graph, and observes whether the address changes correspondingly according to each micro instruction under high-speed running, thereby verifying the performance of the system and whether the logic of the micro instruction part is normal. The potential problems which cannot be found by the traditional self-test can be reflected to a greater extent, so that the factory equipment is more stable, the failure rate is smaller, and the problems can be found by targeted interference elimination in the field failure.
Description
Technical Field
The invention belongs to the technical field of ATE digital test systems, and particularly relates to an ATE digital test system and a self-checking method thereof.
Background
The self-checking method is used for a digital testing system in the ATE field, self-checking is indispensable in detection before delivery and debugging after delivery, the purpose of self-checking is to fully expose potential problems, and traditional self-checking projects comprise memory self-checking, driver loop-back self-checking and the like. The self-checking of the memory is to write data into the memory in the board, read out and judge whether the data are consistent, and mainly verify whether the function of the memory is good. The driver loop-back self-test is to output a simple graph from the driver, return the graph to the driver through an internal or external path for comparison, and finally see whether the comparison result is consistent with the expected result. Although these conventional self-test items verify that the associated hardware is functioning properly, there is no verification of performance and some critical logic, such as whether the various micro-instructions are functioning properly and whether some micro-instructions are functioning properly at high speed. These conditions, which are often used in practice, can easily cause product hazards if verification is not performed.
Disclosure of Invention
The invention aims to: aiming at the defects existing in the prior art, the invention aims to provide an ATE digital test system, so that factory equipment is more stable, the failure rate is smaller, and the problem of targeted interference elimination and finding in field failure is easier. It is another object of the present invention to provide a self-test method of the above ATE digital test system.
The technical scheme is as follows: in order to achieve the above object, the present invention adopts the following technical scheme:
an ATE digital test system comprises an address generator, a graphic memory, an instruction memory, a self-checking memory and a driver, wherein the address generator is connected with the graphic memory, the instruction memory and the self-checking memory, the self-checking memory is connected with a bus, and the graphic memory is connected with the driver.
The self-checking memory adopts IS61LV12824 product of ISSI company, and IS 128K 24 bit static memory.
The address generator is the product of EP1C6Q240C8 of ALTERA company, and the main function is to generate addresses.
The self-checking method of the ATE digital test system includes that a self-checking pattern which is coded in advance is stored in a pattern memory and an instruction memory at first in the self-checking process, when the system runs, an address generator reads a first instruction to determine how to do next, an address generator following a designated action sends a new address to the instruction memory to generate a next instruction, and meanwhile, the address is sent to the self-checking memory to be stored as data, and the address of the self-checking memory is increased by one;
according to the micro instruction, the address makes corresponding change, when the self-checking execution is completed, after the address is all sequentially stored in the self-checking memory, the content in the self-checking memory is read onto a bus and is transmitted to a computer; and comparing the read address sequence with the correct address sequence, and judging whether the address in actual operation changes correctly according to the micro instruction.
In the self-checking method of the ATE digital test system, a 17-bit counter is arranged in the address generator, 17 bits correspond to 128K of the self-checking memory, the counter is clocked by the same system clock as a normal address generator, and when each beat period starts, the address is added by one first, and then corresponding data is stored.
The self-checking method of the ATE digital test system is characterized in that the instructions are stored in a memory in the form of machine codes, and are realized by writing micro instructions in a graph when the instructions are operated, wherein the micro instructions corresponding to the used instructions are as follows:
adding one: the address is taken by one step, namely one is added sequentially;
and (3) circulation: stay at the current address until the cycle number of stay equals to the set cycle number, then continue to execute the next instruction;
and (3) jumping: changing the address to the set address, and continuing to execute from the new position after the jump;
block loop/block loop times: the block circulation is a certain section of integral circulation, which needs to be set from the start circulation, and the circulation is from the start position to the block circulation instruction; the number of circulation times is set, namely, how many times the whole block circulates, the block circulation instruction can judge whether the current circulation times reach the set number of times, and when the circulation times reach the set circulation times, the block circulation instruction is continuously executed downwards when the instruction is circulated;
ending: the micro instruction typically acts as the last sentence of the graph, stopping the graph from running, and the address will stay in this position until the next time the system is re-run.
The beneficial effects are that: compared with the prior art, the ATE digital test system and the self-checking method thereof effectively solve the problem that the traditional self-checking mode does not verify, the graph used for self-checking comprises special instructions such as loops, jumps, block loops and the like except one, then the running track of the graph is monitored, whether the address changes correspondingly according to each micro instruction under high-speed running is observed, and therefore the performance of the system and the logic of the micro instruction part are verified to be normal. The potential problems which cannot be found by the traditional self-test can be reflected to a greater extent, so that the factory equipment is more stable, the failure rate is smaller, and the problems can be found by targeted interference elimination in the field failure.
Drawings
FIG. 1 is a schematic diagram of the logic structure of an ATE digital test system;
FIG. 2 is a schematic diagram of the logical structure of an address generator implementing a self-checking memory address generator within an address generator FPGA;
FIG. 3 is an exemplary diagram of address generation at self-test; the left side is the micro instruction and the right side is the address.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
As shown in FIG. 1, the ATE digital test system comprises an address generator, a graphic memory, an instruction memory, a self-checking memory and a driver, wherein the address generator is connected with the graphic memory, the instruction memory and the self-checking memory, the self-checking memory is connected with a bus, and the graphic memory is connected with the driver. The self-checking memory can be made of IS61LV12824 product of ISSI company, and IS 128K x 24 bit static memory. The address generator is implemented by an FPGA, and in this example, is implemented by using an EP1C6Q240C8 product of ALTERA company, and the main function is to generate an address.
A self-checking method for ATE digital test system features that when the system is running, the address generator generates address and sends it to instruction memory and graphics memory as address. And after the graphics memory receives the address, generating corresponding data, namely graphics, and outputting the data to a subsequent circuit to complete corresponding functions. The instruction memory receives the address and then sends the corresponding data, i.e. the instruction, back to the address generator, so that the address generator determines from the instruction how the address of the next beat should change, for example, add one or jump, etc.
Meanwhile, in order to realize the self-checking method, the address generator sends the address to the self-checking memory as data to be stored in the self-checking memory, and the address of the self-checking memory is another set of addresses generated by the address generator, namely the self-checking memory address, and the address generator is realized by logic independent of a normal address generator. The address is always incremented by one every beat from the beginning to the end of the self-test, so that the self-test memory can store the addresses used for running the graphics and instructions every beat. In the address generator FPGA, the logic is mainly implemented by a 17-bit counter (fig. 2), where 17 bits correspond to 128K of the self-checking memory, the counter is clocked by the same system clock as the normal address generator, and the address is incremented by one at the beginning of each beat period, and then the corresponding data is stored. Since the addresses are stored as data, in this example, the addresses are used to control a 1M graphics, instruction memory, and are therefore 22-bit, unlike 16-bit other data, the self-test memory is distinguished from other memory by selecting a 24-bit data bit wide memory to store a 22-bit address. The memory depth is 128K, which is sufficient to satisfy the length of the self-test pattern.
The self-checking process is to store the pre-programmed self-checking pattern in the pattern and instruction memory, when the system is running, the address generator will read the first instruction to determine how to do next, the address generator following the appointed action will send the new address to the instruction memory to generate the next instruction, and at the same time send the address to the self-checking memory as data to store, and make the self-checking memory address added one. Instructions are stored in a memory in the form of machine code and are implemented by writing micro-instructions in a graph when the instructions are operated on, wherein the used micro-instructions correspond to several types of micro-instructions (as shown in fig. 3):
adding one: the address is taken one step, i.e. sequentially incremented by one.
And (3) circulation: stay at the current address until the number of stay cycles is equal to the set number of loops, after which execution of the next instruction continues.
And (3) jumping: the address is replaced to the set address, in this example the jump destination is directly indicated by the address. Execution continues from the new location after the jump.
Block loop/block loop times: a block loop is a whole loop, which needs to be set from the start position to the instruction of the block loop as a bar, and the start position is expressed by an address in this example. The number of cycles, i.e. how many times the whole block circulates, is set, and the block circulation instruction can judge whether the current number of cycles reaches the set number of cycles, and when the number of cycles reaches the set number of cycles, the block circulation instruction continues to execute downwards when the instruction.
Ending: the micro instruction typically acts as the last sentence of the graph, stopping the graph from running, and the address will stay in this position until the next time the system is re-run.
According to the micro instruction, the address makes corresponding change, when the self-checking execution is completed, the address is stored in the self-checking memory in sequence, and the content in the self-checking memory is read onto the bus and transmitted to the computer. Because the graph is pre-coded, various actions with normal addresses are fixed, namely the correct address sequence is determined, so that whether the addresses are changed correctly according to the micro instructions in actual operation can be judged as long as the read address sequence is compared with the correct address sequence.
Claims (3)
1. A self-checking method of ATE digital test system, said ATE digital test system includes address generator, figure memory, instruction memory, self-checking memory and driver, the address generator is connected with figure memory, instruction memory and self-checking memory, the self-checking memory is connected with bus, the figure memory is connected with driver; the self-checking method is characterized in that a self-checking pattern which is pre-programmed is firstly stored in a pattern memory and an instruction memory in the self-checking process, when the system operates, an address generator reads a first instruction to determine how to do next, an address generator following a designated action sends a new address to the instruction memory to generate a next instruction, and meanwhile, the address is sent to the self-checking memory to be stored as data, and the address of the self-checking memory is increased by one;
according to the micro instruction, the address makes corresponding change, when the self-checking execution is completed, after the address is all sequentially stored in the self-checking memory, the content in the self-checking memory is read onto a bus and is transmitted to a computer; and comparing the read address sequence with the correct address sequence, and judging whether the address in actual operation changes correctly according to the micro instruction.
2. The method according to claim 1, wherein a 17-bit counter is provided in the address generator, the 17-bit counter corresponds to 128K of the self-test memory, the counter is clocked by the same system clock as the normal address generator, and the address is incremented by one at the beginning of each beat period, and then the corresponding data is stored.
3. The method according to claim 1, wherein the instructions are stored in the instruction memory in the form of machine code, and are implemented by writing micro instructions in the graphics when the instructions are operated, wherein the micro instructions corresponding to the instructions are as follows:
adding one: the address is taken by one step, namely one is added sequentially;
and (3) circulation: stay at the current address until the cycle number of stay equals to the set cycle number, then continue to execute the next instruction;
and (3) jumping: changing the address to the set address, and continuing to execute from the new position after the jump;
block cycle/number of block cycles: the block circulation is a certain section of integral circulation, which needs to be set from the start circulation, and the circulation is from the start position to the block circulation instruction; the number of circulation times is set, namely, how many times the whole block circulates, the block circulation instruction can judge whether the current circulation times reach the set number of times, and when the circulation times reach the set circulation times, the block circulation instruction is continuously executed downwards when the instruction is circulated;
ending: the micro instruction typically acts as the last sentence of the graph, stopping the graph from running, and the address will stay in this position until the next time the system is re-run.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610867908.1A CN106356102B (en) | 2016-09-29 | 2016-09-29 | ATE digital test system and self-checking method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610867908.1A CN106356102B (en) | 2016-09-29 | 2016-09-29 | ATE digital test system and self-checking method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106356102A CN106356102A (en) | 2017-01-25 |
| CN106356102B true CN106356102B (en) | 2023-06-09 |
Family
ID=57866400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610867908.1A Active CN106356102B (en) | 2016-09-29 | 2016-09-29 | ATE digital test system and self-checking method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106356102B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109974765B (en) * | 2018-12-28 | 2021-09-24 | 北京航天测控技术有限公司 | Intelligent assistant for automatic test system |
| CN115083504B (en) * | 2022-07-22 | 2022-11-01 | 中科声龙科技发展（北京）有限公司 | Chip self-inspection method and chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458971A (en) * | 2008-12-02 | 2009-06-17 | 炬力集成电路设计有限公司 | Test system and method for built-in memory |
| CN101692337A (en) * | 2009-10-16 | 2010-04-07 | 中国电子科技集团公司第四十一研究所 | High speed synchronization technique of character and figure sequence |
| CN103187103A (en) * | 2011-12-28 | 2013-07-03 | 中国航空工业集团公司第六三一研究所 | Memory test method |
| CN105551527A (en) * | 2014-11-03 | 2016-05-04 | 龙芯中科技术有限公司 | Test circuit, test method and apparatus of CAM |
| CN206194378U (en) * | 2016-09-29 | 2017-05-24 | 江苏艾科半导体有限公司 | ATE digit test system |
-
2016
- 2016-09-29 CN CN201610867908.1A patent/CN106356102B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458971A (en) * | 2008-12-02 | 2009-06-17 | 炬力集成电路设计有限公司 | Test system and method for built-in memory |
| CN101692337A (en) * | 2009-10-16 | 2010-04-07 | 中国电子科技集团公司第四十一研究所 | High speed synchronization technique of character and figure sequence |
| CN103187103A (en) * | 2011-12-28 | 2013-07-03 | 中国航空工业集团公司第六三一研究所 | Memory test method |
| CN105551527A (en) * | 2014-11-03 | 2016-05-04 | 龙芯中科技术有限公司 | Test circuit, test method and apparatus of CAM |
| CN206194378U (en) * | 2016-09-29 | 2017-05-24 | 江苏艾科半导体有限公司 | ATE digit test system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106356102A (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109840207B (en) | AutoSAR-based network management automation test system and test method | |
| US8997059B2 (en) | Reverse debugging | |
| CN109144515B (en) | Off-line simulation method and device for DCS graphical algorithm configuration | |
| US4797886A (en) | Memory test pattern generator | |
| KR20120031960A (en) | Robust memory link testing using memory controller | |
| CN110704314B (en) | Fault injection method for embedded software test | |
| CN111327490B (en) | Byzantine fault-tolerant detection method of block chain and related device | |
| CN106356102B (en) | ATE digital test system and self-checking method thereof | |
| KR100191143B1 (en) | High speed pattern generator | |
| US9092312B2 (en) | System and method to inject a bit error on a bus lane | |
| CN110704315B (en) | Fault injection device for embedded software test | |
| CN107329889B (en) | Method for automatically testing C compiler | |
| KR102087603B1 (en) | Memory test device and operating method of the same | |
| US11789851B2 (en) | Offline debugging method | |
| Trakhtenbrot | Implementation-oriented mutation testing of statechart models | |
| US10666294B2 (en) | Error correction code words with binomial bit error distribution | |
| JP2006242569A (en) | Testing device and testing method | |
| Friske et al. | Improving test coverage for UML state machines using transition instrumentation | |
| CN113704040A (en) | Microprocessor memory reliability testing method | |
| US7788564B2 (en) | Adjustable test pattern results latency | |
| CN110688271A (en) | Controllable random fault injection method applied to processor chip simulation verification | |
| CN111611768B (en) | Method and device for monitoring clock signals | |
| Petrus et al. | Model-Based Test Case Minimization and Prioritization for Improved Early Fault Detection Capability | |
| TWI661208B (en) | Test apparatus and testing circuit board thereof | |
| CN115563017B (en) | Test system and method based on bus injection and computer equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |