CN108520878A - A kind of Embedded Ferroelectric Random Access Memory of CMOS backend process and preparation method thereof - Google Patents
A kind of Embedded Ferroelectric Random Access Memory of CMOS backend process and preparation method thereof Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
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Abstract
A kind of high storage density of present invention proposition, low process costs, the Embedded Ferroelectric Random Access Memory of CMOS backend process and preparation method thereof.The capacitance is integrated into CMOS backend process lines in conjunction with suitable metal electrode up and down using the low temperature annealing process feature of novel ferroelectric material oxidation hafnium or zirconium oxide, information storage is realized, reads.In addition, the invention also discloses it is a kind of with 0.13 μm of CMOS technology line is completely compatible, does not need special barrier layer and the preparation method of ferroelectric memory that encapsulation technology, anti-radiation performance are good.
Description
Technical field
The invention belongs to integrated circuit processing technique field, it is related to the integrated technique field of novel memory devices, specially one
Kind and cmos compatible, Embedded Ferroelectric Random Access Memory (FRAM) and preparation method thereof.
Background technology
FRAM is very promising one kind in next-generation memory technology, is always focus of people's attention.It is by
Ferroelectric capacitor (including hearth electrode, ferroelectric thin-flim materials and top electrode) is integrated in complimentary oxide metal semiconductor (CMOS),
Store function, such as Fig. 1 are realized by the way that positive and negative polarization charge value in definition ferroelectric capacitor ferroelectric hysteresis loop is data " 0 " and " 1 ".
FRAM is provided simultaneously with the characteristics of RAM (random access memory) and ROM (read-only memory), non-volatile, low-power consumption, endurance,
Read or write speed is fast and radioresistance etc. has advantage, is widely used to RFID, intelligent electric meter, gas meter, water meter, elevator, ATM
The fields such as machine, PLC controls and Medical Devices.
Although FRAM has both above-mentioned the advantages of being better than traditional volatile memory and other non-volatile technologies, non-at present
FRAM only occupies smaller share to volatile memory in the market, also has very vast market prospect.Limit FRAM extensive uses
Principal element be its lower storage density, higher manufacturing cost and embedded integration relatively difficult to achieve.It is commercial at present single
In chip and embedded FRAM, the hearth electrode and top electrode of ferroelectric capacitor are mainly Pt, Ir, IrO2And SrRO3Deng ferroelectric thin film
Material is mainly lead zirconate titanate (PZT) series (including doping and non-impurity-doped).(600 DEG C of the higher crystallization temperature of PZT series thin films
Or higher), so that current ferroelectric capacitor is mainly integrated in before metal interconnection layer, i.e., ferroelectric capacitor is embedded in connects with transistor source region
On the through-hole connect.In preparation process, since ferroelectric thin film and electrode material can pollute the transistor and the rear ends CMOS work of front end
Skill (BEOL) can degenerate the electric property of ferroelectric thin film, it is necessary to use barrier technology and the technology of multilayer top electrode to reduce iron
The ferroelectric thin film characteristic degeneration that protium is brought in the diffusion of effumability element and backend process in conductive film.This increases
Process complexity and manufacturing cost, and it is difficult to realize High Density Integration.In addition, when embedded integration, increased FRAM techniques
Module cannot change the performance of other logical devices, otherwise must be limited using Full-custom design to increase design cost
Its Embedded realization.
Technological process, reduction manufacturing cost for the existing FRAM of simplification, Chinese patent notification number CN 102956566B reports
A kind of inserted self-registered technology reducing mask and etch step, but its technological process is still cumbersome.And in order to improve
Memory capacity, ferroelectric capacitor has been designed to 3D shape, but the three-dimensional capacitance technology of preparing of current pzt thin film is more difficult；And with
The electric property of the reduction of thickness, pzt thin film is degenerated.For the Embedded Application of FRAM, the limited public affairs of Japan Electric share
Department proposes a kind of ferroelectric capacitor integrated technology based on 0.25 μm of CMOS backend process：By MOCVD, (metal is organic for they
Object chemical vapor deposition) method has prepared pzt thin film at 445 DEG C, and ferroelectric capacitor is integrated in backend process.The technique
Influence of the backend process to ferroelectric thin film characteristic is reduced, reduces the cross contamination during flow, reduces production cost；
And other logical devices and technique need not be improved, be conducive to the embedded integration of ferroelectric capacitor.But low temperature process
The electric property of pzt thin film prepared by (being less than 600 DEG C) is poor；On the other hand, with the continuous diminution of process, the technology
Also it is difficult to meet lower and lower heat budget.
Therefore, further develop the preparation method of the integrated high density FRAM of low manufacturing cost, insertion type, have important
Research significance and be widely applied value.
Invention content
It is an object of the invention to for the above technical problems, propose a kind of high storage density, low process costs,
Embedded Ferroelectric Random Access Memory of CMOS backend process and preparation method thereof.
Technical scheme is as follows：
A kind of preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process is provided, the specific steps are：
Step 1：The preparation of mos field effect transistor (MOSFET) and multilayer through-hole, interlayer are situated between
Matter, metal interconnection, until before last layer of metal line is formed；
Step 2：Surface rubbing after being filled through-hole using chemically mechanical polishing (CMP) technology improves rough surface
Degree；
Step 3：Prepare the metallic bottom electrode of ferroelectric capacitor；
Step 4：Prepare ferroelectric layer；
Step 5：Prepare the metallic top electrode of ferroelectric capacitor；
Step 6：Metal-ferroelectric layer-metal (MFM) capacitance structure etching, ferroelectric capacitor is integrated in by chemical machinery
The surface of the through-hole of polishing process；
Step 7：The etching and filling, technique and traditional cmos process of the formation of passivation layer and last layer of through-hole
Finishing operation it is completely compatible, complete the preparation of storage unit；
Step 8：Peripheral circuit interconnects and encapsulation technology, completes the preparation of Ferroelectric Random Access Memory.
Preferably, the deposition of ferroelectric capacitor and annealing carry out under the conditions of temperature is less than or equal to 450 DEG C.
Preferably, before ferroelectric capacitor deposit, CMP technique will be for preparing flat metallic substrates, being averaged after CMP technique
Surface roughness reaches Nano grade, and after chemically mechanical polishing, ferroelectric capacitor is directly integrated in right over through-hole.
Preferably, the preparation of ferroelectric thin film may include that the reinforced atomic layer deposition method of plasma, magnetron sputtering, metal are organic
Object chemical vapor deposition or the reinforced metal-organic chemical vapor deposition equipment of plasma.
Preferably, the lithographic method of hafnium oxide base ferroelectric capacitor includes reactive ion etching, inductively coupled plasma-reaction
Ion etching, electron beam lithography, wet etching.
Preferably, the ferroelectric thin film of hafnium oxide, zirconium oxide and one or more doped series can be used as ferroelectric layer, thickness
For 3-30nm, deposition method includes but not limited to rf magnetron sputtering, PEALD, MOCVD, PLD etc..
Preferably, the metal materials such as titanium nitride, tantalum nitride, nickel, tungsten are used as the electrode of ferroelectric capacitor in the present invention.
Preferably, in the etching of ferroelectric capacitor, using the reticle pattern of design, only retain the material being deposited on above through-hole
The area of material, ferroelectric capacitor is 0.2-1 μm, specifically MOSFET process nodes is combined to select.
Preferably, which is applicable to 90nm and process above node, especially can with it is currently advanced
0.13 μm of processing line compatibility, using copper metal line.Ferroelectric capacitor heat budget prepared by the present invention is less than 450 DEG C, completely may be used
It meets the requirements.
Preferably, the thickness of ferroelectric capacitor is 15-60nm, and wherein the thickness of ferroelectric layer is 3-20nm.
The invention discloses a kind of Ferroelectric Random Access Memory, using material doped (undoped) hafnium oxide of novel ferroelectric or
The capacitance is integrated into CMOS backend process by the low temperature annealing process feature of person's zirconium oxide in conjunction with suitable metal electrode up and down
In line, realizes information storage, reads.In addition, that the invention also discloses a kind of is completely compatible with 0.13 μm of CMOS technology line, no
Need the preparation method of special barrier layer and the good ferroelectric memory of encapsulation technology, anti-radiation performance.
Compared with prior art, the present invention mainly has following advantage：
(1) present invention is completely compatible with traditional CMOS silicon process technology, and existing CMOS can be used in the preparation of ferroelectric memory
Processing line；
(2) compared with traditional ferroelectric memory, integrated technique proposed by the present invention can be omitted barrier layer, multilayer top electrode
Etc. techniques, reduce manufacturing cost；
(3) hafnium oxide base ferroelectric capacitor need not use platinum, iridium, yttrium oxide etc. are difficult to etch, be easy to cause cross contamination
Inert metal,
(4) due to the excellent resistant to hydrogen burn into radiation-resisting performance of hafnium oxide base film, device will have advantageous reliable
Property；
It realizes ferroelectric memory high storage density, low process costs in conclusion the present invention has, CMOS insertions can be achieved
The effect of formula.
Description of the drawings
It elaborates below in conjunction with the accompanying drawings to the present invention
Fig. 1 is the ferroelectric hysteresis loop figure of ferroelectric thin film.
Fig. 2 is the device architecture schematic diagram before last one of metal line.
Fig. 3 chemically-mechanicapolish polished in the structure of Fig. 2 after device architecture schematic diagram.
Fig. 4 is that the device architecture schematic diagram after ferroelectric capacitor is deposited in the structure of Fig. 3.
Fig. 5 is the device architecture schematic diagram completed on the basis of Fig. 4 structures after ferroelectric capacitor etching.
Fig. 6 is a kind of Embedded FRAM device architectures schematic diagram proposed by the present invention.
Fig. 7 is the ferroelectric hysteresis loop figure of the hafnium oxide ferroelectric capacitor of zirconium doping.
Fig. 8 is dielectric constant-voltage pattern of the hafnium oxide ferroelectric capacitor of zirconium doping.
Reference numeral：1- substrates, 2- source regions, the drain regions 3-, 4- gate dielectric layers, 5- through-holes, 6- metal layers, the centres 7- are necessary
Metal connection structure, the hearth electrode of 8- ferroelectric capacitors, 9- ferroelectric thin film layers, 10- ferroelectric capacitor top electrodes, 11- passivation layers.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in following description to facilitate a thorough understanding of the present invention, being still based on current CMOS silicon
The present situation of the high speed development of technology, the present invention can also be implemented using other different from other manner described here.
The present invention mainly proposes a kind of ferroelectric capacitor embedded integration in the thinking on CMOS technology line, and inventive point is not limited to certain
The replacement of specific technique and variation together.
With reference to Fig. 2, the source region (2) of transistor is completed on traditional cmos process line, drain region (3), gate dielectric layer (4), is led to
Hole (5), necessary metal interconnection (6,7).
The present embodiment is prepared using p-type silicon as substrate in MOSFET processing lines respectively based on 0.13 μm of process node
Source electrode, drain region and grid, wherein gate dielectric layer are SiON.
The CMOS backend process integrated technique of ferroelectric capacitor is with reference to figure 3- Fig. 6.
With reference to figure 3 using chemical Mechanical Polishing Technique (CMP) by metal (6) surface planarisation, surface flatness reaches
3nm。
On the basis of Fig. 3, with reference to figure 4 in sample surfaces extensive deposition metallic bottom electrode (7), hafnium oxide base ferroelectric thin
Film (8) and metallic top electrode (9).
Metallic bottom electrode (7) is TiN, thickness 10nm.Ferroelectric layer is the hafnium oxide ferroelectric thin film (HZO) of zirconium doping, zirconium
Doping content be 50%, film thickness 9nm, metallic top electrode TiN, thickness 10nm.TiN is by d.c. sputtering legal system
Standby, HZO films are deposited at 300 DEG C by PEALD and are obtained, and HZO in growth course in-situ crystallization and forms ferroelectric phase in the example,
It need not subsequently anneal to it.
With reference to figure 5, ferroelectric capacitor (7,8,9) is integrated in the surface of through-hole.
Photoresist spin coating, front baking, exposure imaging, rear baking and etching are carried out to sample above, complete the figure of ferroelectric capacitor
Shape.The etching of ferroelectric capacitor uses RIE methods, etching gas Ar/Cl2, etching terminal is the lower surface of metal (6).Iron
The area of capacitance is 1 μm2。
The deposition (11) and metal connecting line (6) for further completing passivation layer draw metal electrode with reference to figure 6, complete iron
The preparation of electric storage unit.In conjunction with peripheral circuit interconnection and encapsulation technology, the preparation of Ferroelectric Random Access Memory is completed.
The present invention is prepared for the oxidation of zirconium doping by the experiment of low temperature preparation ferroelectric capacitor using the method for PEALD
Hafnium (HZO) ferroelectric thin film, depositing temperature are 300 DEG C, film thickness 9nm, and upper/lower electrode is all made of chemical vapor deposition (CVD)
The TiN electrodes of preparation, thickness are 10nm, demonstrate the reliable and exploitativeness of the integrated technique.It is emphasized that the iron
The preparation of conductive film does not need after annealing processing and can be obtained excellent ferroelectricity.With reference to figure 7, residue when applied voltage is 2V
Polarization intensity 2PrFor 13 μ C/cm2；Remanent polarization 2P when applied voltage is 3VrFor 28 μ C/cm2, which can meet capacitive
The reading requirement of " 0 ", " 1 " signal is distinguished in ferroelectric memory.
The dielectric constant for the ferroelectric capacitor that this example also provides-voltage relationship figure, with reference to figure 8, the dielectric constant of HZO is about
For 33, it can be achieved that the larger design for reading window, simplifying sense amplifier.In addition, film thickness micro is propped up to Nano grade
Holder part miniaturization.
To sum up, hafnium oxide base ferroelectric capacitor is integrated into CMOS backend process, is obtained using low temperature depositing/annealing excellent
Different ferroelectric properties provides the feasibility of information storage for device；In addition, backend process is integrated due to complete and CMOS technology
Line is compatible with, and low temperature depositing/annealing of follow-up ferroelectric capacitor will not bring CMOS transistor characteristic damage, for the wound of the present invention
New property provides necessary example support and technical support.
Claims (10)
1. a kind of preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process, specific steps include：
Step 1：The preparation of mos field effect transistor and multilayer through-hole, inter-level dielectric, metal interconnection,
Until before last layer of metal line is formed；
Step 2：Surface rubbing after being filled through-hole using chemical Mechanical Polishing Technique improves surface roughness；
Step 3：Prepare the metallic bottom electrode of ferroelectric capacitor；
Step 4：Prepare ferroelectric layer；
Step 5：Prepare the metallic top electrode of ferroelectric capacitor；
Step 6：Metal-ferroelectric layer-metal capacitor structure etching, ferroelectric capacitor is integrated in by CMP process
Through-hole surface；
Step 7：The etching and filling of the formation of passivation layer and last layer of through-hole；
Step 8：Peripheral circuit interconnects and encapsulation, completes the preparation of Ferroelectric Random Access Memory.
2. the preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 1, feature
It is：The deposition of ferroelectric capacitor and annealing carry out under the conditions of temperature is less than or equal to 450 DEG C.
3. the preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 1, feature
It is：The preparation of ferroelectric thin film may include the reinforced atomic layer deposition method of plasma, magnetron sputtering, metal-organic chemical vapor
Deposition or the reinforced metal-organic chemical vapor deposition equipment of plasma.
4. the preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 1, feature
It is：After chemically mechanical polishing, ferroelectric capacitor is directly integrated in right over through-hole.
5. the preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 1, feature
It is：The lithographic method of hafnium oxide base ferroelectric capacitor include reactive ion etching, inductively coupled plasma-reactive ion etching,
Electron beam lithography, wet etching.
6. the preparation method of the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 1, feature
It is：Matched CMOS technology line is 90nm.
7. a kind of Embedded Ferroelectric Random Access Memory of CMOS backend process comprising：
(1) source electrode of mosfet transistor, drain electrode, grid；
(2) metal connecting line and wiring；
(3) hearth electrode of ferroelectric capacitor；
(4) ferroelectric layer；
(5) top electrode of ferroelectric capacitor；
It is characterized in that, ferroelectric capacitor structure setting is before last layer of metal line, the hearth electrode of ferroelectric condenser and top
Hafnium oxide base or zirconium oxide based ferroelectric film are set between electrode.
8. the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 7, it is characterised in that：The iron
Electroxidation hafnium base or zirconium oxide based ferroelectric film, including hafnium oxide, zirconium oxide and its doped series, it is specific such as hafnium oxide, oxygen
Change zirconium and containing aluminium, silicon, yttrium, strontium, lanthanum, lutetium, gold, scandium, neodymium, germanium, zirconium, hafnium, the one or more impurity of nitrogen hafnium oxide base or
Zirconium oxide ferroelectric thin film.
9. the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 7, it is characterised in that：The iron
The hearth electrode of capacitance and the structure that top electrode is titanium nitride, tantalum nitride, tungsten, the single layer of nickel or multi-layered electrode.
10. the Embedded Ferroelectric Random Access Memory of CMOS backend process according to claim 7, it is characterised in that：Its iron
The thickness of conductive film is 3-30nm.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109473431A (en) * | 2018-11-13 | 2019-03-15 | 中国科学院微电子研究所 | A kind of three-dimensional ferroelectric memory and preparation method thereof |
| CN109518163A (en) * | 2018-11-27 | 2019-03-26 | 合肥安德科铭半导体科技有限公司 | A kind of preparation method, product and its application of zirconium doping hafnium oxide ferroelectric thin film |
| CN109904162A (en) * | 2019-03-08 | 2019-06-18 | 成都豆萁集成电路设计有限公司 | A kind of ferroelectric storage unit and its manufacturing method |
| CN109935589A (en) * | 2019-03-26 | 2019-06-25 | 湘潭大学 | A kind of hafnium oxide base ferroelectric capacitor and preparation method thereof |
| CN111732128A (en) * | 2020-07-04 | 2020-10-02 | 湘潭大学 | Two-dimensional tetragonal ferromagnetic material and preparation method thereof, storage unit and method for regulating and controlling identification and storage data of storage unit |
| US10861862B1 (en) | 2019-06-24 | 2020-12-08 | Wuxi Petabyte Technologies Co, Ltd. | Ferroelectric memory devices |
| US20220351768A1 (en) * | 2017-05-09 | 2022-11-03 | Micron Technology, Inc. | Ferroelectric devices and ferroelectric memory cells |
| WO2023197766A1 (en) * | 2022-04-11 | 2023-10-19 | 华为技术有限公司 | Structure of and preparation method for ferroelectric thin film capacitor |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220351768A1 (en) * | 2017-05-09 | 2022-11-03 | Micron Technology, Inc. | Ferroelectric devices and ferroelectric memory cells |
| CN109473431A (en) * | 2018-11-13 | 2019-03-15 | 中国科学院微电子研究所 | A kind of three-dimensional ferroelectric memory and preparation method thereof |
| CN109518163A (en) * | 2018-11-27 | 2019-03-26 | 合肥安德科铭半导体科技有限公司 | A kind of preparation method, product and its application of zirconium doping hafnium oxide ferroelectric thin film |
| CN109904162A (en) * | 2019-03-08 | 2019-06-18 | 成都豆萁集成电路设计有限公司 | A kind of ferroelectric storage unit and its manufacturing method |
| CN109935589A (en) * | 2019-03-26 | 2019-06-25 | 湘潭大学 | A kind of hafnium oxide base ferroelectric capacitor and preparation method thereof |
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| US10861862B1 (en) | 2019-06-24 | 2020-12-08 | Wuxi Petabyte Technologies Co, Ltd. | Ferroelectric memory devices |
| WO2020258877A1 (en) * | 2019-06-24 | 2020-12-30 | Wuxi Petabyte Technologies Co., Ltd. | Ferroelectric memory devices and methods for forming the same |
| CN111732128A (en) * | 2020-07-04 | 2020-10-02 | 湘潭大学 | Two-dimensional tetragonal ferromagnetic material and preparation method thereof, storage unit and method for regulating and controlling identification and storage data of storage unit |
| WO2023197766A1 (en) * | 2022-04-11 | 2023-10-19 | 华为技术有限公司 | Structure of and preparation method for ferroelectric thin film capacitor |
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Application publication date: 20180911 |