CN108493232A - A kind of mixing section terminal protection structure and preparation method thereof that Spatial dose modulation JTE is constituted with field wire ring - Google Patents
A kind of mixing section terminal protection structure and preparation method thereof that Spatial dose modulation JTE is constituted with field wire ring Download PDFInfo
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- CN108493232A CN108493232A CN201810238503.0A CN201810238503A CN108493232A CN 108493232 A CN108493232 A CN 108493232A CN 201810238503 A CN201810238503 A CN 201810238503A CN 108493232 A CN108493232 A CN 108493232A
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- jte
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
- 230000000903 blocking effect Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 12
- 238000002513 implantation Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000012190 activator Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Abstract
The invention discloses the mixing section terminal protection structure and preparation method thereof that a kind of Spatial dose modulation JTE is constituted with field wire ring, the protection structure includes the JTE structures being sequentially distributed from the active area of device to device edge and field wire ring structure.The protection structure of the application is applied to be formed in the section terminal area of longitudinal power device or the drift region of lateral power reduces device surface electric field to reach, and improves the effect of device pressure resistance.The structure can achieve the purpose that reduce surface field and improve pressure resistance, the relatively low and requirement to photoetching of cost is relatively low in the case of a photoetching and ion implanting.In addition; the mixing section terminal protection structure that the Spatial dose modulation JTE of the application is constituted with field wire ring; 3 times are reduced to the required precision of photoetching process compared with conventional field ring structure, 7 times are increased to the concentration window of implantation dosage and activator impurity compared with traditional JTE structures, increases process window.
Description
Technical field
The present invention relates to semiconductor devices to protect construction applications, and in particular to a kind of Spatial dose modulation JTE and field wire ring
Mixing section terminal protection structure of composition and preparation method thereof.
Background technology
Existing power device product generally requires terminal protection structure and is increased with preventing device from puncturing in advance at pn-junction edge
Add the pressure resistance of device, while preventing surface field excessively high to improve device reliability.
Traditional terminal protection structure either requires accurate (such as tradition JTE structures) or to light to implantation dosage control
It is higher (such as traditional field limiting ring structure) to carve required precision.Requirement of traditional JTE structures to implantation dosage generally within ± 50%,
And traditional field limiting ring structure generally requires lithographic accuracy at 0.5 micron or less.For these traditional structures, due to implant angle
With the deviation of photoetching process, chip it is resistance to be pressed in piece uniformity between uniformity and piece can be by process deviation large effect.
For silicon carbide device, there is uncertainty in the impurity concentration that can be activated after ion implanting, more aggravated work
Skill difficulty.
Invention content
For problems of the prior art, the purpose of the present invention is to provide a kind of Spatial dose modulation JTE and fields
The mixing section terminal protection structure that wire loop is constituted, the structure can reach reduction table in the case of a photoetching and ion implanting
Face electric field and the purpose for improving pressure resistance, the relatively low and requirement to photoetching of cost are relatively low.Another object of the present invention is to provide
A kind of preparation method for the mixing section terminal protection structure that Spatial dose modulation JTE is constituted with field wire ring.
To achieve the above object, the present invention uses following technical scheme：
A kind of mixing section terminal protection structure that Spatial dose modulation JTE is constituted with field wire ring, the protection structure include
The JTE structures being sequentially distributed from the active area of device to device edge and field wire ring structure；Wherein, the JTE structures are at least wrapped
Region containing a spatial modulation, the injection region in the region account for the 1% to 99% of the region gross area；If including two or more
Spatial modulation region, injection region accounting successively decreases from active area to device edge；The field wire ring structure includes including at least one
A field wire ring, if including two or more field wire rings, the interval of field wire ring can be same intervals, equal difference interval or differ
Interval.
A kind of preparation method for the mixing section terminal protection structure that Spatial dose modulation JTE is constituted with field wire ring, the side
Method is：
Injection mask blocks layer is set in the ion implanted regions of device surface first, is then made by ion implanting
The JTE structures and the field wire ring structure make shape by adjusting the blocking pattern density of the injection mask blocks layer
The JTE structures successively decreased from active area to device edge at injection region accounting；And by modulated Field wire loop interval come modulated Field wire loop
Injection ratio.
Further, the mask blocks layer be the silica of 0.5um -3um thickness, silicon nitride, polysilicon, photoresist or
Their mixed structure.
Further, the angle of the ion implanting is 0-45 degree, and ion implantation energy 1keV-3000keV, dosage is
2E11cm-2-2E15cm-2。
Further, the blocking layer pattern on the mask blocks layer is circle, circular ring shape or polygon.
The present invention has following advantageous effects：
The protection structure of the application is applied in the section terminal area of longitudinal power device or the drift of lateral power
Area is formed reduces device surface electric field to reach, and improves the effect of device pressure resistance.The structure can be in a photoetching and ion implanting
In the case of, achieve the purpose that reduce surface field and improve pressure resistance, the relatively low and requirement to photoetching of cost is relatively low.In addition,
The mixing section terminal protection structure that the Spatial dose modulation JTE of the application is constituted with field wire ring, compared with conventional field ring structure
3 times are reduced to the required precision of photoetching process, the concentration window of implantation dosage and activator impurity is increased compared with traditional JTE structures
Add 7 times, increases process window.
Description of the drawings
Fig. 1 is the mask blocks that Spatial dose of the present invention modulates the mixing section terminal protection structure that JTE is constituted with field wire ring
The figure of layer；
Fig. 2 is the 3-D graphic that Spatial dose of the present invention modulates the mixing section terminal protection structure that JTE is constituted with field wire ring；
Fig. 3 is process window and the typical case JTE+FLR injections of the invention in a traditional area, 2nd area, four area's JTE implantation dosages
The process window comparison chart of dosage；
Fig. 4 be from top to bottom be that an area JTE injects the terminal structure schematic diagram to be formed, two area JTE inject to be formed respectively
Terminal structure schematic diagram, four area JTE inject the terminal structure schematic diagram to be formed and the typical JTE+ field wires ring injection of the present invention
Terminal structure schematic diagram；
Fig. 5 is the structural schematic diagram of the blocking layer pattern on mask blocks layer in the embodiment of the present invention.
Specific implementation mode
In the following, refer to the attached drawing, makes a more thorough explanation the present invention, shown in the drawings of the exemplary implementation of the present invention
Example.However, the present invention can be presented as a variety of different forms, it is not construed as the exemplary implementation for being confined to describe here
Example.And these embodiments are to provide, it is of the invention full and complete to make, and will fully convey the scope of the invention to this
The those of ordinary skill in field.
It is described the present invention provides the mixing section terminal protection structure that a kind of Spatial dose modulation JTE is constituted with field wire ring
Protection structure includes the JTE structures being sequentially distributed from the active area of device to device edge and field wire ring structure；Wherein, described
JTE structures include at least the region of a spatial modulation, and the injection region in the region accounts for the 1% to 99% of the region gross area；If
Including two or more spatial modulation regions, injection region accounting are successively decreased from active area to device edge；The field wire ring structure
Including including at least a field wire ring, if including two or more field wire rings, the interval of field wire ring can be same intervals, etc.
Difference interval or unequal interval.
The protection structure of the present invention is applied in the section terminal area of longitudinal power device or the drift of lateral power
Area is formed reduces device surface electric field to reach, and improves the effect of device pressure resistance.The structure can be in a photoetching and ion implanting
In the case of, achieve the purpose that reduce surface field and improve pressure resistance, the relatively low and requirement to photoetching of cost is relatively low.The structure
It is sequentially distributed from chip active area to chip edge, Spatial dose modulates JTE structures and field limiting ring structure.Wherein, Spatial dose
JTE (Junction Termination Extension, section terminal extend) structure is modulated, the ion note in chip surface is passed through
Enter region and forms discrete blocking figure to realize the modulation of implantation dosage.With from active area to chip edge, stop figure
The change of density, the equivalent implantation dosage in space change correspondingly；Stop that the density of figure is bigger, the equivalent implantation dosage in space is smaller.
Field limiting ring structure followed by will provide entire device enough pressure-resistant design margins, to ensure enough process windows.
A kind of preparation method for the mixing section terminal protection structure that Spatial dose modulation JTE is constituted with field wire ring, the side
Method is：
Injection mask blocks layer is set in the ion implanted regions of device surface first, is then made by ion implanting
The JTE structures and the field wire ring structure make shape by adjusting the blocking pattern density of the injection mask blocks layer
The JTE structures successively decreased from active area to device edge at injection region accounting；And by modulated Field wire loop interval come modulated Field wire loop
Injection ratio.
Such as Fig. 1, mask blocks layer be the silica of 0.5um -3um thickness, silicon nitride, polysilicon, photoresist or they
Mixed structure.Blocking layer pattern on mask blocks layer is circle, circular ring shape or polygon；Mask is set forth in Fig. 5
Blocking layer pattern on barrier layer is the structural schematic diagram of quadrangle, diamond shape, circle, hexagon and annular.In Fig. 1 from a left side to
The right side is followed successively by the injection regions 100%JTE, the injection regions 75%JTE, the injection regions 50%JTE, the injection regions 25%JTE and field wire ring note
Enter the mask pattern in area.As shown in Fig. 2, the figure is exactly three of the protection structure by being formed after the mask pattern injection in Fig. 1
Tie up figure.
The angle of ion implanting is 0-45 degree, ion implantation energy 1keV-3000keV, dosage 2E11cm-2-2E15cm-2.As shown in figure 3, the process window and a traditional area, 2nd area, four area JTE for typical case's JTE+FLR implantation dosages of the invention are noted
Enter the process window comparison chart of dosage；Fig. 4 is to inject the terminal structure schematic diagram to be formed according to the injection curve in Fig. 3；From Fig. 3
It is found that the mixing section terminal protection structure that the Spatial dose modulation JTE of the present invention is constituted with field wire ring, with conventional field ring structure
3 times are reduced compared to the precision to photoetching process, the concentration window of implantation dosage and activator impurity is increased compared with traditional JTE structures
Add 7 times, increases process window.
It is described above simply to illustrate that of the invention, it is understood that the present invention is not limited to the above embodiments, meets
The various variants of inventive concept are within protection scope of the present invention.
Claims (5)
1. a kind of mixing section terminal protection structure that Spatial dose modulation JTE is constituted with field wire ring, which is characterized in that the protection
Structure includes the JTE structures being sequentially distributed from the active area of device to device edge and field wire ring structure；Wherein, the JTE knots
Structure includes at least the region of a spatial modulation, and the injection region in the region accounts for the 1% to 99% of the region gross area；If including two
A or more spatial modulation region, injection region accounting are successively decreased from active area to device edge；The field wire ring structure includes extremely
Include less a field wire ring, if including two or more field wire rings, the interval of field wire ring can be same intervals, equal difference interval
Or unequal interval.
2. a kind of system for the mixing section terminal protection structure that Spatial dose modulation JTE described in claim 1 is constituted with field wire ring
Preparation Method, which is characterized in that the method is：
Injection mask blocks layer is set in the ion implanted regions of device surface first, is then made by ion implanting described
JTE structures and the field wire ring structure, the blocking pattern density by adjusting the injection mask blocks layer to form note to make
Enter the JTE structures that area's accounting is successively decreased from active area to device edge；And by modulated Field wire loop interval come the note of modulated Field wire loop
Enter ratio.
3. the system for the mixing section terminal protection structure that Spatial dose modulation JTE according to claim 2 is constituted with field wire ring
Preparation Method, which is characterized in that the mask blocks layer be the silica of 0.5um -3um thickness, silicon nitride, polysilicon, photoresist or
Their mixed structure of person.
4. the system for the mixing section terminal protection structure that Spatial dose modulation JTE according to claim 2 is constituted with field wire ring
Preparation Method, which is characterized in that the angle of the ion implanting is 0-45 degree, and ion implantation energy 1keV-3000keV, dosage is
2E11cm-2-2E15cm-2。
5. the system for the mixing section terminal protection structure that Spatial dose modulation JTE according to claim 2 is constituted with field wire ring
Preparation Method, which is characterized in that the blocking layer pattern on the mask blocks layer is circle, circular ring shape or polygon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810238503.0A CN108493232A (en) | 2018-03-22 | 2018-03-22 | A kind of mixing section terminal protection structure and preparation method thereof that Spatial dose modulation JTE is constituted with field wire ring |
| PCT/CN2018/082586 WO2019178903A1 (en) | 2018-03-22 | 2018-04-11 | Hybrid junction termination protection structure composed of spatial dose modulated jte and field limiting ring, and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810238503.0A CN108493232A (en) | 2018-03-22 | 2018-03-22 | A kind of mixing section terminal protection structure and preparation method thereof that Spatial dose modulation JTE is constituted with field wire ring |
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| Publication Number | Publication Date |
|---|---|
| CN108493232A true CN108493232A (en) | 2018-09-04 |
Family
ID=63318971
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810238503.0A Pending CN108493232A (en) | 2018-03-22 | 2018-03-22 | A kind of mixing section terminal protection structure and preparation method thereof that Spatial dose modulation JTE is constituted with field wire ring |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108493232A (en) |
| WO (1) | WO2019178903A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102460652A (en) * | 2009-05-12 | 2012-05-16 | 克里公司 | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| CN102479807A (en) * | 2010-11-26 | 2012-05-30 | 三菱电机株式会社 | Silicon carbide semiconductor device and manufacturing method therefor |
| US20150340443A1 (en) * | 2014-05-21 | 2015-11-26 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
| CN106601826A (en) * | 2015-10-16 | 2017-04-26 | 国网智能电网研究院 | Fast recovery diode and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801836A (en) * | 1996-07-16 | 1998-09-01 | Abb Research Ltd. | Depletion region stopper for PN junction in silicon carbide |
| CN102610635B (en) * | 2012-03-26 | 2014-04-02 | 大连理工大学 | High-density graded field limiting ring structure and manufacturing process thereof |
| CN104952910A (en) * | 2015-05-19 | 2015-09-30 | 上海先进半导体制造股份有限公司 | Terminal structure of super-junction semiconductor device and manufacturing method thereof |
| CN204696121U (en) * | 2015-06-19 | 2015-10-07 | 深圳市谷峰电子有限公司 | A kind of terminal structure of high-voltage MOSFET device |
| CN105932046B (en) * | 2016-06-01 | 2019-03-01 | 清华大学 | Edge junction termination structures towards silicon carbide high pressure high power device |
| CN106298512A (en) * | 2016-09-22 | 2017-01-04 | 全球能源互联网研究院 | A kind of fast recovery diode and preparation method thereof |
-
2018
- 2018-03-22 CN CN201810238503.0A patent/CN108493232A/en active Pending
- 2018-04-11 WO PCT/CN2018/082586 patent/WO2019178903A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102460652A (en) * | 2009-05-12 | 2012-05-16 | 克里公司 | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| CN102479807A (en) * | 2010-11-26 | 2012-05-30 | 三菱电机株式会社 | Silicon carbide semiconductor device and manufacturing method therefor |
| US20150340443A1 (en) * | 2014-05-21 | 2015-11-26 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
| CN106601826A (en) * | 2015-10-16 | 2017-04-26 | 国网智能电网研究院 | Fast recovery diode and manufacturing method thereof |
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| Publication number | Publication date |
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| WO2019178903A1 (en) | 2019-09-26 |
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Application publication date: 20180904 |