CN101752381B - OTP (one-time programmable) element structure and preparation method thereof - Google Patents
OTP (one-time programmable) element structure and preparation method thereof Download PDFInfo
- Publication number
- CN101752381B CN101752381B CN 200810044082 CN200810044082A CN101752381B CN 101752381 B CN101752381 B CN 101752381B CN 200810044082 CN200810044082 CN 200810044082 CN 200810044082 A CN200810044082 A CN 200810044082A CN 101752381 B CN101752381 B CN 101752381B
- Authority
- CN
- China
- Prior art keywords
- additional ions
- floating boom
- region
- active area
- electric capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses an OTP (one-time programmable) element structure which comprises a transistor region and a capacitor region, wherein the transistor region comprises a transistor active region; the capacitor region comprises a floating gate and capacitor active regions positioned at two sides of the floating gate, and also comprises two additional ion injection regions which are positioned at two sides below the floating gate and are separable mutually and respectively comprise the capacitor active region, and part of the two additional ion injection regions is positioned below the floating gate. A preparation method of the OTP element structure comprises the steps of: firstly, before the active region is injected, defining an ion injection region by using a photolithographic process; secondly, carrying out additional ion injection; and thirdly, annealing to enable the additional ion injection region to be transversely dispersed. The OTP element structure has programming current increase and programming speed acceleration, enables the current peak of the floating gate to be slowly changed, reduces the precision requirement on programming voltage, and reduces the influences on programming effect by process deviation.
Description
Technical field
The present invention relates to a kind of OTP parts structure.The invention still further relates to a kind of preparation method of OTP parts.
Background technology
Utilizing floating boom (Floating poly) store electrons is the basic functional principle of common disposable programmable memory spare OTP (one-time programmable memory).Floating boom in the OTP parts can embed in the common logic process, generally add a floating boom electric capacity and realize the basic programming of OTP and the function of charge storage by a transistor, the schematic diagram of OTP parts is seen Fig. 1, domain in concrete preparation is seen Fig. 2, wherein the shared polysilicon of control gate and floating boom.
The OTP of this structure is under the influence of process deviation, the program speed of product can be variant, generally do not wait at 100u-500us, and fixing program conditions is often not general for different products, for jumbo product, program speed is unusual important techniques index.
Utilize (CHE) grid maximum current of thermoelectronic effect when programming owing to existing OTP parts simultaneously, the crest of maximum current is steep excessively, can be for the too high (see figure 4) of the required precision of program voltage.
Summary of the invention
The technical problem to be solved in the present invention is a kind of OTP parts structure, and it can improve the performance of OTP programming.The present invention also will provide a kind of preparation method of OTP parts.
For solving the problems of the technologies described above, the described OTP parts of OTP parts structure of the present invention comprises transistor area and capacitor regions, described transistor area comprises the transistor active area, the electric capacity active area that described capacitor regions comprises floating boom and is positioned at the floating boom both sides, the shared polysilicon of control gate of the described floating boom of described capacitor regions and described transistor area, the described electric capacity active area of the described floating boom both sides of described capacitor regions is drawn the source electrode and the drain electrode of described capacitor regions; Described capacitor regions also comprises and is positioned at both sides, described floating boom below, be separated from each other and comprise respectively two additional ions injection zones of described electric capacity active area, described additional ions injection zone partly is positioned at the floating boom below, the injection ionic type of described additional ions injection zone is identical with the ionic type of electric capacity active area, and the ion concentration of described additional ions injection zone is less than the ion concentration of electric capacity active area.
The preparation method of OTP parts of the present invention for before active area injects, utilizes photoetching process to define the ion implanted region territory earlier, after carry out additional ions and inject, annealing afterwards makes the horizontal proliferation of additional ions injection zone.
In the OTP parts structure of the present invention, utilize the extra coupling regime that increases the transistor active area and the floating utmost point that injects, make the floating boom maximum current of OTP programming NMOS appear at the voltage higher position, current value is big more, and device programming speed is fast more.And the coupling regime of active area and grid increases, and OTPProgram grid current peak value is slowed down, and for the required precision reduction of program voltage, and reduces the influence of process deviation for programing effect.And OTP parts of the present invention increases the floating boom electric current by utilizing the stack of FN tunnelling current and hot electron CHE (Hot electron) effect, thereby program speed is improved, and program voltage can suitably descend according to demand.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the schematic diagram of OTP parts;
Fig. 2 is an OTP parts layout design schematic diagram;
Fig. 3 is the schematic cross-section along BB ' among Fig. 2;
Fig. 4 is existing OTP parts floating boom maximum current measured drawing;
Fig. 5 is an OTP parts floating boom maximum current measured drawing of the present invention.
Embodiment
The present invention is on existing OTP parts structure, a kind of OTP parts project organization and process implementation method have been proposed, be embedded in the common logic process, realization comprises the lifting of program capability, the reduction of program voltage, the raising of program speed, the raising of storage reserve force (Data retention) etc. for floating boom OTP parts optimization in Properties.
Utilizing the extra coupling regime that injects increase active area and grid is emphasis of the present invention.Fig. 3 is the schematic cross-section along BB ' in the coupling capacitance zone of the present invention.Be example with the OTP parts that contains nmos pass transistor among the figure, from this sectional view as can be known, both sides below as the polysilicon of floating boom, two additional ions injection zones that are separated from each other and comprise the electric capacity active area are respectively arranged, described additional ions injection zone partly is positioned at floating boom below (see figure 3), forms the coupling regime of electric capacity active area and floating boom.Maximum current appears at the voltage higher position on the floating boom of programming NMOS, and current value is big more, and device programming speed is fast more.Coupling regime between transistor active area and the floating boom increases, and makes the OTP parts programming grid current peak (see figure 5) that slows down, and the required precision that has reduced program voltage reduces, and reduces the influence of process deviation for programing effect.And by utilizing FN tunnelling current and hot electron to puncture the stack of (CHE:Hot electron) effect, grid current is increased, thereby program speed is improved, program voltage can suitably descend according to demand.
Process implementation method for the additional ions injection that increases: utilize active area to be infused in active area and inject the extra injection of appending before once, the ionic type that this secondary ion injects is identical with the injection ionic type of active area, implantation concentration is lower than the active area, but energy is wanted big (being that the degree of depth is wanted deeply), the annealing thermal process of technology after utilizing, diffuse laterally into the grid below, inject the coupling regime that forms between transistor active area and the floating boom.In the example as shown in Figure 3, additional ions is injected to the ion of N type, can be arsenic, and its implantation concentration is: 5 * 10
13-5 * 10
14Between individual atom/square centimeter, the injection energy is: 50-100Kev.Additional ions of the present invention is injected, and also can use extra lithography mask version (figure of this mask is identical with the ion implanted region of being scheduled to) to realize, can not need the DIFFUSION TREATMENT of annealing after injecting like this.
Fig. 4 and Fig. 5 are respectively the comparison of the Ig-Vg measured data of OTP parts of the present invention and existing OTP parts.After can seeing that carrying out additional ions in OTP parts of the present invention injects, the maximum current peak of floating boom becomes a big order of magnitude, and the decline of the electric current after the peak value slows down.
The present invention is on existing OTP structure, a kind of novel designs structure and process implementation method have been proposed, embed common logic process, realization comprises the lifting of program capability, the reduction of program voltage, the raising of program speed, the raising of Data retention (storage reserve force) for floating boom OTP parts optimization in Properties.
Claims (4)
1. OTP parts structure, described OTP parts comprises transistor area and capacitor regions, described transistor area comprises the transistor active area, the electric capacity active area that described capacitor regions comprises floating boom and is positioned at the floating boom both sides, the shared polysilicon of control gate of the described floating boom of described capacitor regions and described transistor area, the described electric capacity active area of the described floating boom both sides of described capacitor regions is drawn the source electrode and the drain electrode of described capacitor regions; It is characterized in that: described capacitor regions also comprises and is positioned at both sides, described floating boom below, be separated from each other and comprise respectively two additional ions injection zones of described electric capacity active area, described additional ions injection zone partly is positioned at the floating boom below, the injection ionic type of described additional ions injection zone is identical with the ionic type of electric capacity active area, and the ion concentration of described additional ions injection zone is less than the ion concentration of electric capacity active area.
2. method for preparing the described OTP parts structure of claim 1, it is characterized in that, before active area injects, carry out ion earlier and be infused in the step that capacitor regions forms the additional ions injection region, described additional ions injection region is positioned at both sides, floating boom below, be separated from each other and comprise two electric capacity active areas in the OTP parts respectively, described additional ions injection region part is positioned at the floating boom below; Concrete processing step comprises: utilize photoetching process to define the ion implanted region territory earlier, after carry out additional ions and inject, annealing afterwards makes the horizontal proliferation of additional ions injection zone.
3. in accordance with the method for claim 2, it is characterized in that: described additional ions is injected ion and is: arsenic, its implantation concentration is: 5 * 10
13-5 * 10
14Between individual atom/square centimeter, the injection energy is: 50-100Kev.
4. according to claim 2 or 3 described methods, it is characterized in that: the annealing process condition of described additional ions injection zone is identical with the annealing process condition in device source drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810044082 CN101752381B (en) | 2008-12-10 | 2008-12-10 | OTP (one-time programmable) element structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810044082 CN101752381B (en) | 2008-12-10 | 2008-12-10 | OTP (one-time programmable) element structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101752381A CN101752381A (en) | 2010-06-23 |
| CN101752381B true CN101752381B (en) | 2013-07-24 |
Family
ID=42479074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810044082 Active CN101752381B (en) | 2008-12-10 | 2008-12-10 | OTP (one-time programmable) element structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101752381B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122642B (en) * | 2011-01-27 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The formation method of OTP parts |
| TWI606448B (en) | 2015-07-29 | 2017-11-21 | 國立交通大學 | Dielectric fuse memory circuit and operation method thereof |
| CN109103189B (en) * | 2018-07-11 | 2021-08-24 | 上海华虹宏力半导体制造有限公司 | One-time programmable device composed of N-type capacitance coupling transistor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504706A (en) * | 1993-10-12 | 1996-04-02 | Texas Instruments Incorporated | Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells |
| CN1147314A (en) * | 1994-03-03 | 1997-04-09 | 罗姆有限公司 | Low voltage one transistor flash EEPROM cell using Fowler-Nordheim Programming and erase |
| US6282123B1 (en) * | 1998-12-21 | 2001-08-28 | Lattice Semiconductor Corporation | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell |
| CN1505841A (en) * | 2001-05-01 | 2004-06-16 | ÷˹���ɷݹ�˾ | EEPROM cell with asymmetric thin window |
| CN1819208A (en) * | 2004-12-28 | 2006-08-16 | 株式会社瑞萨科技 | Semiconductor storage device |
| CN1828774A (en) * | 2005-03-02 | 2006-09-06 | 三洋电机株式会社 | Nonvolatile semiconductor memory device and manufacturing method of the same |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
-
2008
- 2008-12-10 CN CN 200810044082 patent/CN101752381B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5504706A (en) * | 1993-10-12 | 1996-04-02 | Texas Instruments Incorporated | Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells |
| CN1147314A (en) * | 1994-03-03 | 1997-04-09 | 罗姆有限公司 | Low voltage one transistor flash EEPROM cell using Fowler-Nordheim Programming and erase |
| US6282123B1 (en) * | 1998-12-21 | 2001-08-28 | Lattice Semiconductor Corporation | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell |
| CN1505841A (en) * | 2001-05-01 | 2004-06-16 | ÷˹���ɷݹ�˾ | EEPROM cell with asymmetric thin window |
| CN1819208A (en) * | 2004-12-28 | 2006-08-16 | 株式会社瑞萨科技 | Semiconductor storage device |
| CN1828774A (en) * | 2005-03-02 | 2006-09-06 | 三洋电机株式会社 | Nonvolatile semiconductor memory device and manufacturing method of the same |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101752381A (en) | 2010-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102737967B (en) | Semiconductor device and substrate with chalcogen doped region | |
| CN103000672A (en) | Semiconductor component having main body with doped material area and method for forming area | |
| CN101752381B (en) | OTP (one-time programmable) element structure and preparation method thereof | |
| CN102130164A (en) | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) | |
| DE102018205274B4 (en) | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCTION THEREOF | |
| CN102446912B (en) | Metal oxide semiconductor transistor ESD (Electrostatic Discharge) protection structure and making method thereof | |
| CN103178087A (en) | Ultra-high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and production method thereof | |
| CN103367398A (en) | Terminal guard ring and manufacturing method thereof | |
| CN102104068A (en) | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof | |
| CN104299908B (en) | VDMOS and preparation method thereof | |
| CN101197377B (en) | Single layer polysilicon grid MTP device and manufacturing method thereof | |
| CN101877329B (en) | OTP (One Time Programming) device and manufacture method | |
| CN103022125A (en) | NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method | |
| CN102130163B (en) | ESD (electrostatic discharge) high-voltage DMOS (diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN101043056A (en) | Nonvolatile memory device and method of forming the same | |
| CN101901810A (en) | Memory device and methods for fabricating and operating the same | |
| CN104851839A (en) | Method improving memory performance | |
| CN106206677A (en) | The laterally junction termination structures of high voltage power device | |
| CN105428404A (en) | Power device and method of manufacturing the same | |
| CN102983080B (en) | Method for improving erasure and programming performances of split gate memory | |
| CN104201203A (en) | High voltage resistance LDMOS device and manufacturing method thereof | |
| CN104900695A (en) | Power-junction-type field effect transistor and manufacturing method thereof | |
| CN102969318B (en) | P-type one-time programmable (OTP) device and manufacturing method thereof | |
| KR20100030798A (en) | Flash memory device and method for manufacturing thereof | |
| CN107180763A (en) | The method for improving VDMOS device breakdown voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |