CN107180763A - The method for improving VDMOS device breakdown voltage - Google Patents
The method for improving VDMOS device breakdown voltage Download PDFInfo
- Publication number
- CN107180763A CN107180763A CN201610137943.8A CN201610137943A CN107180763A CN 107180763 A CN107180763 A CN 107180763A CN 201610137943 A CN201610137943 A CN 201610137943A CN 107180763 A CN107180763 A CN 107180763A
- Authority
- CN
- China
- Prior art keywords
- region
- type
- photoresist
- vdmos
- partial pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 230000015556 catabolic process Effects 0.000 title claims abstract description 25
- 238000002347 injection Methods 0.000 claims abstract description 54
- 239000007924 injection Substances 0.000 claims abstract description 54
- 238000000407 epitaxy Methods 0.000 claims abstract description 28
- -1 BF2 ion Chemical class 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 20
- 230000005684 electric field Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Abstract
The embodiment of the present invention provides a kind of method for improving VDMOS device breakdown voltage.This method includes：N-type epitaxy layer and oxide layer are grown successively on the surface of N-type substrate；Active area and partial pressure area are made successively, and the partial pressure area is the annulus of the circle centered on the active area, and the partial pressure area includes multiple p-type injection regions；The outside injection BF2 ion formation heavy doping P+ shallow junctions of the farthest p-type injection region of active area described in distance in the partial pressure area, the width of the heavy doping P+ shallow junctions is two times of the p-type injection sector width.The embodiment of the present invention injects BF2 ions formation heavy doping P+ shallow junctions by the outside of farthest apart from active area p-type injection region in partial pressure area, so that the depletion layer boundaries close to VDMOS surfaces become gentle, alleviate the surface curvature effect of electric field, improve the breakdown voltage on VDMOS surfaces, cut-off ring is eliminated simultaneously, VDMOS cost of manufacture is reduced.
Description
Technical field
The present embodiments relate to semiconductor applications, more particularly to a kind of raising VDMOS device breakdown voltage
Method.
Background technology
Vertical double diffused metal-oxide semiconductor field effect transistor (Vertical
Double-diffused Metal Oxide Semiconductor, abbreviation VDMOS) most important performance
Exactly block high pressure, device by design can in PN junction, Metals-semiconductor contacts, MOS interfaces
High pressure is born on depletion layer, with the increase of applied voltage, depletion layer electric-field intensity can also increase, finally
There is avalanche breakdown more than material limits.In the increase of device edge depletion region electric field curvature, electric field can be caused
Strength ratio die internal is big, and die edge snowslide can occur earlier than die internal during voltage is elevated
Puncture, in order to maximize the performance of device, it is necessary to design partial-pressure structure in device edge, reduce active area
The curvature of (cellular region) edge PN junction, extends laterally depletion layer, strengthens the resistance to pressure energy of horizontal direction
Power, makes the edge and inside of device while puncturing.
Junction terminal extension technology is to realize one of technology of partial-pressure structure, as shown in figure 1, in N-type substrate
On 11 grow N-type epitaxy layer 12, the surface of N-type epitaxy layer 12 by certain spacing implanting p-type from
The p-type injection region 14 of son generation certain intervals, the reverse of active area 16 has effectively been shared in partial pressure region 17
Voltage, improves the surface breakdown voltage of active area 16, but the depletion layer that p-type injection region 14 is formed
Border 13 can be restrained in electric field highest zone 15, cause the electric-field intensity of electric field highest zone 15 larger and
It is easily breakdown.
In order to alleviate the electric-field intensity of electric field highest zone 15, the breakdown potential of electric field highest zone 15 is improved
Pressure, as shown in Fig. 2 on the basis of Fig. 1, setting and cutting in the middle of partial pressure region 17 and dicing lane 18
Only ring 19, are specially to form N-type injection in the outside of the p-type injection region 14 farthest apart from active area 16
Area 20, changes the radius of curvature of original surrounding equipotential lines of p-type injection region 14, all equipotential lines would not
A point is pointed to simultaneously, the electric-field intensity of electric field highest zone 15 is alleviated, while improving electric field highest
The breakdown voltage in region 15, but introduce the cost of manufacture that device is improved after cut-off ring 19.Therefore,
VDMOS device breakdown voltage, and reduction element manufacturing cost can be improved by lacking one kind in the prior art
Method.
The content of the invention
A kind of method that the embodiment of the present invention provides raising VDMOS device breakdown voltage, to improve VDMOS
Switching characteristic.
The one side of the embodiment of the present invention is to provide a kind of method for improving VDMOS device breakdown voltage,
Including：
N-type epitaxy layer and oxide layer are grown successively on the surface of N-type substrate；
Active area and partial pressure area are made successively, and the partial pressure area is the annulus of the circle centered on the active area,
The partial pressure area includes multiple p-type injection regions；
The outside injection BF2 ions of the farthest p-type injection region of active area described in distance in the partial pressure area
Heavy doping P+ shallow junctions are formed, the width of the heavy doping P+ shallow junctions is the two of the p-type injection sector width
Times.
The method provided in an embodiment of the present invention for improving VDMOS device breakdown voltage, by partial pressure area
The outside injection BF2 ion formation heavy doping P+ shallow junctions of the p-type injection region farthest apart from active area so that
Depletion layer boundaries close to VDMOS surfaces become gentle, alleviate the surface curvature effect of electric field, improve
The breakdown voltage on VDMOS surfaces, while eliminating cut-off ring, reduces VDMOS cost of manufacture.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section of VDMOS in the prior art；
Fig. 2 is the diagrammatic cross-section of VDMOS in the prior art；
Fig. 3 is the method flow diagram provided in an embodiment of the present invention for improving VDMOS device breakdown voltage；
Fig. 4 is the diagrammatic cross-section for performing VDMOS in manufacturing process of the embodiment of the present invention；
Fig. 5 is the diagrammatic cross-section for performing VDMOS in manufacturing process of the embodiment of the present invention；
Fig. 6 is the top view of VDMOS during execution present invention method；
Fig. 7 is the diagrammatic cross-section for performing VDMOS in manufacturing process of the embodiment of the present invention；
The method flow diagram for the raising VDMOS device breakdown voltage that Fig. 8 provides for another embodiment of the present invention；
Fig. 9 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 10 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 11 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 12 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
The method flow for the raising VDMOS device breakdown voltage that Figure 13 provides for another embodiment of the present invention
Figure；
Figure 14 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 15 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 16 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 17 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process；
Figure 18 is the diagrammatic cross-section for performing VDMOS in another embodiment of the present invention manufacturing process.
Embodiment
Fig. 1 is the method flow diagram provided in an embodiment of the present invention for improving VDMOS device breakdown voltage.For
To the method in the present embodiment understand the description of system, the present embodiments relate to
VDMOS diagrammatic cross-section is the corresponding structural representation of half of the complete sections of VDMOS.Fig. 2,
Fig. 3, Fig. 4, Fig. 5, Fig. 7 illustrate for the section of VDMOS during execution present invention method
Figure, Fig. 6 is the top view of VDMOS during execution present invention method, as shown in figure 1,
Methods described includes：
Step S101, on the surface of N-type substrate N-type epitaxy layer and oxide layer are grown successively；
Grow N-type epitaxy layer and oxide layer successively on the surface of N-type substrate, perform after step S101
VDMOS diagrammatic cross-section as shown in figure 4, wherein, N-type substrate is represented with 11, N-type epitaxy layer
Represented with 12, oxide layer is represented with 30.
Step S102, make active area and partial pressure area successively, the partial pressure area be using the active area in
The annulus of heart circle, the partial pressure area includes multiple p-type injection regions；
Active area and partial pressure area are made by existing technique, specific manufacturing process is by following implementation
Example is explained, and the partial pressure area is the annulus of the circle centered on the active area, and the partial pressure area includes
Multiple p-type injection regions, perform the diagrammatic cross-section of the VDMOS after step S102 as shown in figure 5, its
In, active area is represented with 16, and partial pressure area represents that dicing lane is represented with 18 with 17, and p-type injection region is used
14 are represented, the depletion layer boundaries that p-type injection region 14 is formed are represented with 13.
VDMOS top view is illustrated in figure 6, wherein, active area 16 is located at center, partial pressure area
17 be the circle ring area around active area 16, and dicing lane 18 is the circle ring area around partial pressure area 17.
Step S103, in the partial pressure area the farthest p-type injection region of active area described in distance outside note
Enter BF2 ions formation heavy doping P+ shallow junctions, the width of the heavy doping P+ shallow junctions is the p-type injection
Two times of sector width；
On the basis of such as Fig. 5, the p-type injection region 14 farthest apart from active area 16 in partial pressure area 17
Outside injection BF2 ions formation heavy doping P+ shallow junctions, the width of the heavy doping P+ shallow junctions is described
P-type injection two times of sector width, perform the diagrammatic cross-section of the VDMOS after step S103 as shown in fig. 7,
P-type injection region represents that heavy doping P+ shallow junctions are represented with 31 with 14, the width of heavy doping P+ shallow junctions 31
It it is two times or two times of p-type injection region 14 or so, p-type injection region 14 and heavy doping P+ are shallow
Knot 31 formation depletion layer boundaries represented with 13, depletion layer boundaries 13 as shown in Figure 7, close to VDMOS
The depletion layer boundaries on surface become gentle, alleviate the surface curvature effect of electric field, improve VDMOS tables
The breakdown voltage in face, while eliminating cut-off ring, reduces VDMOS cost of manufacture.
It is preferred that, the outside of the heavy doping P+ shallow junctions and the p-type injection region farthest apart from the active area
Edge is connected.As shown in fig. 7, heavy doping P+ shallow junctions 31 and the p-type note farthest apart from the active area
Enter the outer ledge connection in area 14.
It is preferred that, in embodiments of the present invention, the energy of injection BF2 ions is the one of ring region Implantation Energy
Half, the dosage for injecting BF2 ions is identical with the dosage that ring region is injected.Ring region injection is to form p-type injection
One step in area, subsequent embodiment will illustrate the process that ring region is injected.
The embodiment of the present invention is injected by the outside of farthest apart from active area p-type injection region in partial pressure area
BF2 ions formation heavy doping P+ shallow junctions so that the depletion layer boundaries close to VDMOS surfaces become gentle,
The surface curvature effect of electric field is alleviated, the breakdown voltage on VDMOS surfaces is improved, cut while eliminating
Only ring, reduces VDMOS cost of manufacture.
The method flow diagram for the raising VDMOS device breakdown voltage that Fig. 8 provides for another embodiment of the present invention.
In order to the method in the present embodiment understand the description of system, Fig. 9-12 is the execution embodiment of the present invention
VDMOS diagrammatic cross-section in procedure, the embodiment of the present invention is illustrated in above-mentioned steps S102 and made
Make the specific method of active area, as shown in figure 8, methods described includes：
Step S201, the presumptive area in the oxide layer upper surface lay photoresist, and photoresist is not laid
Region be border circular areas；
On the basis of Fig. 4, the presumptive area in the upper surface of oxide layer 30 lays photoresist, performs step
The diagrammatic cross-section of VDMOS after S201 is as shown in figure 9, the photoresist of laying is represented with 32, not
The region of laying photoresist is represented with 33, is the upper table in partial pressure area 17 and dicing lane 18 corresponding to Fig. 6
Photoresist is laid in face, and the region that photoresist is not laid is active area 16.
Step S202, use wet etching remove do not lay the oxide layer in photoresist region with expose it is described not
Lay the N-type epitaxy layer below photoresist region；
On the basis of Fig. 9, the oxide layer 30 for not laying photoresist region 33 is removed using wet etching,
To expose the N-type epitaxy layer 12 for not laying the lower section of photoresist region 33, perform after step S202
VDMOS diagrammatic cross-section is as shown in Figure 10.
Step S203, remove the photoresist to expose the oxide layer of the presumptive area；
On the basis of Figure 10, photoresist 32 is removed to expose the oxide layer 30 of presumptive area, step is performed
The diagrammatic cross-section of VDMOS after rapid S203 is as shown in figure 11.
Step S204, it is JFET in the N-type epitaxy layer upper surface exposed and injects to form JFET areas, institute
State the N-type epitaxy layer below JFET areas and the JFET areas, N-type substrate and constitute the active area.
On the basis of Figure 11, junction field effect transistor is done in the upper surface for the N-type epitaxy layer 12 exposed
Pipe (Junction Field-Effect Transistor, abbreviation JFET) injection forms JFET areas, performs step
As shown in figure 12, JFET areas are represented the diagrammatic cross-section of VDMOS after rapid S204 with 34, then JFET
Area 34, the N-type epitaxy layer 12 of the lower section of JFET areas 34 and N-type substrate 11 constitute the active area 16.
It is preferred that, injection JFET energy is 50KeV-150KeV, and implantation dosage is 12 powers.Note
The purpose for entering JFET is to reduce VDMOS JFET resistance.
The embodiment of the present invention specifically details the processing step for making active area.
The method flow for the raising VDMOS device breakdown voltage that Figure 13 provides for another embodiment of the present invention
Figure.In order to the method in the present embodiment understand the description of system, Figure 14-18 is to perform the present invention
VDMOS diagrammatic cross-section in embodiment procedure, the embodiment of the present invention illustrates above-mentioned steps
The specific method in partial pressure area is made in S102, as shown in figure 13, methods described includes：
Step S301, the upper surface laying photoresist in the JFET areas；
On the basis of Figure 12, photoresist is laid in the upper surface in JFET areas 34, step S301 is performed
As shown in figure 14, the photoresist of laying is represented the diagrammatic cross-section of VDMOS afterwards with 35.
Step S302, multiple annular regions in the oxide layer upper surface of the presumptive area lay photoresist,
The multiple annular region is centered on the active area, and the width of the multiple annular region is along active
District center outwardly direction is incremented by successively, and the pore width between adjacent annular region is equal；
On the basis of Figure 14, multiple annular regions in the upper surface of the oxide layer 30 of presumptive area are spread
If photoresist, the diagrammatic cross-section for performing the VDMOS after step S302 is as shown in figure 15, Duo Gehuan
It is equipped with photoresist 37 on the (not shown) of shape region, and along the center outwardly direction light of active area 16
The width of photoresist 37 is incremented by successively, and the width of hole 36 between adjacent photoresist 37 is equal.
Step S303, use wet etching remove do not lay the oxide layer in photoresist region with expose it is described not
Lay the N-type epitaxy layer below photoresist region；
On the basis of Figure 15, removed using wet etching and do not lay the photoresist region i.e. oxygen of hole 36
Change layer 30 does not lay the N-type epitaxy layer 12 of the lower section of photoresist region 36 to expose, and performs step S303
The diagrammatic cross-section of VDMOS afterwards is as shown in figure 16.
Step S304, in the N-type epitaxy layer upper surface exposed do ring region injection；
On the basis of Figure 16, ring region injection is done in the upper surface of N-type epitaxy layer 12 exposed, is specially
In the upper surface implanting p-type ion of N-type epitaxy layer 12 exposed, the VDMOS after step S304 is performed
Diagrammatic cross-section as shown in figure 17, the p-type ion of injection is represented with 38.
Step S305, the removal photoresist, and the region progress ring region injected to ring region drives in processing shape
Into p-type injection region.
Photoresist 35 and 37 is removed on the basis of Figure 17, carrying out ring region to the region that ring region is injected drives in
Processing forms p-type injection region 14, performs diagrammatic cross-section such as Figure 18 of the VDMOS after step S305
It is shown.It is the structure shown in Fig. 5 to remove the oxide layer 30 described in Figure 18.
It is preferred that, the energy of the ring region injection is 50KeV-150KeV, and implantation dosage is 15 powers.
It is preferred that, the ring region is driven in for activating injection ion and silicon formation covalent bond, makes the injection
Ion is at high temperature to the N-type epitaxy layer diffusion inside, so as to form one in the N-type epitaxy layer
The Ring knots of p-type.
The embodiment of the present invention specifically details the processing step for making partial pressure area.
In summary, BF2 is injected by the outside of farthest apart from active area p-type injection region in partial pressure area
Ion formation heavy doping P+ shallow junctions so that the depletion layer boundaries close to VDMOS surfaces become gentle, alleviate
The surface curvature effect of electric field, improves the breakdown voltage on VDMOS surfaces, while cut-off ring is eliminated,
Reduce VDMOS cost of manufacture.
In several embodiments provided by the present invention, it should be understood that disclosed apparatus and method,
It can realize by another way.For example, device embodiment described above is only schematical,
For example, the division of the unit, only a kind of division of logic function, can have in addition when actually realizing
Dividing mode, such as multiple units or component can combine or be desirably integrated into another system, or
Some features can be ignored, or not perform.It is another, shown or discussed coupling each other or
Direct-coupling or communication connection can be the INDIRECT COUPLING or communication link of device or unit by some interfaces
Connect, can be electrical, machinery or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, make
It can be for the part that unit is shown or may not be physical location, you can with positioned at a place,
Or can also be distributed on multiple NEs.Can select according to the actual needs part therein or
Person's whole units realize the purpose of this embodiment scheme.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit,
Can also be that unit is individually physically present, can also two or more units be integrated in a list
In member.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ hardware adds software
The form of functional unit is realized.
The above-mentioned integrated unit realized in the form of SFU software functional unit, can be stored in a computer
In read/write memory medium.Above-mentioned SFU software functional unit is stored in a storage medium, including some fingers
Order is to cause a computer equipment (can be personal computer, server, or network equipment etc.)
Or processor (processor) performs the part steps of each embodiment methods described of the invention.And it is foregoing
Storage medium include：USB flash disk, mobile hard disk, read-only storage (Read-Only Memory, ROM),
Random access memory (Random Access Memory, RAM), magnetic disc or CD etc. are various can be with
The medium of store program codes.
Those skilled in the art can be understood that, for convenience and simplicity of description, only with above-mentioned each
The division progress of functional module is for example, in practical application, as needed can divide above-mentioned functions
With by different functional module completions, i.e., the internal structure of device is divided into different functional modules, with
Complete all or part of function described above.The specific work process of the device of foregoing description, can be with
With reference to the corresponding process in preceding method embodiment, it will not be repeated here.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, and
The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a kind of method for improving VDMOS device breakdown voltage, it is characterised in that including：
N-type epitaxy layer and oxide layer are grown successively on the surface of N-type substrate；
Active area and partial pressure area are made successively, and the partial pressure area is the annulus of the circle centered on the active area,
The partial pressure area includes multiple p-type injection regions；
The outside injection BF2 ions of the farthest p-type injection region of active area described in distance in the partial pressure area
Heavy doping P+ shallow junctions are formed, the width of the heavy doping P+ shallow junctions is the two of the p-type injection sector width
Times.
2. according to the method described in claim 1, it is characterised in that the heavy doping P+ shallow junctions and away from
The outer ledge connection of the p-type injection region farthest from the active area.
3. method according to claim 2, it is characterised in that injecting the energy of BF2 ions is
The half of ring region Implantation Energy, the dosage for injecting BF2 ions is identical with the dosage that ring region is injected.
4. method according to claim 3, it is characterised in that the making active area, including：
Presumptive area in the oxide layer upper surface lays photoresist, and it is circle that the region of photoresist is not laid
Shape region；
Use wet etching to remove not laying the oxide layer in photoresist region and described do not lay photoresist to expose
N-type epitaxy layer below region；
The photoresist is removed to expose the oxide layer of the presumptive area；
In the N-type epitaxy layer upper surface exposed JFET is to inject to form JFET areas, the JFET areas and
N-type epitaxy layer, N-type substrate below the JFET areas constitute the active area.
5. method according to claim 4, it is characterised in that injection JFET energy is
50KeV-150KeV, implantation dosage is 12 powers.
6. method according to claim 5, it is characterised in that the making partial pressure area, including：
Photoresist is laid in the upper surface in the JFET areas；
Multiple annular regions in the oxide layer upper surface of the presumptive area lay photoresist, the multiple
Annular region centered on the active area, the width of the multiple annular region along active district center to
Outer direction is incremented by successively, and the pore width between adjacent annular region is equal；
Use wet etching to remove not laying the oxide layer in photoresist region and described do not lay photoresist to expose
N-type epitaxy layer below region；
Ring region injection is done in the N-type epitaxy layer upper surface exposed；
The photoresist is removed, and ring region is carried out to the region that ring region is injected and drives in processing formation p-type injection
Area.
7. method according to claim 6, it is characterised in that the energy of the ring region injection is
50KeV-150KeV, implantation dosage is 15 powers.
8. method according to claim 6, it is characterised in that the ring region is driven in for activating note
Enter ion and silicon formation covalent bond, make the injection ion at high temperature to expansion inside the N-type epitaxy layer
Dissipate, so as to form the Ring knots of a p-type in the N-type epitaxy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610137943.8A CN107180763B (en) | 2016-03-10 | 2016-03-10 | Method for improving breakdown voltage of VDMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610137943.8A CN107180763B (en) | 2016-03-10 | 2016-03-10 | Method for improving breakdown voltage of VDMOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107180763A true CN107180763A (en) | 2017-09-19 |
| CN107180763B CN107180763B (en) | 2020-03-06 |
Family
ID=59830057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610137943.8A Active CN107180763B (en) | 2016-03-10 | 2016-03-10 | Method for improving breakdown voltage of VDMOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107180763B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054195A (en) * | 2017-12-08 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Semiconductor power device and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445054B1 (en) * | 1999-08-11 | 2002-09-03 | Dynex Semiconductor Limited | Semiconductor device |
| US20040119087A1 (en) * | 2002-08-28 | 2004-06-24 | Ixys Corporation | Breakdown voltage for power devices |
| CN103887327A (en) * | 2013-11-29 | 2014-06-25 | 杭州恩能科技有限公司 | Semiconductor device terminal reliability reinforcing technology |
| CN204696121U (en) * | 2015-06-19 | 2015-10-07 | 深圳市谷峰电子有限公司 | A kind of terminal structure of high-voltage MOSFET device |
-
2016
- 2016-03-10 CN CN201610137943.8A patent/CN107180763B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445054B1 (en) * | 1999-08-11 | 2002-09-03 | Dynex Semiconductor Limited | Semiconductor device |
| US20040119087A1 (en) * | 2002-08-28 | 2004-06-24 | Ixys Corporation | Breakdown voltage for power devices |
| CN103887327A (en) * | 2013-11-29 | 2014-06-25 | 杭州恩能科技有限公司 | Semiconductor device terminal reliability reinforcing technology |
| CN204696121U (en) * | 2015-06-19 | 2015-10-07 | 深圳市谷峰电子有限公司 | A kind of terminal structure of high-voltage MOSFET device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054195A (en) * | 2017-12-08 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Semiconductor power device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107180763B (en) | 2020-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6693131B2 (en) | Semiconductor device | |
| CN104969360A (en) | Semiconductor device | |
| US10453931B2 (en) | Semiconductor device having termination trench | |
| CN106463503A (en) | Semiconductor device | |
| JP6026418B2 (en) | Bipolar non-punch-through power semiconductor device | |
| US9455319B2 (en) | Semiconductor device | |
| CN104078364A (en) | Method of manufacturing a super-junciton semiconductor device | |
| CN117913146A (en) | Charge carrier extraction reverse diode | |
| TW201222649A (en) | HV Schottky diode with dual guard regions | |
| US10181513B2 (en) | Power device configured to reduce electromagnetic interference (EMI) noise | |
| CN102751317B (en) | Enhancing schottky breakdown voltage (BV) without affecting an integrated MOSFET-schottky device layout | |
| CN104979398A (en) | Semiconductor Device and Method for Forming a Semiconductor Device | |
| CN101114583A (en) | Semiconductor power device and manufacturing method thereof | |
| JP2017084998A (en) | Super junction mosfet device and semiconductor chip | |
| JP2002164542A (en) | Integrated circuit device and its fabricating method | |
| JP6648429B2 (en) | Semiconductor device | |
| CN106298479B (en) | A kind of the knot terminal expansion structure and its manufacturing method of power device | |
| CN104269437A (en) | LDMOS device with double-layer shielding rings and manufacturing method of LDMOS device | |
| CN107180763A (en) | The method for improving VDMOS device breakdown voltage | |
| CN106960867B (en) | Insulated gate bipolar transistor device | |
| CN113097287A (en) | IGBT chip terminal structure and manufacturing method thereof | |
| CN111066148B (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
| CN106340534A (en) | Field limit loop and junction terminal expansion complex pressure dividing structure and manufacturing method thereof | |
| CN105185830A (en) | Power transistor and junction termination structure thereof | |
| CN106783940B (en) | Power semiconductor device with edge termination structure of gradual change concentration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |