CN108493167A - The barrier enclosure production method and barrier enclosure structure of chip - Google Patents
The barrier enclosure production method and barrier enclosure structure of chip Download PDFInfo
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- CN108493167A CN108493167A CN201810385620.XA CN201810385620A CN108493167A CN 108493167 A CN108493167 A CN 108493167A CN 201810385620 A CN201810385620 A CN 201810385620A CN 108493167 A CN108493167 A CN 108493167A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 144
- 239000002184 metal Substances 0.000 claims abstract description 144
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 claims abstract description 34
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 51
- 239000004033 plastic Substances 0.000 claims description 40
- 238000005516 engineering process Methods 0.000 claims description 29
- 239000005022 packaging material Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 6
- 239000010935 stainless steel Substances 0.000 claims description 6
- 229910001220 stainless steel Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 238000010079 rubber tapping Methods 0.000 claims description 2
- 239000011888 foil Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 23
- 150000002739 metals Chemical class 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000005286 illumination Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005553 drilling Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 235000013399 edible fruits Nutrition 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910000975 Carbon steel Inorganic materials 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000010962 carbon steel Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of barrier enclosure production methods of chip and barrier enclosure structure, this method to include：The lower surface of metallic carrier is etched, groove structure is formed in the metallic carrier bottom；Wherein, the metal lead wire frame on the metallic carrier is located in the groove structure, and the upper and lower surface of the metallic carrier all has metal film layer；On being formed by structure, using attachment process by the chip attachment in the groove structure, and the metallic carrier is mounted on to the surface of printed circuit board；Using attachment process, metal cover is mounted on the metal film layer at the top of the groove structure so that the metal cover forms barrier enclosure structure with the groove structure.Barrier enclosure structure fabrication processes made by the above method are simple, and packaging cost is low.
Description
Technical field
The present invention relates to chip technology fields, more particularly to the barrier enclosure production method and barrier enclosure of a kind of chip
Structure.
Background technology
Currently, with the continuous development of technology, in order to reduce the volume of equipment, integrated state is presented in more and more circuits
Gesture, so that the application of chip is more and more extensive.With MEMS (Micro-Electro-Mechanical
Systems, abbreviation MEMS) for chip, common product has MEMS microphone, MEMS barometers etc..But most of MEMS
Device is very sensitive to electromagnetic interference, needs to carry out certain encapsulation to these devices to be electromagnetically shielded.
In MEMS package structure in traditional technology, mainly by the way that MEMS device to be protected is fixedly connected on substrate
On, and to MEMS device affixed metal screening cover to be protected, to be electromagnetically shielded to MEMS device to be protected.The structure
In substrate by multilager base plate material carry out punching press, punching, it is green paint etc. techniques be made.
But it is that chip-packaging structure used by electromagnetic interference, complex manufacturing technology is avoided to be packaged into traditional technology
This height.
Invention content
Based on this, it is necessary to which complicated for the packaging manufacturing process of traditional technology chips, the high problem of packaging cost carries
For the barrier enclosure production method and barrier enclosure structure of a kind of chip.
In a first aspect, the present invention provides a kind of barrier enclosure production method of chip, including：
The lower surface of metallic carrier is etched, groove structure is formed in the metallic carrier bottom；Wherein, the gold
The metal lead wire frame belonged on carrier is located in the groove structure, and the upper and lower surface of the metallic carrier all has metallic film
Layer；
On being formed by structure, using attachment process by the chip attachment in the groove structure, and by institute
State the surface that metallic carrier is mounted on printed circuit board；
Using attachment process, metal cover is mounted on the metal film layer at the top of the groove structure so that the gold
Belong to lid and forms barrier enclosure structure with the groove structure.
The barrier enclosure production method of above-mentioned provided chip, is etched by the lower surface to metallic carrier,
Groove structure is formed on metallic carrier bottom, wherein the side wall for surrounding groove structure is a part for encapsulating structure, can play electricity
The effect of magnetic screen, the side wall are effectively utilized part metals carrier, by part metals carrier as barrier enclosure structure
Packaging cost is greatly saved in a part；Also, the metal cover of the present embodiment is planar structure, without complicated Sheet Metal Forming Technology
It can make to obtain the metal cover of plane, manufacture craft is simple.
The lower surface to metallic carrier is etched in one of the embodiments, in the metallic carrier bottom
Groove structure is formed, including：
Using photochemical etching process, the lower surface of the metallic carrier is etched, until the die-attach area
Frame is in naked state, to form groove structure in the metallic carrier bottom.
The barrier enclosure production method of above-mentioned provided chip, is etched by the lower surface to metallic carrier,
Groove structure is formed on metallic carrier bottom, and the side wall for surrounding groove structure is a part for encapsulating structure, can play electromagnetic screen
The effect covered is effectively utilized part metals carrier, by part metals carrier as a part for barrier enclosure structure, greatly
Packaging cost is saved greatly.
The method further includes in one of the embodiments,：
Tapping reason is carried out on the metal cover, obtains at least one through-hole.
The barrier enclosure production method of above-mentioned provided chip obtains having logical by drilling on metal cover
The metal cover in hole can make chip receive the signals such as extraneous sound or air, to facilitate chip to received signal into
Row processing so that obtained barrier enclosure structure can be applicable to receive the chip of outer signals, improve barrier enclosure
The scope of application of structure.
The lower surface to metallic carrier is etched in one of the embodiments, in the metallic carrier bottom
It is formed before groove structure, further includes：
Copper film layer is respectively coated in the upper and lower surface of SPCC substrates or stainless steel substrate, obtains original metal carrier；
Using coating, exposure and electroplating technology, metal lead wire frame is formed on the original metal carrier, and obtain institute
State metallic carrier；Wherein, the metal lead wire frame includes：It is electrically connected described in the first lead frame and the electrical connection of the chip
Second lead frame of printed circuit board.
The barrier enclosure production method of above-mentioned provided chip carries out on the original metal carrier of coating copper film layer
Coating twice, exposure and electroplating technology, you can obtain the first lead frame of electrical connection chip and be electrically connected printed circuit board
Second lead frame, manufacture craft are simple.
It is described using coating, exposure and electroplating technology in one of the embodiments, the shape on the original metal carrier
At metal lead wire frame, and the metallic carrier is obtained, including：
The first photoresist layer is deposited on the first metal film layer of original metal carrier upper surface, and to described
One photoresist layer is exposed, and forms the first figure layer, has multiple first opening areas, first gold medal in first figure layer
It is in naked state to belong to film layer by first opening area；
The first metal film layer at multiple first opening areas is electroplated, first lead frame is obtained
Frame；
The second photoresist layer is deposited on being formed by structure, and second photoresist layer is exposed, and forms the
There are in second figure layer two figure layers multiple second opening areas, first lead frame to pass through second aperture area
Domain is in naked state；
The first lead frame at multiple second opening areas is electroplated, the second lead frame is obtained；
Remove remaining first photoresist layer and the second photoresist layer, obtain the metallic carrier the first lead frame and
Second lead frame.
The barrier enclosure production method of above-mentioned provided chip, it is enterprising in the metallic carrier for coating the first metal film layer
Row coats twice, exposes and electroplating technology, you can obtains the first lead frame be electrically connected with chip and electric with printed circuit board
Second lead frame of connection, manufacture craft are simple.
The method further includes in one of the embodiments,：
The gap structure in the lead frame of the metallic carrier is filled using plastic packaging material, obtains the first lead after plastic packaging
The second lead frame after frame and plastic packaging.
The barrier enclosure production method of above-mentioned provided chip fills the first photoresist layer of removal and the using plastic packaging material
The gap structure of two photoresist layers, you can obtain the metal lead wire frame of plastic packaging material package, manufacture craft is simple, and uses plastic packaging
The metal lead wire frame of material package can play a supporting role to chip.In addition, plastic packaging material price is relatively low, encapsulation is greatly reduced
Cost.
The method further includes in one of the embodiments,：
Polishing treatment is ground to the surface of the metallic carrier after plastic packaging；
And/or
Trepanning processing is carried out to the surface of the metallic carrier after plastic packaging, obtains at least one through-hole.
The barrier enclosure production method of above-mentioned provided chip obtains having logical by drilling on metal cover
The metal cover in hole can make chip receive the signals such as extraneous sound or air, to facilitate chip to received signal into
Row processing so that obtained barrier enclosure structure can be applicable to receive the chip of outer signals, improve barrier enclosure
The scope of application of structure.
The chip includes application-specific integrated circuit ASIC chip and MEMS chip in one of the embodiments,.
Second aspect, the present invention also provides a kind of chip barrier enclosure structures, including：Bottom have groove structure and on
Lower surface all has the metallic carrier, chip and metal cover of metal film layer, the metal that the chip passes through the metallic carrier
Lead frame is electrically connected in the groove structure；
The metal cover is fixed on the metal film layer at the top of the groove structure, is formed and is shielded with the groove structure
Encapsulating structure.
The chip includes application-specific integrated circuit ASIC chip and MEMS chip, the gold in one of the embodiments,
Category, which covers, is provided at least one through-hole.
Metal lead wire frame is embedded in plastic packaging material in one of the embodiments, to form the branch for supporting the chip
Support structure, and the both ends of the metal lead wire frame are in naked state, for connecting the chip and printed circuit board.
The barrier enclosure production method and barrier enclosure structure of chip provided by the invention, pass through the following table to metallic carrier
Face is etched, and forms groove structure in metallic carrier bottom, side wall is a part for encapsulating structure, can play electromagnetic screen
The effect covered is effectively utilized part metals carrier, by part metals carrier as a part for barrier enclosure structure, greatly
Packaging cost is saved greatly.In addition, seam of the present invention using plastic packaging material filling removal the first photoresist layer and the second photoresist layer
Gap structure, you can obtain the metal lead wire frame of plastic packaging material package, manufacture craft is simple, and plastic packaging material price is relatively low, further
Reduce packaging cost.
Description of the drawings
Fig. 1 is the barrier enclosure production method flow diagram for the chip that one embodiment provides；
Fig. 1 a are the structural schematic diagram for the metallic carrier that one embodiment provides；
Fig. 1 b are the structural schematic diagram for the A that another embodiment provides；
Fig. 1 c are the structural schematic diagram for the B that another embodiment provides；
Fig. 1 d are the structural schematic diagram for the C that another embodiment provides；
Fig. 1 e are the structural schematic diagram for the D that another embodiment provides；
Fig. 2 is the structural schematic diagram for the E that another embodiment provides；
Fig. 3 is the flow diagram of the barrier enclosure production method for the chip that another embodiment provides；
Fig. 3 a are the structural schematic diagram for the original metal carrier that another embodiment provides；
Fig. 3 b are the structural schematic diagram for the F that another embodiment provides；
Fig. 4 is the flow diagram of the barrier enclosure production method for the chip that another embodiment provides；
Fig. 4 a are the structural schematic diagram for the H that another embodiment provides；
Fig. 4 b are the structural schematic diagram for the I that another embodiment provides；
Fig. 4 c are the structural schematic diagram for the J that another embodiment provides；
Fig. 4 d are the structural schematic diagram for the K that another embodiment provides；
Fig. 4 e are the structural schematic diagram for the L that another embodiment provides；
Fig. 4 f are the structural schematic diagram for the M that another embodiment provides；
Fig. 4 g are the structural schematic diagram for the N that another embodiment provides；
Fig. 5 is the structural schematic diagram for the O that another embodiment provides；
Fig. 6 is the barrier enclosure structure sectional view that one embodiment provides；
Fig. 7 is the barrier enclosure structure sectional view that another embodiment provides；
Fig. 8 is the barrier enclosure structure sectional view that another embodiment provides.
Reference sign：
1012：Metallic carrier； 1013：Substrate； 1014：First metal film layer；
1015：Second metal film layer； 1016：The side wall of groove structure； 1017：Metal lead wire frame；
1018：Chip； 1019：Routing； 1020：Black glue；
1021：Metal cover； 1022：Photoresist layer； 1023：Through-hole；
1024：Original metal carrier； 1025：First lead frame； 1026：Second lead frame；
1027：Asic chip； 1028：MEMS chip； 1029：First photoresist layer；
1030：First opening area； 1031：Second opening area； 1032：Second photoresist layer；
1033：Plastic packaging material.
Specific implementation mode
With the continuous development of chip technology, the application of chip is more and more extensive.But big multi-chip to electromagnetic interference very
Sensitivity needs to carry out certain encapsulation to these chips to be electromagnetically shielded.Barrier enclosure structure can be used in protecting chip
It is not influenced by electromagnetic interference, chip can also be made to be easily installed and transport using barrier enclosure structure.
Chip is generally fixedly connected on multilager base plate by the barrier enclosure structure in traditional technology, and to chip attachment gold
Belong to screening cover to be electromagnetically shielded.But it is to avoid chip-packaging structure used by electromagnetic interference, manufacture craft in traditional technology
Complexity, packaging cost are high.The barrier enclosure production method of chip provided by the invention aims to solve the problem that the technology as above of traditional technology
Problem.
In order to make the purpose , technical scheme and advantage of the present invention be clearer, by following embodiments and in conjunction with attached
Figure, technical solution in the embodiment of the present invention are described in further details.It should be appreciated that specific embodiment described herein
Only to explain the present invention, it is not intended to limit the present invention.These specific embodiments can be combined with each other below, for phase
Same or similar concept or process may repeat no more in certain embodiments.
Fig. 1 is the barrier enclosure production method flow diagram for the chip that one embodiment provides, as shown in Figure 1, chip
Barrier enclosure production method include：
S101 is etched the lower surface of metallic carrier 1012, and groove knot is formed in 1012 bottom of the metallic carrier
Structure；Wherein, the metal lead wire frame 1017 on the metallic carrier 1012 is located in the groove structure, the metallic carrier
1012 upper and lower surface all has metal film layer.
Specifically, a part for metallic carrier 1012 of the present embodiment using substrate 1013 as encapsulation, optionally, substrate
1013 be cuboid, in order to be subsequently etched to it.The upper and lower surface of substrate 1013 all has metal film layer, gold
It includes the first metal film layer 1014 and the second metal film layer 1015 to belong to film layer, and 1012 upper surface of metallic carrier has metal
The structure of lead frame 1017, metallic carrier 1012 may refer to shown in Fig. 1 a.Optionally, the first metal film layer 1014 and
Two metal film layers 1015 can be layers of copper.
In the present embodiment, 1012 lower surface of metallic carrier is etched, is formed in 1012 bottom of above-mentioned metallic carrier recessed
Slot structure.Optionally, the thickness of the side wall 1016 of groove structure can be 2 microns to 50 microns.Gold on metallic carrier 1012
Belong to lead frame 1017 to be located in groove structure.Optionally, metal lead wire frame 1017 can be copper lead frame, because of copper conduction
Performance is good, and price is relatively low, therefore, can improve electric conductivity with copper lead frame, and cost-effective.Step S101
Structure A is formed by can be found in shown in Fig. 1 b.
S102 is formed by S101 in structure, and the chip 1018 is mounted on the groove knot using attachment process
In structure, and the metallic carrier 1012 is mounted on to the surface of printed circuit board.
Specifically, in the structure that step S101 is formed by Fig. 1 b, chip 1018 is mounted on above-mentioned die-attach area
On frame 1017, and the pad on chip 1018 is linked together by routing 1019 and metal lead wire frame 1017, then
Black glue 1020 is pasted at routing 1019 on 1018 surface of 1018 surface of chip and chip, structure B is formed, referring specifically to Fig. 1 c
(Fig. 1 c are structrural build up after Fig. 1 b are inverted).Optionally, routing 1019 can be the wires such as gold thread, aluminum steel.It can
Choosing, above-mentioned black glue 1020 is epoxy resin, the routing 1019 for protecting 1018 surface of chip 1018 and chip.
Metal cover 1021 is mounted on the metal film layer at the top of the groove structure, is made using attachment process by S103
It obtains the metal cover 1021 and forms barrier enclosure structure with the groove structure.
Specifically, after step S102, the metallic film that the metal cover 1021 made is mounted at the top of groove structure
On layer, structure C is formed, referring specifically to Fig. 1 d.Optionally, metal cover 1021 can also be replaced with electrically-conductive backing plate.
The barrier enclosure production method of chip provided in this embodiment, is etched by the lower surface to metallic carrier,
Groove structure is formed in metallic carrier bottom, wherein the side wall for surrounding groove structure is a part for encapsulating structure, can be played
The effect of electromagnetic shielding, the side wall are effectively utilized part metals carrier, by part metals carrier as barrier enclosure structure
A part, packaging cost is greatly saved；Also, the metal cover of the present embodiment is planar structure, without complicated presser
Skill can make to obtain the metal cover of plane, and manufacture craft is simple.
In another embodiment, the present embodiment refers to be etched the lower surface of metallic carrier 1012, obtains
The detailed process of groove structure.On the basis of the above embodiments, i.e., above-mentioned S101 may include：Using photochemical etching work
Skill is etched the lower surface of the metallic carrier 1012, until the metal lead wire frame 1017 be in naked state, with
Groove structure is formed on 1012 bottom of the metallic carrier.
Specifically, the lower surface of the structure shown in Fig. 1 a deposits a layer photoresist, photoresist layer 1022, the knot of formation are formed
Structure D is specifically as shown in fig. le.Optionally, the both ends part on 1014 surface of the first metal film layer of metallic carrier 1012 does not deposit
Photoresist, this both ends are used in manufacture craft be clamped the part of metallic carrier 1012.And using illumination to photoresist layer 1022 into
Row exposure, then removes photoresist, and the region for needing to etch is presented on metallic carrier 1012.Finally utilize chemical solution to needing
The region to be etched carries out dissolved corrosion, until metal lead wire frame 1017 is in naked state, that is, forms the structure of Fig. 1 b.It is optional
, above-mentioned illumination can be ultraviolet light.Optionally, above-mentioned chemical solution can be strong acid liquid.Metallic carrier 1012 is lost
After quarter, groove structure can be formed in 1012 bottom of metallic carrier, the metallic carrier 1012 after etching forms groove structure.It is optional
, metallic carrier 1012 can also be etched using acid etching carving technology.Optionally, the side wall 1016 of groove structure
Thickness can be 2 microns to 50 microns.
The barrier enclosure production method of chip provided in this embodiment, is etched by the lower surface to metallic carrier,
Groove structure is formed in metallic carrier bottom, the side wall for surrounding groove structure is a part for encapsulating structure, can play electromagnetism
The effect of shielding is effectively utilized part metals carrier, by part metals carrier as a part for barrier enclosure structure,
Packaging cost is greatly saved.
In another embodiment, the present embodiment refers to how to obtain at least one through-hole on metal cover 1021
1023 realization method.On the basis of the above embodiments, the method further includes：Trepanning is carried out on the metal cover 1021
Processing, obtains at least one through-hole 1023.
Specifically, when making metal cover 1021, drills on metal cover 1021, obtains at least one through-hole 1023,
The structure E of formation specifically may refer to shown in Fig. 2.Optionally, it can also drill on the side wall 1016 for surrounding groove structure, institute
Obtained through-hole 1023 can be used for chip 1018 and receive the signals such as extraneous sound or air.
By taking microphone as an example, the through-hole 1023 to be drilled on metal cover 1021 enables to chip 1018 to receive
Extraneous sound, to convenient for the voice signal of reception progress signal processing.
The barrier enclosure production method of chip provided in this embodiment is had by drilling on metal cover
The metal cover of through-hole can make chip receive the signals such as extraneous sound or air, to facilitate chip to received signal
It is handled so that obtained barrier enclosure structure can be applicable to receive the chip of outer signals, improve shielding envelope
The scope of application of assembling structure.
Fig. 3 is the flow diagram of the barrier enclosure production method for the chip that another embodiment of the present invention provides.This reality
It applies example to refer to original metal carrier 1024 using coating, exposure and electroplating technology, the shape on original metal carrier 1024
At the process of metal lead wire frame 1017.On the basis of the above embodiments, i.e., further include before above-mentioned S101：
S301 is respectively coated copper film layer in the upper and lower surface of SPCC substrates or stainless steel substrate, obtains original metal
Carrier 1024.
Specifically, in order to obtain the structure of metallic carrier 1012, the present embodiment is first generally using cold rolled carbon steel sheet and steel
Band (Steel-Plate-Cold-Common, abbreviation SPCC) substrate or stainless steel substrate (i.e. 1011 in Fig. 3 a) it is upper and lower
Copper film layer is respectively coated in surface, obtains original metal carrier 1024, the structure of original metal carrier 1024 is referring to Fig. 3 a.It is optional
, other metal materials can also be coated in the upper and lower surface of SPCC substrates or stainless steel substrate.Optionally, SPCC substrates or
Person's stainless steel substrate is cuboid, in order to be subsequently processed to original metal carrier 1024.
S302 forms metal lead wire frame using coating, exposure and electroplating technology on the original metal carrier 1024
1017, and the metallic carrier 1012 is obtained, the structure of metallic carrier 1012 is as shown in Figure 1a；Wherein, the die-attach area
Frame 1017 includes：It is electrically connected the first lead frame 1025 of the chip 1018 and is electrically connected the second of the printed circuit board and draw
Wire frame 1026.
Specifically, the upper surface of the original metal carrier 1024 obtained in S301 coats a layer photoresist, in coating light
First light shield for embodying the circuit pattern welded with chip 1018 is placed on the surface of photoresist, then utilizes illumination to applying
The upper surface for covering the original metal carrier 1024 after photoresist is exposed, and the part blocked by the first light shield will not be by illumination
It arrives, other photoresists shone by illumination can be corroded, and first time plating metal substance is carried out in the gap being corroded, is obtained
To the first lead frame 1025.Again two are carried out on the first lead frame 1025 with same coating, exposure and electroplating technology
Secondary plating obtains the second lead frame 1026, and being formed by structure F specifically can be as shown in Figure 3b.Optionally, secondary electricity is carried out
When plating light shield and difference when being electroplated for the first time, carry out second when being electroplated light shield be to embody and printing electricity
Second light shield of the circuit pattern of road plate welding.Optionally, the first lead frame 1025 is electrically connected with chip 1018, the second lead
Frame 1026 is electrically connected with printed circuit board.
Optionally, chip 1018 includes application-specific integrated circuit (Application Specific Integrated
Circuit, abbreviation ASIC) chip 1027 and MEMS chip 1028.Optionally, asic chip 1027 passes through with MEMS chip 1028
Routing 1019 is electrically connected.Optionally, asic chip 1027 is for handling signal, and MEMS chip 1028 is for acquiring signal.
The barrier enclosure production method of chip provided in this embodiment, it is enterprising in the original metal carrier of coating copper film layer
Row coating twice, exposure and electroplating technology, you can obtain the first lead frame and electrical connection printed circuit board of electrical connection chip
The second lead frame, manufacture craft is simple.
Fig. 4 is the flow diagram of the barrier enclosure production method for the chip that another embodiment of the present invention provides.This reality
It applies example refers to how to handle original metal carrier 1024 using coating, exposure and electroplating technology, obtains metal load
First lead frame 1025 of body 1011 and the optional realization process of one kind of the second lead frame 1026.In above-described embodiment
On the basis of, i.e., above-mentioned S302 may include：
S401 deposits the first photoresist layer on the first metal film layer 1014 of 1024 upper surface of original metal carrier
1029, and first photoresist layer 1029 is exposed, the first figure layer is formed, has multiple first in first figure layer
Opening area 1030, first metal film layer 1014 are in naked state by first opening area 1030.
Specifically, in the upper surface of original metal carrier 1024, a layer photoresist is deposited, forms the first photoresist layer
1029, structure H such as Fig. 4 a of formation.An embodiment is placed on the surface of the first photoresist layer 1029 to be welded with chip 1018
Circuit pattern the first light shield, then using illumination to coating photoresist after original metal carrier 1024 upper surface carry out
Exposure, can be corroded by the photoresist that the first light shield blocks, and expose the first metal film layer 1014, form multiple first and open
Bore region 1030, the first photoresist layer 1029 that some residual that is blocked is not corroded and the first opening area 1030 form the
One figure layer is formed by structure I and may refer to Fig. 4 b.Optionally, illumination can be ultraviolet light.
S402 is electroplated the first metal film layer 1014 at multiple first opening areas 1030, obtains institute
State the first lead frame 1025.
Specifically, carrying out plating metal material on the first metal film layer 1014 at opening area in the first figure layer
Material, to obtain the first lead frame 1025 on the basis of Fig. 4 a, being formed by structure J specifically can be as illustrated in fig. 4 c.It can
Choosing, the metal material of plating can be copper.Optionally, the first lead frame 1025 is electrically connected with chip 1018.It can
Choosing, the shape of the first lead frame 1025 can be designed according to specific required circuit pattern, and the present embodiment pair first draws
The shape of wire frame 1025 does not limit.
S403, deposits the second photoresist layer 1032 on being formed by structure, and to second photoresist layer 1032 into
Row exposure forms the second figure layer, has multiple second opening areas 1031, first lead frame in second figure layer
1025 by second opening area 1031 be in naked state.
Specifically, the surface for being formed by structure in above-mentioned Fig. 4 c deposits a layer photoresist again, the second photoresist is formed
Layer 1032, structure K such as Fig. 4 d of formation.The circuit diagram for being printed with welding circuit board is placed on the surface of the second photoresist layer 1032
Second light shield of case, is exposed it, can be corroded by the photoresist that the second light shield blocks, and forms the second opening area
1031, expose the first lead frame 1025.Second opening area 1031 and remaining photoresist form the second figure layer, are formed by
Structure L may refer to Fig. 4 e.
S404 is electroplated the first lead frame 1025 at multiple second opening areas 1031, obtains second
Lead frame 1026.
Specifically, carrying out electroplating metal material on the second opening area 1031 that S403 is formed, the second lead frame is obtained
The structure M of frame 1026, formation may refer to shown in Fig. 4 f.Optionally, the second lead frame 1026 is electrically connected with printed circuit board.
Optionally, the metal of plating is copper.Optionally, the shape of the second lead frame 1026 can according to circuit pattern needed for specific into
Row design, the shape of the second lead frame of the present embodiment pair 1026 do not limit.
S405 removes remaining first photoresist layer, 1029 and second photoresist layer 1032, obtains the metallic carrier
1012 the first lead frame 1025 and the second lead frame 1026.
Specifically, the first photoresist layer 1029 and the second photoresist layer 1032 that 1012 upper surface of metallic carrier is blocked
It removes, leaves the first lead frame 1025 and the second lead frame 1026 on 1012 upper surface of metallic carrier, be formed by structure N
It may refer to Fig. 4 g.
The barrier enclosure production method of chip provided in this embodiment, on the metallic carrier for coating the first metal film layer
Carry out coating twice, exposure and electroplating technology, you can obtain the first lead frame being electrically connected with chip and and printed circuit board
Second lead frame of electrical connection, manufacture craft are simple.
In the barrier enclosure production method for the chip that another embodiment provides, the present embodiment refers to carry metal
The gap structure of lead frame on body 1012 carries out plastic packaging, obtains the after the first lead frame 1025 and plastic packaging after plastic packaging
The realization process of two lead frames 1026.On the basis of the above embodiments, the method further includes：It is filled out using plastic packaging material 1033
The gap structure in the lead frame of the metallic carrier 1012 is filled, after obtaining the first lead frame 1025 and plastic packaging after plastic packaging
The second lead frame 1026.
Specifically, at the gap structure for removing the first photoresist layer 1029 and the second photoresist layer 1032, plastic packaging is filled
Material 1033, obtains the second lead frame 1026 after the first lead frame 1025 and plastic packaging after plastic packaging, being formed by structure P can
With as shown in Figure 5.Optionally, capsulation material can select green resin or ordinary resin.
The barrier enclosure production method of chip provided in this embodiment, using plastic packaging material fill removal the first photoresist layer and
The gap structure of second photoresist layer, you can obtain plastic packaging material package metal lead wire frame, manufacture craft is simple, and with mould
The metal lead wire frame of envelope material package can play a supporting role to chip.In addition, plastic packaging material price is relatively low, envelope is greatly reduced
Dress up this.
In another embodiment, the present embodiment refers to be ground at polishing the metallic carrier 1012 after plastic packaging
Reason and the process that trepanning processing is carried out to metal cover 1021.On the basis of above-described embodiment, the method further includes：To plastic packaging
The surface of metallic carrier 1012 afterwards is ground polishing treatment；And/or the surface of the metallic carrier 1012 after plastic packaging is carried out
Trepanning is handled, and obtains at least one through-hole 1023.
Specifically, when carrying out the filling of plastic packaging material 1033, the copper that the second lead frame of part 1026 exposes may be by plastic packaging material
1033 block, and the surface of the metallic carrier 1012 after plastic packaging, which is ground polishing treatment, will be blocked part polishing totally, directly
To the second lead frame 1026 of exposing.
Optionally, trepanning processing is carried out to the surface of the metallic carrier 1012 after plastic packaging, obtains at least one through-hole 1023.
Obtained through-hole 1023 can be used in chip 1018 and receive extraneous voice signal or optical signal etc., so that obtained barrier enclosure
Structure can be applied to the chip 1018 for needing to receive outer signals, improve the accommodation of barrier enclosure structure.
The barrier enclosure production method of chip provided in this embodiment is had by drilling on metal cover
The metal cover of through-hole can make chip receive the signals such as extraneous sound or air, to facilitate chip to received signal
It is handled so that obtained barrier enclosure structure can be applicable to receive the chip of outer signals, improve shielding envelope
The scope of application of assembling structure.
The present invention also provides a kind of barrier enclosure structure, Fig. 6 is barrier enclosure structure provided by one embodiment of the present invention
Sectional view, as shown in fig. 6, including：Bottom has the metallic carrier that groove structure and upper and lower surface all have metal film layer
1012, chip 1018 and metal cover 1021, the metal lead wire frame 1017 that the chip 1018 passes through the metallic carrier 1012
It is electrically connected in the groove structure；The metal cover 1021 is fixed on the metal film layer at the top of the groove structure, with
The groove structure forms barrier enclosure structure.
The method and step that above method embodiment may be used in barrier enclosure structure in the present embodiment is made, technology effect
Fruit is similar with above method embodiment, and details are not described herein.
Fig. 7 is the barrier enclosure structure sectional view that another embodiment of the present invention provides.The basis of embodiment shown in Fig. 6
On, the chip includes application-specific integrated circuit ASIC chip 1027 and MEMS chip 1028, is provided on the metal cover 1021
At least one through-hole 1023.Optionally, asic chip 1027 and MEMS chip 1028 are electrically connected by routing 1019.
The method and step that above method embodiment may be used in barrier enclosure structure in the present embodiment is made, technology effect
Fruit is similar with above method embodiment, and details are not described herein.
Fig. 8 is the barrier enclosure structure sectional view that another embodiment of the present invention provides.The basis of embodiment shown in Fig. 7
On, metal lead wire frame 1017 is embedded in plastic packaging material 1033, to form the support construction for supporting the chip, and the metal
The both ends of lead frame 1017 are in naked state, for connecting the chip 1018 and printed circuit board.
The method and step that above method embodiment may be used in barrier enclosure structure in the present embodiment is made, technology effect
Fruit is similar with above method embodiment, and details are not described herein.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (11)
1. a kind of barrier enclosure production method of chip, which is characterized in that including：
The lower surface of metallic carrier is etched, groove structure is formed in the metallic carrier bottom；Wherein, the metal carries
Metal lead wire frame on body is located in the groove structure, and the upper and lower surface of the metallic carrier all has metal film layer；
On being formed by structure, using attachment process by the chip attachment in the groove structure, and by the gold
Belong to the surface that carrier is mounted on printed circuit board；
Using attachment process, metal cover is mounted on the metal film layer at the top of the groove structure so that the metal cover
Barrier enclosure structure is formed with the groove structure.
2. according to the method described in claim 1, it is characterized in that, the lower surface to metallic carrier is etched, in institute
It states metallic carrier bottom and forms groove structure, including：
Using photochemical etching process, the lower surface of the metallic carrier is etched, until the metal lead wire frame is in
Naked state, to form groove structure in the metallic carrier bottom.
3. according to the method described in claim 2, it is characterized in that, the method further includes：
Tapping reason is carried out on the metal cover, obtains at least one through-hole.
4. according to the method described in claim 2, it is characterized in that, the lower surface to metallic carrier is etched, in institute
It states metallic carrier bottom to be formed before groove structure, further includes：
Copper film layer is respectively coated in the upper and lower surface of SPCC substrates or stainless steel substrate, obtains original metal carrier；
Using coating, exposure and electroplating technology, metal lead wire frame is formed on the original metal carrier, and obtain the gold
Belong to carrier；Wherein, the metal lead wire frame includes：It is electrically connected the first lead frame of the chip and is electrically connected the printing
Second lead frame of circuit board.
5. according to the method described in claim 4, it is characterized in that, described use coating, exposure and electroplating technology, described first
Metal lead wire frame is formed on beginning metallic carrier, and obtains the metallic carrier, including：
The first photoresist layer is deposited on the first metal film layer of original metal carrier upper surface, and to first light
Photoresist layer is exposed, and forms the first figure layer, has multiple first opening areas, first metal foil in first figure layer
Film layer is in naked state by first opening area；
The first metal film layer at multiple first opening areas is electroplated, first lead frame is obtained；
The second photoresist layer is deposited on being formed by structure, and second photoresist layer is exposed, and forms the second figure
Layer, it is in by second opening area with multiple second opening areas, first lead frame in second figure layer
Naked state；
The first lead frame at multiple second opening areas is electroplated, the second lead frame is obtained；
Remaining first photoresist layer and the second photoresist layer are removed, the first lead frame and second of the metallic carrier is obtained
Lead frame.
6. according to the method described in claim 5, it is characterized in that, the method further includes：
The gap structure in the lead frame of the metallic carrier is filled using plastic packaging material, obtains the first lead frame after plastic packaging
With the second lead frame after plastic packaging.
7. according to the method described in claim 6, it is characterized in that, the method further includes：
Polishing treatment is ground to the surface of the metallic carrier after plastic packaging；
And/or
Trepanning processing is carried out to the surface of the metallic carrier after plastic packaging, obtains at least one through-hole.
8. according to claim 1-7 any one of them methods, which is characterized in that the chip includes application-specific integrated circuit ASIC
Chip and MEMS chip.
9. a kind of chip barrier enclosure structure, which is characterized in that including：Bottom has groove structure and upper and lower surface all has gold
Belong to metallic carrier, chip and the metal cover of film layer, the chip is electrically connected by the metal lead wire frame of the metallic carrier
In in the groove structure；
The metal cover is fixed on the metal film layer at the top of the groove structure, and barrier enclosure is formed with the groove structure
Structure.
10. barrier enclosure structure according to claim 9, which is characterized in that the chip includes application-specific integrated circuit
Asic chip and MEMS chip are provided at least one through-hole on the metal cover.
11. barrier enclosure structure according to claim 10, which is characterized in that metal lead wire frame is embedded in plastic packaging material
Interior, to form the support construction for supporting the chip, and the both ends of the metal lead wire frame are in naked state, for connecting
The chip and printed circuit board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810385620.XA CN108493167A (en) | 2018-04-26 | 2018-04-26 | The barrier enclosure production method and barrier enclosure structure of chip |
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| CN201810385620.XA CN108493167A (en) | 2018-04-26 | 2018-04-26 | The barrier enclosure production method and barrier enclosure structure of chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040179344A1 (en) * | 2002-11-18 | 2004-09-16 | Nec Compound Semiconductor Devices, Ltd. | Electronic device capable of preventing electromagnetic wave from being radiated |
| CN102097415A (en) * | 2009-12-10 | 2011-06-15 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacture method thereof |
| CN104009006A (en) * | 2013-02-27 | 2014-08-27 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same |
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2018
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040179344A1 (en) * | 2002-11-18 | 2004-09-16 | Nec Compound Semiconductor Devices, Ltd. | Electronic device capable of preventing electromagnetic wave from being radiated |
| CN102097415A (en) * | 2009-12-10 | 2011-06-15 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacture method thereof |
| CN104009006A (en) * | 2013-02-27 | 2014-08-27 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same |
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Application publication date: 20180904 |