CN108493151A - 跳通孔结构 - Google Patents

跳通孔结构 Download PDF

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CN108493151A
CN108493151A CN201810132709.5A CN201810132709A CN108493151A CN 108493151 A CN108493151 A CN 108493151A CN 201810132709 A CN201810132709 A CN 201810132709A CN 108493151 A CN108493151 A CN 108493151A
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hole
wiring layer
layer
jump
distribution
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CN108493151B (zh
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张洵渊
林萱
J·J·麦克马洪
S·B·劳
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GlobalFoundries US Inc
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Abstract

本揭示内容涉及跳通孔结构，其关于半导体结构，且更特别的是，关于跳通孔结构及其制法。该结构包括：第一配线层，具有一或更多配线结构；上层配线层，具有一或更多配线结构，其位于该第一配线层上方；阻挡材料，接触该上层配线层的该配线结构中的至少一者；跳通孔，具有金属化物，该跳通孔穿过该上层配线层且与该第一配线层的该一或更多配线结构接触；以及导电材料，在该金属化物上方的该跳通孔中以及在该阻挡材料上方的通孔互连中。

Description

跳通孔结构
技术领域
本揭示内容是关于半导体结构，且更特别的是，关于跳通孔结构及其制法。
背景技术
在通孔技术中，可形成穿过许多绝缘体层的跳通孔，例如，跳过在绝缘体层内的一或更多配线结构，以与下层配线结构连接。这提供改良的电阻特性，最小化下层配线结构(例如，在M0层)的电容，以及提供芯片工艺的面积效率。
使用跳通孔有许多挑战。例如，在工艺中，跳通孔需要落在在下阶层(例如，M0阶层)中的配线结构上，同时正规通孔需要落在上阶层(例如，M1或以上的阶层)中的配线结构上。然而，由于跳通孔蚀刻工艺，在上阶层中的配线结构与通孔互连结构的接口处会导致损伤。亦即，由于蚀刻深度不同，跳通孔蚀刻工艺会导致上层配线结构(例如，铜材料)表面损伤。此损伤造成较高的电阻率，接着是，减低装置效能。
再者，在跳通孔工艺中，习知镀铜工艺用来填充通孔。然而，镀铜工艺在各个方向成长，包括通孔的侧壁及底部，导致产生大量空洞，因为具有源于侧壁成长的夹止(pinch-off)以及源于不充分物理气相沉积(PVD)种子覆盖于高纵横比通孔上的底部空洞。空洞也可起因于由超低k(ULK)电浆诱发损伤(PID)或帽盖对于层间电介质的选择性形成的底切轮廓(undercut profile)。再者，衬里/种子不足以覆盖高纵横比通孔的全长，也导致空洞形成。这些空洞对于跳通孔的电阻率有负面影响，接着是，减少装置效能。
发明内容
在本揭示内容的一态样中，一种结构，其包含：第一配线层，具有一或更多配线结构；上层配线层，具有一或更多配线结构，其位于该第一配线层上方；阻挡材料，其接触该上层配线层的该配线结构中的至少一者；跳通孔，具有金属化物，该跳通孔穿过该上层配线层且与该第一配线层的该一或更多配线结构接触；以及导电材料，其在该金属化物上方的该跳通孔中以及在该阻挡材料上方的通孔互连中。
在本揭示内容的一态样中，一种方法，其包含：形成通孔以暴露上层配线层的一或更多配线结构；形成跳通孔，其穿过该上层配线层且暴露下层配线层的一或更多配线结构；在该通孔中形成覆盖该上层配线层的该暴露一或更多配线结构的阻挡材料；选择性成长金属材料于该跳通孔中；以及用导电材料填充该跳通孔及该通孔的其余部分。
在本揭示内容的一态样中，一种方法，其包含：形成具有一或更多配线结构的配线层于下层配线层中；形成具有一或更多配线结构的配线层于位于该下层配线层上方的上层配线层中；形成暴露该上层配线层的该一或更多配线结构的第一通孔与穿过该上层配线层且在该下层配线层上方结束的第二通孔；在该第一通孔中形成阻挡材料以阻挡该上层配线层的该暴露一或更多配线结构；延伸落在该下层配线层上的该第二通孔以形成暴露该下层配线层的该一或更多配线结构的跳通孔，同时该阻挡材料保护该上层配线层的该暴露一或更多配线结构；用导电材料填充至少该跳通孔以接触该下层配线层的该一或更多配线结构且与该上层配线层的该一或更多配线结构电气连接；以及用不同导电材料填充该跳通孔及该第一通孔的其余部分。
附图说明
以下说明详述本揭示内容，其中参考多个附图以不具限定性的方式举例说明本揭示内容的示范具体实施例。
图1根据本揭示内容的数个态样图标结构及各个工艺。
图2根据本揭示内容的数个态样图示形成于通孔开口(但不限于此)中的阻挡材料及各个工艺。
图3根据本揭示内容的数个态样图标跳通孔结构(但不限于此)及各个工艺。
图4根据本揭示内容的数个态样图标在跳通孔结构及正规通孔结构(但不限于此)中的金属化物特征及各个工艺。
图5图示根据本揭示内容的其他态样的替代结构及各个工艺。
具体实施方式
本揭示内容是有关于半导体结构，且更特别的是，有关于跳通孔结构及制法。更特别的是，本揭示内容提供工艺及所得的跳通孔结构，其解决上阶层通孔形成的通孔蚀刻时间不相等问题，例如，上层配线层在跳通孔蚀刻工艺期间出现损伤。相应及有利地，工艺及所得的跳通孔结构不会因为通孔蚀刻深度的任何差异而造成上层配线结构损伤。换言之，本文所提供的方法不会造成在上配线阶层(例如，M1阶层)的铜或其他金属化物材料在跳通孔形成期间过度蚀刻。
在附加具体实施例中，本揭示内容描述一种选择性无电(钴或镍)工艺，其在跳通孔结构中从下到上地成长金属。利用选择性无电金属(例如，钴或镍)成长工艺，钴或镍不会形成于跳通孔的侧壁上，接着是，确保这是无空洞填充，不论跳通孔的轮廓及纵横比如何。以此方式，有利的是，可防止由源于侧壁成长的夹止以及源于不充分物理气相沉积(PVD)种子覆盖于高纵横比通孔上的底部空洞所引起的大量空洞，接着，会减低跳通孔的电阻率从而提高装置效能。
在附加具体实施例中，描述于本文的工艺提供一种在跳通孔蚀刻工艺期间在上层配线结构(例如，M1阶层)的暴露表面上面的阻挡材料。在数个具体实施例中，该阻挡材料可保护上层配线结构的暴露表面以及防止钴在通孔及上层配线层中过度成长。亦即，该阻挡材料会用作屏蔽以在跳通孔蚀刻工艺期间保护上层配线结构。该阻挡材料也会用来防止钴材料在正规通孔互连及配线结构内过度成长。再者，有利的是，描述于本文的金属互连结构对于用于7纳米以下的装置的后段(BEOL)及中段(MOL)互连结构有冲击，在此习知铜金属化物可能无法延伸。
可使用许多不同工具以许多方法来制造本揭示内容的跳通孔结构。然而，通常该方法及工具是用来形成具有微米及纳米级尺寸的结构。用来制造本揭示内容的跳通孔结构的该方法，亦即，技术，是选自集成电路(IC)技术。例如，该结构建立于晶片上以及实现于在晶片上面用光刻工艺(photolithographic process)图案化的材料膜中。特别是，该跳通孔结构的制造使用以下3个基本建造区块：(i)沉积数个材料薄膜于衬底上，(ii)用光刻成像法铺设图案化屏蔽于薄膜上面，以及(i ii)对于该屏蔽选择性地蚀刻薄膜。
图1根据本揭示内容的数个态样图标结构及各个工艺。在数个具体实施例中，图1中图标的结构10例如可为BEOL或MOL结构。特别是，结构10包括在晶粒中的多个配线阶层，例如M0、M1等等。例如，结构10包括设于绝缘体材料12中的配线结构14。本领域技术人员应了解，绝缘体材料12中的配线结构14是代表性地指定在M0阶层的下层配线结构；然而配线结构14可设在结构的任何下阶层。
配线结构14可由任何导电材料构成，例如铜、钴、钌、钨、铝等等，其衬有氮化钛(TiN)、氮化钽(TaN)、钛、钽、钌、钴等等。在数个具体实施例中，绝缘体材料14为可用例如化学气相沉积(CVD)的习知沉积方法沉积的氧化物，例如层间介电材料。绝缘体材料14也可为超低k介电材料、掺碳绝缘体材料或有多孔性的其他绝缘体材料。
配线结构14可用本领域技术人员所习知的习知光刻、蚀刻及沉积方法形成。例如，形成于绝缘体材料12上面的抗蚀剂暴露于能量(光线)以形成图案(开口)。用选择性化学物的蚀刻工艺，例如，反应性离子蚀刻(RIE)，会通过抗蚀剂的开口用来在绝缘体材料12中形成一或更多沟槽。然后，抗蚀剂可用习知氧气灰化法(oxygen ashing process)或其他习知去膜剂(stripant)移除。在移除抗蚀剂后，可用任何习知沉积工艺(例如，化学气相沉积(CVD)工艺)沉积导电材料于一或更多沟槽中。绝缘体材料12表面上的任何残余材料14可用习知化学机械研磨(CMP)工艺移除。
在CMP工艺后，形成覆盖层16于配线结构14及绝缘体材料12上。在数个具体实施例中，覆盖层16可为扩散阻障层，例如，铜扩散阻障层，其防止铜或其他金属化物扩散到上层绝缘体层18。覆盖层16也可防止氧扩散到配线结构14。
仍参考图1，配线结构20及通孔互连结构22皆形成于上层绝缘体层18中。在数个具体实施例中，配线结构20及互连结构22可形成于在配线结构14上方的任何配线层中。例如，在绝缘体材料18中的配线结构20标示为在M1、M2等阶层的上层配线结构；然而，互连结构22各自标示为V0、V1等等。配线结构20及互连结构22可用习知光刻、蚀刻及沉积工艺形成，这与在说明下层配线结构14的形成时所述的类似。配线结构20及通孔互连结构22可由任何导电材料构成，例如铜、钴、钌、钨、铝等等，其衬有氮化钛、氮化钽、钛、钽、钌、钴等等。
在移除绝缘体材料18表面的任何残余材料的CMP工艺后，形成覆盖层24于配线结构20及绝缘体材料18上。在数个具体实施例中，覆盖层24可为扩散阻障层，例如铜扩散阻障层，如上述。
例如，形成屏蔽材料28于绝缘体材料26的表面上，在M1阶层上的选定配线结构20的边缘与M0阶层上的配线结构14之间。屏蔽材料28可为用例如RIE的习知沉积及蚀刻工艺进行沉积及图案化的氮化钛。形成抗蚀剂30于屏蔽材料28及绝缘体材料26上，其暴露于能量(光线)以形成各自与在M0、M1阶层的一或更多配线结构14、22对齐的图案(开口)。用选择性化学物的蚀刻工艺，例如RIE，会通过抗蚀剂30的开口用来形成绝缘体材料26及覆盖层24中的一或更多通孔32a、32b。该蚀刻工艺经计时以在在上层配线结构20的表面被通孔32b暴露时的深度停止。以此方式，通孔32b的深度落在位于M1阶层上的配线结构20的表面上并暴露出该表面。
在图2中，直接在上层配线结构20表面上面及/或之上形成阻挡材料34于通孔32b中。在数个具体实施例中，阻挡材料34可为选择性成长于配线结构20的暴露表面上的锰。在数个具体实施例中，该锰用化学气相沉积(CVD)或原子层沉积(ALD)工艺选择性成长于铜表面上，例如，铜配线结构。阻挡材料34的深度最好为3纳米或更小，例如。在替代具体实施例中，阻挡材料34可为各自用SiH4或GeH4处理配线结构的铜表面而形成的铜硅(CuSi)或铜锗(CuGe)。
在图3中，跳通孔蚀刻工艺继续穿过上阶层(例如，M1阶层)到在结构的下阶层(例如，M0阶层)的配线结构14。在数个具体实施例中，跳通孔蚀刻延伸(加深)通孔32a'，其落在位于下阶层上的配线结构14上且暴露它。在此跳通孔蚀刻工艺期间，阻挡材料34会保护(屏蔽)位于上层上的配线结构20(在配线结构14上方)的表面以免被使用于跳通孔蚀刻工艺的蚀刻化学物损伤。
然后，抗蚀剂30可用习知氧气灰化法或其他习知去膜剂移除，接着是进行沟槽RIE以形成(上阶层，例如阶层M2的)沟槽36，然后用湿工艺移除屏蔽材料28。阻挡材料34也会在移除屏蔽材料期间保护位于M1阶层上的配线结构20的表面。
如图4所示，通孔32a'及32b和沟槽36用导电材料38填充以形成双层镶嵌结构(dual damascene structure)，例如，互连结构与上层配线结构。本领域技术人员应了解，形成于通孔32a'中的互连结构会是电气及直接连接至位于M0阶层上的配线结构14的跳通孔结构，例如，其跳过在M1或以上的阶层中的任何连接。另一方面，在通孔32b中的导电材料38会是正规通孔互连结构，其提供与位于下阶层上的配线结构20的电气及直接连接。
在更特定的具体实施例中，跳通孔32a'是用钴(Co)38部分填充；然而，在数个具体实施例中，阻挡材料34可实质防止钴在互连通孔32b中成长。在数个具体实施例中，钴(Co)38用选择性无电成长工艺在通孔32a'中以由下往上的方式形成于M0、M1阶层上。具体而言，在数个具体实施例中，钴(Co)38会选择性成长于下层配线层的一或更多配线结构14的暴露金属表面上，同时不成长于通孔32a'、32b的绝缘体侧壁上或于通孔32b中的阻挡材料34上，例如，钴(Co)38不会成长于形成通孔的侧壁的绝缘体材料上。
以此方式，钴(Co)38成长工艺会以由下往上的方式完全填充跳通孔32a'的下半部，防止在通孔32a内形成任何空洞。换言之，该选择性成长工艺会保证跳通孔32a的无空洞填充，不论它的轮廓及纵横比、种子覆盖(seed coverage)、配线结构14上的超低k(ULK)电浆诱发损伤(PID)或者是帽盖对于层间电介质的选择性如何。接着，互连结构的这种无空洞形成会增加跳通孔32a'的电阻率。本领域技术人员也应了解，钴(Co)的无电成长工艺相容于介电材料，因而排除阻障层的需要。
更如图4所示，跳通孔32a'、正规通孔32b及沟槽36(用于上层配线结构)的其余部分用导电材料40填充以形成双层镶嵌结构，例如互连结构与上层配线结构。在数个具体实施例中，导电材料40可为例如铜、铝、钨等等几个想到的材料。导电材料40可用习知沉积方法沉积，例如，电镀、无电沉积、CVD及/或电浆气相沉积(PVD)及/或原子层沉积(ALD)，接着是习知平坦化工艺，例如，CMP，以移除绝缘体层26上的任何残余材料。然后，可形成覆盖层42于绝缘体层26及导电材料40上面，接着进行习知BEOL工艺(例如，焊接结构)。
图5根据本揭示内容的数个替代态样图标替代结构及各个工艺。在此替代具体实施例中，在钴(Co)38成长于通孔32b内的任何情形下，用钴材料38部分填充通孔32b，沟槽32b中的阻挡材料34会抑制钴(Co)38在通孔32b中过度成长，例如，长到高过通孔32b的高度。亦即，钴成长率应较小于在通孔32a中的情形，而甚至此一较小的钴成长率可用来填充通孔32b。因此，在此具体实施例中，通孔32b中的阻挡材料34会大幅减缓钴材料38的成长工艺，同时与位于M1阶层上的配线结构20及通孔32b中的钴38直接电气连接。例如，钴(Co)材料38在通孔32a'、32b中的成长率在各个表面上可为大约2：1，例如，配线结构14被通孔32a'及通孔32b中的阻挡材料34暴露的铜表面。接着，钴(Co)材料38会与其余导电材料40直接电气接触。
上述该(等)方法是使用于集成电路芯片的制造。所得集成电路芯片可由制造者以原始晶片形式(raw wafer form)(也就是具有多个未封装芯片的单一晶片)、作为裸晶粒(bare die)或已封装的形式来销售。在后一情形下，芯片装在单芯片封装体中(例如，塑料载体(plastic carrier)，具有固定至主板或其他更高层载体的引脚(lead))，或多芯片封装体中(例如，具有表面互连件(surface interconnection)或内嵌互连件(buriedinterconnection)任一或两者兼具的陶瓷载体)。然后，在任一情形下，芯片与其他芯片、离散电路组件及/或其他信号处理装置整合成为下列任一者的一部分：(a)中间产品(例如，主板)，或(b)最终产品。该最终产品可为包括集成电路芯片的任何产品，从玩具及其他低端应用到有显示器、键盘或其他输入设备及中央处理器的先进计算机产品不等。
为了图解说明，已呈现本揭示内容的各种具体实施例的描述，但是并非旨在穷尽或限定于所揭示的具体实施例。本领域一般技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市上可找到的技术的技术改善，或使得本领域一般技术人员能够了解揭示于本文的具体实施例。

Claims (20)

1.一种结构，包含：
第一配线层，具有一或更多配线结构；
上层配线层，具有一或更多配线结构，该上层配线层位于该第一配线层上方；
阻挡材料，接触该上层配线层的该配线结构中的至少一者；
跳通孔，具有金属化物，该跳通孔穿过该上层配线层且与该第一配线层的该一或更多配线结构接触；以及
导电材料，在该金属化物上方的该跳通孔中以及在该阻挡材料上方的通孔互连中。
2.如权利要求1所述的结构，其中，该导电材料为该跳通孔与在该跳通孔上方的配线结构的一部分。
3.如权利要求2所述的结构，其中，该金属化物为选择性成长于通孔开口中的钴或镍，该通孔开口穿过该上层配线层且暴露该第一配线层的该一或更多配线结构。
4.如权利要求3所述的结构，其中，该钴或镍部分填充该通孔开口。
5.如权利要求4所述的结构，其中，该跳通孔没有空洞。
6.如权利要求4所述的结构，其中，该钴或镍部分填充在该阻挡材料上方的通孔。
7.如权利要求6所述的结构，其中，该导电材料填充在该通孔及该上层配线层上方的配线沟槽，以及该导电材料形成配线结构。
8.如权利要求1所述的结构，其中，该阻挡材料为锰。
9.如权利要求1所述的结构，其中，该阻挡材料为铜硅或铜锗，其通过各自用SiH4或GeH4处理该上层配线层的该配线结构的铜表面而形成。
10.一种方法，包含：
形成通孔以暴露上层配线层的一或更多配线结构；
形成跳通孔，其穿过该上层配线层且暴露下层配线层的一或更多配线结构；
在该通孔中形成覆盖该上层配线层的该暴露一或更多配线结构的阻挡材料；
选择性成长金属材料于该跳通孔中；以及
用导电材料填充该跳通孔及该通孔的其余部分。
11.如权利要求10所述的方法，其中，该金属材料的选择性成长包含选择性成长钴于该跳通孔中以部分填充该跳通孔。
12.如权利要求11所述的方法，其中，该钴或镍的该选择性成长为无电成长工艺。
13.如权利要求12所述的方法，其中，该无电成长工艺是在该跳通孔内从该下层配线层的该一或更多配线结构的暴露部分开始从下往上。
14.如权利要求10所述的方法，其中，该导电材料为铜。
15.如权利要求10所述的方法，其中，该钴或镍的成长部分填充该通孔，以及该方法更包含用该导电材料填充该通孔的其余部分及在该上层配线层上方的配线沟槽。
16.如权利要求10所述的方法，其中，通过沉积锰来形成该阻挡材料。
17.如权利要求10所述的结构，其中，该阻挡材料为铜硅或铜锗，其通过各自用SiH4或GeH4处理该上层配线层的该配线结构的表面而形成。
18.一种方法，包含：
形成具有一或更多配线结构的配线层于下层配线层中；
形成具有一或更多配线结构的配线层于位于该下层配线层上方的上层配线层中；
形成暴露该上层配线层的该一或更多配线结构的第一通孔与穿过该上层配线层且在该下层配线层上方结束的第二通孔；
在该第一通孔中形成阻挡材料以阻挡该上层配线层的该暴露一或更多配线结构；
延伸落在该下层配线层上的该第二通孔以形成暴露该下层配线层的该一或更多配线结构的跳通孔，同时该阻挡材料保护该上层配线层的该暴露一或更多配线结构；
用导电材料填充至少该跳通孔以接触该下层配线层的该一或更多配线结构且与该上层配线层的该一或更多配线结构电气连接；以及
用不同导电材料填充该跳通孔及该第一通孔的其余部分。
19.如权利要求18所述的方法，其中，该阻挡材料为锰、铜硅或铜锗。
20.如权利要求18所述的方法，其中，用导电材料填充至少该跳通孔为钴或镍的无电成长工艺。
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