CN108490343B

CN108490343B - Drive circuit board test aging device of PCR instrument

Info

Publication number: CN108490343B
Application number: CN201810494429.9A
Authority: CN
Inventors: 胡炎昌; 伊波; 贾伟; 童国军; 石建军; 贺贤汉
Original assignee: Hangzhou Bori Technology Co ltd
Current assignee: Hangzhou Bori Technology Co ltd
Priority date: 2018-05-22
Filing date: 2018-05-22
Publication date: 2023-07-25
Anticipated expiration: 2038-05-22
Also published as: CN108490343A

Abstract

The invention discloses a drive circuit board test aging device of a PCR instrument. The influence of human factors in the testing process of the driving circuit board testing device of the PCR instrument is great. The invention comprises a main board power supply, a control main board and an analog load group; the simulated load group comprises a first simulated load, a second simulated load, a third simulated load, a fourth simulated load, a fifth simulated load and a sixth simulated load; the control main board comprises a power supply conversion circuit, a main control singlechip circuit, a current sampling circuit, an output interface circuit, an auxiliary channel output signal indicating circuit, a storage unit display circuit, a display key interface circuit, a storage unit data processing circuit, a data memory circuit, a feedback signal conversion circuit and a storage unit signal interface circuit; the invention makes the tested PCR drive circuit board finish testing and aging in a strict working environment by powering up and loading.

Description

Drive circuit board test aging device of PCR instrument

Technical Field

The invention belongs to the technical field of test aging of drive boards, and particularly relates to a device for testing aging of a drive circuit board of a PCR instrument.

Background

The aging mode commonly used for the driving circuit board in the PCR field at present is as follows: and after the debugging and testing are finished, performing off-line high-low temperature impact aging on the single board, and then performing test rechecking to select out the unqualified board. The process does not test the components in the board in fatigue period, and can not pick out unstable boards in the operation process, and the operation process is too complicated. The human factor in the debugging and testing process is too large.

Disclosure of Invention

The invention aims to provide a device for testing aging of a drive circuit board of a PCR instrument.

The invention comprises a main board power supply, a control main board and an analog load group; the simulated load group comprises a first simulated load, a second simulated load, a third simulated load, a fourth simulated load, a fifth simulated load and a sixth simulated load; the control main board comprises a power supply conversion circuit, a main control singlechip circuit, a current sampling circuit, an output interface circuit, an auxiliary channel output signal indicating circuit, a storage unit display circuit, a display key interface circuit, a storage unit data processing circuit, a data memory circuit, a feedback signal conversion circuit and a storage unit signal interface circuit; the power supply conversion circuit supplies power to the main control singlechip circuit, the current sampling circuit, the storage unit display circuit, the storage unit data processing circuit, the data memory circuit and the feedback signal conversion circuit through the power supply voltage reduction module, the first voltage stabilizing chip and the second voltage stabilizing chip; the master control singlechip circuit sends a driving signal to the driving signal interface circuit through the first singlechip; the current sampling circuit displays voltage values at two ends of a first analog load and a second analog load respectively through a first digital voltage gauge head and a second digital voltage gauge head; the feedback signal conversion circuit converts the received voltage value into switching value through the photoelectric coupler and transmits the switching value to the storage unit data processing circuit; the memory cell data processing circuit is connected with the memory cell display circuit.

The driving signal interface circuit is a driving signal wiring terminal block; the 1 pin of the drive signal wiring terminal block is connected with the fourth data output end of the main control single-chip microcomputer circuit, the 3 pin is connected with the third data output end of the main control single-chip microcomputer circuit, and the 5 pin is connected with the first data output end of the main control single-chip microcomputer circuit; the 9 pin is connected with the second data output end of the master control singlechip circuit, the 13 pin is connected with the ninth control output end of the master control singlechip circuit, the 15 pin is connected with the eighth control output end of the master control singlechip circuit, the 25 pin is connected with the second control output end of the master control singlechip circuit, the 26 pin is connected with the first control output end of the master control singlechip circuit, the 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 and 29 pins are all connected with the 3.3V output end of the power conversion circuit, the 17 pin is connected with the third control output end of the master control singlechip circuit, the 19 pin is connected with the fourth control output end of the master control singlechip circuit, the 7 pin is connected with the seventh control output end of the master control singlechip circuit, the 27 pin is connected with the sixth control output end of the master control singlechip circuit, the 28 pin is connected with the fifth control output end of the master control singlechip circuit, and the 35 pin is grounded.

The output interface circuit comprises a first transmission wiring terminal block and an output wiring terminal block. The pins 2 and 4 of the first transmission wiring terminal row are respectively connected with the first wiring ends of the first analog load and the second analog load, the pin 9 is connected with the signal interaction end of the main control singlechip circuit, the pin 10 is connected with the positive electrode of the main board power supply, and the pins 17, 18, 19 and 20 are respectively connected with the first wiring end of the third analog load, the first wiring end of the fourth analog load, the first wiring end of the fifth analog load and the first wiring end of the sixth analog load; and the second wiring terminals of the third analog load, the fourth analog load, the fifth analog load and the sixth analog load are connected with the positive electrode of the main board power supply.

Pins 1, 2, 9 and 10 of the output wiring terminal row are connected with a second wiring terminal of a first analog load, pins 3, 4, 11 and 12 are connected with a first wiring terminal of the first analog load, pins 5, 6, 13 and 14 are connected with a second wiring terminal of the second analog load, and pins 7, 8, 15 and 16 are connected with a first wiring terminal of the second analog load.

The display key interface circuit comprises a first communication wiring terminal row. Pins 8, 10, 12, 14 and 16 of the first communication wiring terminal row are respectively connected with one ends of a first key, a second key, a third key, a fourth key and a fifth key; the other ends of the first key, the second key, the third key, the fourth key and the fifth key are all grounded; the pins 11 and 13 of the first communication wiring terminal row are connected with the 5V output end of the power conversion circuit, the pins 7 and 9 are grounded, and the pins 1, 3 and 5 are respectively connected with the first signal input end, the second signal input end and the third signal input end of the memory cell display circuit.

The memory cell signal interface circuit includes a second communication terminal block and a second transmission terminal block. The pins 7 and 9 of the second communication wiring terminal row are grounded, the pins 11 and 13 are connected with the 5V output end of the power conversion circuit, and the pins 1, 3 and 5 are respectively connected with the third display output end, the second display output end and the first display output end of the storage unit data processing circuit; pins 2, 4, 6, 8, 10, 12, 14 and 16 of the second communication terminal block are respectively connected with a ninth signal input end to a sixteenth signal input end of the memory cell data processing circuit.

And the 9 pins of the second transmission wiring terminal block are connected with the signal interaction end of the data processing circuit of the storage unit. The 1 pin and the 3 pin of the second transmission wiring terminal block are respectively connected with two third analog input ends of the feedback signal conversion circuit; the pins 2 and 4 of the second transmission wiring terminal block are respectively connected with two fourth analog input ends of the feedback signal conversion circuit; the 10 pins of the second transmission wiring terminal block are connected with the first analog input end of the feedback signal conversion circuit; pins 17, 18, 19 and 20 of the second transmission wiring terminal row are respectively connected with four second analog input ends of the feedback signal conversion circuit.

The drive signal interface circuit is a drive signal wiring terminal block. The 1 pin of the drive signal wiring terminal block is connected with the fourth data output end of the main control single-chip microcomputer circuit, the 3 pin is connected with the third data output end of the main control single-chip microcomputer circuit, and the 5 pin is connected with the first data output end of the main control single-chip microcomputer circuit; the 9 pin is connected with the second data output end of the master control singlechip circuit, the 13 pin is connected with the ninth control output end of the master control singlechip circuit, the 15 pin is connected with the eighth control output end of the master control singlechip circuit, the 25 pin is connected with the second control output end of the master control singlechip circuit, the 26 pin is connected with the first control output end of the master control singlechip circuit, the 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 and 29 pins are all connected with the 3.3V output end of the power conversion circuit, the 17 pin is connected with the third control output end of the master control singlechip circuit, the 19 pin is connected with the fourth control output end of the master control singlechip circuit, the 7 pin is connected with the seventh control output end of the master control singlechip circuit, the 27 pin is connected with the sixth control output end of the master control singlechip circuit, the 28 pin is connected with the fifth control output end of the master control singlechip circuit, and the 35 pin is grounded.

Twenty pins of the first transmission wiring terminal block are respectively connected with twenty pins of the second transmission wiring terminal block by a 20-core wire bundle; twenty pins of the first communication terminal block are respectively connected with twenty pins of the second communication terminal block by a 20-core wire bundle.

Further, the power supply conversion circuit comprises a first voltage stabilizing chip, a second voltage stabilizing chip and a power supply voltage reducing module; the model of the power supply voltage reducing module is SUCS102412C; the model of the first voltage stabilizing chip is SP1117M3-3.3; the model of the second voltage stabilizing chip is NCP1117DT50G; the pin 1 of the power supply voltage reducing module is connected with the positive electrode of the main board power supply, the negative electrode of the fifth diode D5, the positive electrode of the first capacitor C1 and one end of the second capacitor C2, the pin 2 and the pin 3 are connected with the negative electrode of the main board power supply, the positive electrode of the fifth diode D5, the negative electrode of the first capacitor C1 and the other end of the second capacitor C2, the pin 4 is connected with the positive electrode of the seventh capacitor C7 and one end of the third capacitor C3, the pin 1 of the first voltage stabilizing chip and the pin 1 of the second voltage stabilizing chip, the pin 5 is suspended, and the pin 6 is connected with the negative electrode of the seventh capacitor C7 and the other end of the third capacitor C3 and grounded; the 3 pin of the first voltage stabilizing chip is connected with one end of the fourth capacitor C4 and the anode of the eighth capacitor C8; the 2 pins of the first voltage stabilizing chip, the other end of the fourth capacitor C4 and the negative electrode of the eighth capacitor C8 are all grounded; the 3 pin of the second voltage stabilizing chip is connected with one end of the sixth capacitor C6 and the positive electrode of the ninth capacitor C9; the 2 pin of the second voltage stabilizing chip, the other end of the sixth capacitor C6 and the negative electrode of the ninth capacitor C9 are grounded; the 3 pin of the first voltage stabilizing chip is a 3.3V output end of the power supply conversion circuit; the 3 pin of the second voltage stabilizing chip is the 5V output end of the power supply conversion circuit.

Further, the master control singlechip comprises a first singlechip; the model of the first singlechip is P89V51; the 29 pins of the first singlechip are connected with the 5V output end of the power conversion circuit, the 16 pins are grounded, and the 38 pins are connected with the 5V output end of the power conversion circuit, one end of the fifth capacitor C5 and the common pins of the first resistor bank and the second resistor bank; the other end of the fifth capacitor C5 is grounded; the four common pins of the first resistor bank are respectively connected with pins 34, 35, 36 and 37 of the first singlechip; the four common pins of the second row of resistors are respectively connected with pins 30, 31, 32 and 33 of the first singlechip; pins 32 and 33 of the first singlechip are respectively connected with one end of the sixth key and one end of the seventh key; the other ends of the sixth key and the seventh key are grounded; the 4 pin of the first singlechip is connected with one end of the first resistor R1 and the cathode of the tenth capacitor C10; the other end of the first resistor R1 is grounded; the positive electrode of the tenth capacitor C10 is connected with the 5V output end of the power conversion circuit; the 14 pin of the first singlechip is connected with one end of the first crystal oscillator Z1 and one end of the eleventh capacitor C11, and the 15 pin is connected with the other end of the first crystal oscillator Z1 and one end of the twelfth capacitor C12; the other end of the eleventh capacitor C11 and the other end of the twelfth capacitor C12 are grounded; the 12 pins of the first singlechip are connected with the cathode of the first buzzer; the positive electrode of the first buzzer is connected with the 5V output end of the power supply conversion circuit; the 18 pin of the first singlechip is connected with one end of a seventh resistor R7, the other end of the seventh resistor R7 is connected with the positive electrode of a ninth light emitting tube D9, and the negative electrode of the ninth light emitting tube D9 is grounded; the 19 pin of the first singlechip is connected with one end of an eighth resistor R8, the other end of the eighth resistor R8 is connected with the positive electrode of an eighth luminous tube D8, and the negative electrode of the eighth luminous tube D8 is grounded; the 20 pins of the first singlechip are connected with one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected with the positive electrode of a seventh luminous tube D7, and the negative electrode of the seventh luminous tube D7 is grounded; the pin 21 of the first singlechip is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is connected with the positive electrode of a sixth luminous tube D6, and the negative electrode of the sixth luminous tube D6 is grounded; pins 1, 3, 8, 9, 10, 11, 30, 36 and 37 of the first singlechip are respectively a first control output end to a ninth control output end of the main control singlechip circuit; pins 41, 42, 43 and 44 of the first singlechip are respectively a first data output end to a fourth data output end of the main control singlechip circuit; the 31 pins of the first singlechip are signal interaction ends of the main control singlechip circuit; the other pins of the first singlechip are suspended.

Further, the current sampling circuit comprises a first power supply conversion chip, a second power supply conversion chip, a first digital voltage meter and a second digital voltage meter; the model numbers of the first power conversion chip and the second power conversion chip are NMK0505SAC; the model numbers of the first digital voltmeter head and the second digital voltmeter head are FY5140B; the 1 pins of the first power conversion chip and the second power conversion chip are connected with the 5V output end of the power conversion circuit, and the 2 pins are grounded.

The 3 pin of the first power conversion chip is connected with a first wiring end of a first analog load, a thirty-seventh resistor R37, one end of a twenty-seventh capacitor C20, the 2 pin of the first digital voltage meter head, one end of a resistor in the first potentiometer and a movable contact; the 4 pin of the first power conversion chip is connected with the other end of the thirty-seventh resistor R37 and the 3 pin of the first digital voltage meter; the other end of the resistor body in the first potentiometer is connected with one end of a twenty-ninth resistor R29; the other ends of the twenty-ninth resistor R29 and the twenty-eighth capacitor C20 are connected with one end of the thirty-third resistor R33 and the 1 pin of the first digital voltmeter; the other end of the thirty-third resistor R33 is terminated to a second terminal of the first analog load.

The 3 pin of the second power conversion chip is connected with a first wiring terminal of a second analog load, a thirty-eighth resistor R38, one end of a twenty-first capacitor C21, the 2 pin of a second digital voltmeter head, one end of a resistor in a second potentiometer and a movable contact; the 4 pin of the second power conversion chip is connected with the other end of the thirty-eighth resistor R38 and the 3 pin of the second digital voltage meter; the other end of the inner resistor of the second potentiometer is connected with one end of a thirty-first resistor R30; the other ends of the thirty-fourth resistor R30 and the twenty-first capacitor C21 are connected with one end of the thirty-fourth resistor R34 and the 1 pin of the second digital voltmeter head; the other end of the thirty-fourth resistor R34 is terminated at a second terminal of the second analog load.

Further, the auxiliary channel output signal indicating circuit includes a sixteenth light emitting tube D16, a seventeenth light emitting tube D17, an eighteenth light emitting tube D18, and a nineteenth light emitting tube D19. The anodes of the sixteenth light-emitting tube D16, the seventeenth light-emitting tube D17, the eighteenth light-emitting tube D18 and the nineteenth light-emitting tube D19 are respectively connected with one ends of an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14; the other ends of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14 are all connected with the positive electrode of the main board power supply, and the negative electrodes of the sixteenth light emitting tube D16, the seventeenth light emitting tube D17, the eighteenth light emitting tube D18 and the nineteenth light emitting tube D19 are respectively connected with the first wiring end of the third simulation load, the first wiring end of the fourth simulation load, the first wiring end of the fifth simulation load and the first wiring end of the sixth simulation load.

Further, the memory cell data processing circuit includes a second single chip microcomputer. The model of the second singlechip is P89V51. The 29 pins of the second singlechip are connected with the 5V output end of the power conversion circuit, the 16 pins are grounded, and the 38 pins are connected with the 5V output end of the power conversion circuit, one end of a twenty-fifth capacitor C25 and the common pins of the third resistor bank and the fourth resistor bank; the other end of the twenty-fifth capacitor C25 is grounded; the four common pins of the third row of resistors are respectively connected with pins 34, 35, 36 and 37 of the second singlechip; four common pins of the fourth row of resistors are respectively connected with pins 30, 31, 32 and 33 of the second singlechip; the 4 pin of the second singlechip is connected with one end of a fifteenth resistor R15 and the negative electrode of a twenty-sixth capacitor C26; the other end of the fifteenth resistor R15 is grounded; the positive electrode of the twenty-sixth capacitor C26 is connected with the 5V output end of the power conversion circuit; the 14 pin of the second singlechip is connected with one end of the second crystal oscillator and the twenty-seventh capacitor C27, and the 15 pin is connected with the other end of the second crystal oscillator and one end of the twenty-eighth capacitor C28; the other end of the twenty-seventh capacitor C27 and the twenty-eighth capacitor C28 are grounded; the 32 pins of the second singlechip are connected with the cathode of the second buzzer; the anode of the second buzzer is connected with the 5V output end of the power supply conversion circuit; pins 40, 41, 42, 43, 44, 1, 2, 3, 18, 19, 20, 21, 22, 23, 24 and 25 of the second singlechip are respectively a first signal input end to a sixteenth signal input end of the data processing circuit of the memory unit; pins 30 and 31 of the second singlechip are respectively an IIC clock end and an IIC bidirectional data end of the data processing circuit of the storage unit; pins 35, 36 and 37 of the second singlechip are respectively a first display output end, a second display output end and a third display output end of the data processing circuit of the storage unit; and a 33 pin of the second singlechip is a signal interaction end of the data processing circuit of the storage unit.

Further, the storage unit display circuit comprises a nixie tube driving chip and a nixie tube; the model of the nixie tube driving chip is TM1623; the model of the nixie tube is S02848A-B; the pins 9 and 25 of the nixie tube driving chip are connected with one end of a twenty-fourth capacitor C24 and the 5V output end of the power supply conversion circuit; the other ends of pins 26, 29 and 32 and a twenty-fourth capacitor C24 of the nixie tube driving chip are grounded; pins 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 23, 24, 27, 28, 30 and 31 of the nixie tube driving chip are respectively connected with pins 14, 16, 13, 3, 5, 11, 15, 7, 12, 9, 10, 4, 8, 6, 2 and 1 of the nixie tube M1; the 3, 4 and 5 pins of the nixie tube driving chip are respectively a first signal input end, a second signal input end and a third signal input end of the memory cell display circuit.

Further, the data memory circuit includes a memory chip; the model of the memory chip is 24C01; the pins 1, 2, 3, 4 and 7 of the memory chip are all grounded, and the pin 8 is connected with one end of a twenty-ninth capacitor C29 and the 5V output end of the power supply conversion circuit; the other end of the twenty-ninth capacitor C29 is grounded; and pins 5 and 6 of the memory chip are respectively connected with an IIC bidirectional data end and an IIC clock end of the memory unit data processing circuit.

Further, the feedback signal conversion circuit comprises four first signal feedback units and two second signal feedback units; the first signal feedback unit comprises a first optical coupler; the first input end of the first optocoupler is connected with one end of a forty-fifth resistor R45, the first output end of the first optocoupler is connected with the ground, and the second output end of the first optocoupler is connected with one end of a forty-sixth resistor R46; the other end of the forty-six resistor R46 is connected with the 5V output end of the power conversion circuit.

The second signal feedback unit comprises a second optical coupler and a third optical coupler. The first input end of the second optical coupler and the second input end of the third optical coupler are connected with one end of a sixteenth resistor R16; the second input end of the second optical coupler is connected with the first input end of the third optical coupler; the first output ends of the second optical coupler and the third optical coupler are grounded; the second output end of the second optocoupler is connected with one end of a seventeenth resistor R17; the other end of the seventeenth resistor R17 is connected with the 5V output end of the power conversion circuit; the second output end of the third optocoupler is connected with one end of an eighteenth resistor R18; the other end of the eighteenth resistor R18 is connected with the 5V output end of the power conversion circuit.

The ends, far away from the first optocoupler, of the forty-fifth resistor R45 in the four first signal feedback units are connected together and serve as first analog input ends of the feedback signal conversion circuits; the second input ends of the first optocouplers in the four first signal feedback units are respectively four second analog input ends of the feedback signal conversion circuit; the second output ends of the first optocouplers in the four first signal feedback units are respectively connected with the first signal input end to the fourth signal input end of the data processing circuit of the storage unit.

The ends of the sixteenth resistor R16 in the two second signal feedback units, which are far away from the second optocoupler, are respectively two third analog input ends of the feedback signal conversion circuit; the second input ends of the second optocouplers in the two second signal feedback units are respectively two fourth analog input ends of the feedback signal conversion circuit; the second output ends of the second optocouplers and the third optocouplers in the two second signal feedback units are respectively connected with the fifth signal input end to the eighth signal input end of the data processing circuit of the storage unit.

The invention has the beneficial effects that:

the invention makes the tested PCR drive circuit board finish testing and aging in a strict working environment by powering up and loading, so that the unqualified board can expose the defects in advance, and the intrinsic components in the board can accelerate to pass the fatigue period. And unqualified products are screened out before engineering installation, so that the stability and the production efficiency of the instrument are improved.

Drawings

FIG. 1 is a system block diagram of the present invention;

FIG. 2 is a schematic circuit diagram of a power conversion circuit according to the present invention;

FIG. 3 is a schematic circuit diagram of a master control singlechip circuit according to the present invention;

FIG. 4 is a schematic circuit diagram of a driving signal interface circuit according to the present invention;

FIG. 5 is a schematic circuit diagram of a current sampling circuit according to the present invention;

fig. 6 is a wiring diagram of a first transmission terminal block according to the present invention;

FIG. 7 is a wiring diagram of an output terminal block according to the present invention;

FIG. 8 is a schematic circuit diagram of an auxiliary channel output signal indicating circuit according to the present invention;

FIG. 9 is a schematic circuit diagram of a memory cell display circuit according to the present invention;

FIG. 10 is a schematic circuit diagram showing a key interface circuit according to the present invention;

FIG. 11 is a schematic circuit diagram of a memory cell data processing circuit according to the present invention;

FIG. 12 is a schematic circuit diagram of a data memory circuit of the present invention;

FIG. 13 is a schematic circuit diagram of a first signal feedback unit according to the present invention;

FIG. 14 is a schematic circuit diagram of a second signal feedback unit according to the present invention;

FIG. 15 is a wiring diagram of a second communication terminal block according to the present invention;

fig. 16 is a wiring diagram of a second transmission terminal block according to the present invention;

fig. 17 is a graph of inductance matching according to the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, the driving circuit board test burn-in apparatus of the PCR instrument includes a main board power supply 3, a control main board, and an analog load group 4. The simulated load group 4 includes a first simulated load, a second simulated load, a third simulated load, a fourth simulated load, a fifth simulated load, and a sixth simulated load. The first, second, third, fourth, fifth and sixth simulated loads all adopt gold aluminum shell resistances.

The control main board comprises a power supply conversion circuit 101, a main control singlechip circuit 102, a driving signal interface circuit 103, a current sampling circuit 104, an output interface circuit 105, an auxiliary channel output signal indicating circuit 106, a storage unit display circuit 201, a display key interface circuit 202, a storage unit data processing circuit 203, a data memory circuit 204, a feedback signal conversion circuit 205 and a storage unit signal interface circuit 206. The power conversion circuit 101 converts 24V voltage output by the main board power supply 3 into 12V through a power supply voltage reduction module, converts 12V voltage output by the power supply module into 3.3V through a first voltage stabilizing chip to supply power for the driving signal interface circuit 103, and converts 12V voltage output by the power supply voltage reduction module into 5V through a second voltage stabilizing chip U2 to supply power for the main control singlechip circuit 102, the current sampling circuit 104, the storage unit display circuit 201, the storage unit data processing circuit 203, the data memory circuit 204 and the feedback signal conversion circuit 205. The master control single-chip microcomputer circuit 102 sends a driving signal to the driving signal interface circuit 103 through the first single-chip microcomputer. The driving signal interface circuit 103 and the analog load group 4 are connected with the board 5 to be tested. The current sampling circuit 104 displays the voltage values of the first analog load and the second analog load through the first digital voltage header and the second digital voltage header respectively. The display key interface circuit 202 transmits the model of the board under test to the memory cell data processing circuit 203 by keys. The output interface circuit 105 and the memory cell signal interface circuit 206 transmit the voltage values of the first analog load, the second analog load, the third analog load, the fourth analog load, the fifth analog load, and the sixth analog load to the feedback signal converting circuit 205. The feedback signal conversion circuit 205 converts the received voltage value into a switching value through a photocoupler and transmits the switching value to the memory cell data processing circuit 203. The storage unit data processing circuit 203 determines whether the switching value transmitted from the feedback signal conversion circuit 205 is correct through the second singlechip, and generates a detection code or an error code. The memory cell display circuit 201 displays the detection code or error code transmitted from the memory cell data processing circuit 203 through a nixie tube. The memory circuit 204 stores the detection code or the error code through the memory chip.

As shown in fig. 2, the power conversion circuit 101 includes a first voltage stabilizing chip U1, a second voltage stabilizing chip U2, and a power supply voltage reducing module U7. The model of the power supply voltage reducing module U7 is SUCS102412C. The model of the first voltage stabilizing chip U1 is SU7117M3-3.3. The model of the second voltage stabilizing chip U2 is NCU7117DT50G. The 1 pin of the power supply voltage reducing module U7 is connected with the positive electrode HV+ of the main board power supply 3, the negative electrode of the fifth diode D5, the positive electrode of the first capacitor C1 and one end of the second capacitor C2, the 2 pin and the 3 pin are connected with the positive electrode of the main board power supply 3, the positive electrode of the fifth diode D5, the negative electrode of the first capacitor C1 and the other end of the second capacitor C2, the 4 pin is connected with the positive electrode of the seventh capacitor C7, one end of the third capacitor C3, the 1 pin of the first voltage stabilizing chip U1 and the 1 pin of the second voltage stabilizing chip U2, the 5 pin is suspended, and the 6 pin is connected with the negative electrode of the seventh capacitor C7 and the other end of the third capacitor C3 and is grounded. The 3 pin of the first voltage stabilizing chip U1 is connected with one end of the fourth capacitor C4 and the anode of the eighth capacitor C8; the 2 pin of the first voltage stabilizing chip U1, the other end of the fourth capacitor C4 and the negative electrode of the eighth capacitor C8 are all grounded; the 3 pin of the second voltage stabilizing chip U2 is connected with one end of the sixth capacitor C6 and the anode of the ninth capacitor C9; the 2 pin of the second voltage stabilizing chip U2, the other end of the sixth capacitor C6 and the negative electrode of the ninth capacitor C9 are all grounded. The 3 pin of the first voltage stabilizing chip U1 is the 3.3V output terminal +3.3v of the power conversion circuit 101. The 3 pin of the second voltage stabilizing chip U2 is the 5V output terminal +5v of the power conversion circuit 101.

As shown in fig. 3, the master single-chip microcomputer circuit 102 includes a first single-chip microcomputer U3. The model of the first singlechip U3 is P89V51. The 29 pins of the first singlechip U3 are connected with the 5V output end +5V of the power conversion circuit 101, the 16 pins are grounded, and the 38 pins are connected with the 5V output end +5V of the power conversion circuit 101, one end of the fifth capacitor C5 and the common pins of the first resistor RR1 and the second resistor RR 2. The other end of the fifth capacitor C5 is grounded. Four common pins of the first resistor RR1 are respectively connected with pins 34, 35, 36 and 37 of the first singlechip U3. Four common pins of the second resistor RR2 are respectively connected with pins 30, 31, 32 and 33 of the first singlechip U3. Pins 32 and 33 of the first singlechip U3 are respectively connected with one ends of the sixth key S6 and the seventh key S7. The other ends of the sixth key S6 and the seventh key S7 are grounded. The 4 pins of the first singlechip U3 are connected with one end of the first resistor R1 and the cathode of the tenth capacitor C10. The other end of the first resistor R1 is grounded. The positive electrode of the tenth capacitor C10 is connected with the 5V output end +5V of the power conversion circuit 101; the 14 pin of the first singlechip U3 is connected with one end of the first crystal oscillator Z1 and the eleventh capacitor C11, and the 15 pin is connected with the other end of the first crystal oscillator Z1 and one end of the twelfth capacitor C12. The other ends of the eleventh capacitor C11 and the twelfth capacitor C12 are grounded. The 12 pins of the first singlechip U3 are connected with the cathode of the first buzzer LS 1. The positive pole of the first buzzer LS1 is connected to the 5V output terminal +5v of the power conversion circuit 101. The 18 pin of the first singlechip U3 is connected with one end of a seventh resistor R7, the other end of the seventh resistor R7 is connected with the positive electrode of a ninth luminous tube D9, and the negative electrode of the ninth luminous tube D9 is grounded; the pin 19 of the first singlechip U3 is connected with one end of an eighth resistor R8, the other end of the eighth resistor R8 is connected with the positive electrode of an eighth luminous tube D8, and the negative electrode of the eighth luminous tube D8 is grounded; the 20 pins of the first singlechip U3 are connected with one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected with the positive electrode of a seventh luminous tube D7, and the negative electrode of the seventh luminous tube D7 is grounded; the pin 21 of the first singlechip U3 is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is connected with the positive electrode of a sixth luminous tube D6, and the negative electrode of the sixth luminous tube D6 is grounded. Pins 1, 3, 8, 9, 10, 11, 30, 36 and 37 of the first singlechip U3 are respectively a first control output end to a ninth control output end of the master singlechip circuit 102. Pins 41, 42, 43 and 44 of the first singlechip U3 are respectively a first data output end to a fourth data output end of the main control singlechip circuit 102. The 31 pin of the first singlechip U3 is a signal interaction end of the main control singlechip circuit 102. The other pins of the first singlechip U3 are suspended.

As shown in fig. 4, the driving signal interface circuit 103 is a driving signal connection terminal block J3. The drive signal terminal block J3 has 40 bits. The 1 pin of the driving signal wiring terminal block J3 is connected with the fourth data output end CLK of the master control single-chip microcomputer circuit 102, the 3 pin is connected with the third data output end DIN of the master control single-chip microcomputer circuit 102, and the 5 pin is connected with the first data output end FS of the master control single-chip microcomputer circuit 102; the 9 pin is connected with a second data output end CS of the master control singlechip circuit 102, the 13 pin is connected with a ninth control output end DIR1 of the master control singlechip circuit 102, the 15 pin is connected with an eighth control output end DIR2 of the master control singlechip circuit 102, the 25 pin is connected with a second control output end L-HOTLID of the master control singlechip circuit 102, the 26 pin is connected with a first control output end R-HOTLID of the master control singlechip circuit 102, and the 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 and 29 pins are connected with a 3.3V output end +3.3V of the power conversion circuit 101 and the 17 pin is connected with a third control output end HEATER1 of the master control singlechip circuit 102; the 19 pins of the driving signal wiring terminal block J3 are connected with a fourth control output end HEATER2 of the master control singlechip circuit 102. The 7 pin is connected with a seventh control output end DA_LOAD of the master control single-chip microcomputer circuit 102, the 27 pin is connected with a sixth control output end L-PWM of the master control single-chip microcomputer circuit 102, the 28 pin is connected with a fifth control output end R-PWM of the master control single-chip microcomputer circuit 102, and the 35 pin is grounded. The other pins of the driving signal wiring terminal block J3 are suspended.

As shown in fig. 5, the current sampling circuit 104 includes a first power conversion chip IC1, a second power conversion chip IC2, a first digital voltmeter head BK1, and a second digital voltmeter head BK2. The models of the first power conversion chip IC1 and the second power conversion chip IC2 are NMK0505SAC. The first digital voltmeter head BK1 and the second digital voltmeter head BK2 are respectively of the model number FY5140B. The pins 1 of the first power conversion chip IC1 and the second power conversion chip IC2 are connected with the 5V output end +5V of the power conversion circuit 101, and the pins 2 are grounded.

The 3 pin of the first power conversion chip IC1 is connected with a first wiring terminal TE1-, a thirty-seventh resistor R37, one end of a twentieth capacitor C20, the 2 pin of the first digital voltage meter head BK1, one end of a resistor in the first potentiometer RP1 and a movable contact. The 4 pin of the first power conversion chip IC1 is connected with the other end of the thirty-seventh resistor R37 and the 3 pin of the first digital voltage meter head BK 1. The other end of the resistor in the first potentiometer RP1 is connected with one end of a twenty-ninth resistor R29. The other ends of the twenty-ninth resistor R29 and the twenty-eighth capacitor C20 are connected with one end of the thirty-third resistor R33 and the 1 pin of the first digital voltage meter head BK 1. The other end of the thirty-third resistor R33 is terminated by a second terminal te1+ of the first analog load.

The 3 pin of the second power conversion chip IC2 is connected with a first wiring terminal TE2-, a thirty-eighth resistor R38, one end of a twenty-first capacitor C21, the 2 pin of the second digital voltage meter head BK2, one end of a resistor in the second potentiometer RP2 and a movable contact of the second analog load. The 4 pin of the second power conversion chip IC2 is connected with the other end of the thirty-eighth resistor R38 and the 3 pin of the second digital voltage meter head BK 2. The other end of the internal resistor of the second potentiometer RP2 is connected to one end of the thirty-first resistor R30. The other ends of the thirty-fourth resistor R30 and the twenty-first capacitor C21 are connected with one end of the thirty-fourth resistor R34 and the 1 pin of the second digital voltage meter head BK 2. The other end of the thirty-fourth resistor R34 is terminated by a second terminal te2+ of the second analog load.

As shown in fig. 6 and 7, the output interface circuit 105 includes a first transmission terminal block J19 and an output terminal block J21. Pins 2 and 4 of the first transmission wiring terminal row J19 are respectively connected with first wiring terminals of a first analog load and a second analog load, pins 9 are connected with a signal interaction end P0.6 of the master control singlechip circuit 102, pins 10 are connected with a positive pole HV+ of a main board power supply, and pins 17, 18, 19 and 20 are respectively connected with a first wiring terminal OUT1 of a third analog load, a first wiring terminal OUT2 of a fourth analog load, a first wiring terminal OUT3 of a fifth analog load and a first wiring terminal OUT4 of a sixth analog load. The other pins of the first transmission wiring terminal row J19 are suspended. The second terminals of the third analog load, the fourth analog load, the fifth analog load and the sixth analog load are all connected with the positive pole HV+ of the main board power supply 3.

As shown in fig. 7, pins 1, 2, 9 and 10 of the output terminal block J21 are connected to the second terminal TE1+ of the first analog load, pins 3, 4, 11 and 12 are connected to the first terminal TE1-,5, 6, 13 and 14 of the first analog load, pins 7, 8, 15 and 16 are connected to the second terminal TE 2-of the second analog load.

As shown in fig. 8, the auxiliary channel output signal indicating circuit 106 includes a sixteenth light emitting tube D16, a seventeenth light emitting tube D17, an eighteenth light emitting tube D18, and a nineteenth light emitting tube D19. The anodes of the sixteenth light-emitting tube D16, the seventeenth light-emitting tube D17, the eighteenth light-emitting tube D18 and the nineteenth light-emitting tube D19 are connected to one ends of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14, respectively. The other ends of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14 are respectively connected with the positive pole HV+ of the main board power supply, and the negative poles of the sixteenth light emitting tube D16, the seventeenth light emitting tube D17, the eighteenth light emitting tube D18 and the nineteenth light emitting tube D19 are respectively connected with the first wiring end OUT1 of the third analog load, the first wiring end OUT2 of the fourth analog load, the first wiring end OUT3 of the fifth analog load and the first wiring end OUT4 of the sixth analog load.

As shown in fig. 9, the memory cell display circuit 201 includes a nixie tube driving chip U6 and a nixie tube M1. The model of the nixie tube driving chip U6 is TM1623. The model of the nixie tube is S02848A-B. Pins 9 and 25 of the nixie tube driving chip U6 are connected with one end of the twenty-fourth capacitor C24 and the 5V output end +5V of the power conversion circuit 101. The other ends of pins 26, 29 and 32 of the nixie tube driving chip U6 and the fourth capacitor C24 are grounded. Pins 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 23, 24, 27, 28, 30 and 31 of the nixie tube driving chip U6 are respectively connected with pins 14, 16, 13, 3, 5, 11, 15, 7, 12, 9, 10, 4, 8, 6, 2 and 1 of the nixie tube M1. Pins 3, 4 and 5 of the nixie tube driving chip U6 are respectively a first signal input end DO, a second signal input end CO and a third signal input end SO of the memory cell display circuit 201. The other pins of the nixie tube driving chip U6 are suspended.

As shown in fig. 10, the key interface circuit 202 includes a first communication terminal block J4. Pins 8, 10, 12, 14 and 16 of the first communication terminal block J4 are respectively connected to one ends of the first key S1, the second key S2, the third key S3, the fourth key S4 and the fifth key S5. The other ends of the first key S1, the second key S2, the third key S3, the fourth key S4 and the fifth key S5 are grounded. Pins 11 and 13 of the first communication connection terminal row J4 are connected to the 5V output end +5v of the power conversion circuit 101, pins 7 and 9 are grounded, and pins 1, 3 and 5 are respectively connected to the first signal input end DO, the second signal input end CO and the third signal input end SO of the memory cell display circuit 201. The other pins of the first communication terminal block J4 are suspended.

As shown in fig. 11, the memory cell data processing circuit 203 includes a second single chip microcomputer U4. The model of the second singlechip U4 is P89V51. The 29 pins of the second singlechip U4 are connected with the 5V output end +5V of the power conversion circuit 101, the 16 pins are grounded, and the 38 pins are connected with the common pins of the 5V output end +5V of the power conversion circuit 101, one end of the twenty-fifth capacitor C25, the third resistor RR3 and the fourth resistor RR 4. The other end of the twenty-fifth capacitor C25 is grounded. Four common pins of the third resistor RR3 are respectively connected with pins 34, 35, 36 and 37 of the second singlechip U4. Four common pins of the fourth resistor RR4 are respectively connected with pins 30, 31, 32 and 33 of the second singlechip U4. The 4 pin of the second singlechip U4 is connected with one end of a fifteenth resistor R15 and the cathode of a twenty-sixth capacitor C26. The other end of the fifteenth resistor R15 is grounded. The positive electrode of the twenty-sixth capacitor C26 is connected with the 5V output end +5V of the power conversion circuit 101; the 14 pin of the second singlechip U4 is connected with one end of the second crystal oscillator Z2 and the twenty-seventh capacitor C27, and the 15 pin is connected with the other end of the second crystal oscillator Z2 and one end of the twenty-eighth capacitor C28. The other ends of the twenty-seventh capacitor C27 and the twenty-eighth capacitor C28 are grounded. The 32 pins of the second singlechip U4 are connected with the cathode of the second buzzer LS 2. The positive pole of the second buzzer LS2 is connected to the 5V output terminal +5v of the power conversion circuit 101. Pins 40, 41, 42, 43, 44, 1, 2, 3, 18, 19, 20, 21, 22, 23, 24, 25 of the second singlechip U4 are respectively a first signal input end to a sixteenth signal input end of the memory cell data processing circuit 203. Pins 30 and 31 of the second singlechip U4 are respectively an IIC clock end SCL2 and an IIC bidirectional data end SDA2 of the memory unit data processing circuit 203. Pins 35, 36 and 37 of the second singlechip U4 are respectively a first display output end SI, a second display output end CI and a third display output end DI of the memory unit data processing circuit 203. The 33 pins of the second singlechip U4 are the signal interaction ends F of the memory unit data processing circuit 203. The other pins of the second singlechip U4 are suspended.

As shown in fig. 12, the data memory circuit 204 includes a memory chip U5. The model of the memory chip U5 is 24C01. Pins 1, 2, 3, 4 and 7 of the memory chip U5 are all grounded, and pin 8 is connected with one end of the twenty-ninth capacitor C29 and the 5V output end +5V of the power conversion circuit 101. The other end of the twenty-ninth capacitor C29 is grounded. Pins 5 and 6 of the memory chip U5 are respectively connected to the IIC bidirectional data terminal SDA2 and the IIC clock terminal SCL2 of the memory unit data processing circuit 203.

As shown in fig. 13 and 14, the feedback signal conversion circuit 205 includes four first signal feedback units and two second signal feedback units. The first signal feedback unit includes a first optocoupler P1. The first input end of the first optocoupler P1 is connected with one end of a forty-five resistor R45, the first output end of the first optocoupler P1 is connected with the ground, and the second output end of the first optocoupler P is connected with one end of a forty-six resistor R46. The other end of the forty-sixth resistor R46 is connected with the 5V output end +5V of the power conversion circuit 101;

as shown in fig. 14, the second signal feedback unit includes a second optocoupler P2 and a third optocoupler P3. The first input end of the second optocoupler P2 and the second input end of the third optocoupler P3 are both connected to one end of the sixteenth resistor R16. The second input end of the second optical coupler P2 is connected with the first input end of the third optical coupler P3; the first output ends of the second optical coupler P2 and the third optical coupler P3 are grounded; the second output end of the second optocoupler P2 is connected to one end of the seventeenth resistor R17. The other end of the seventeenth resistor R17 is connected with the 5V output end +5V of the power conversion circuit 101; the second output end of the third optocoupler P3 is connected to one end of the eighteenth resistor R18. The other end of the eighteenth resistor R18 is connected to the 5V output terminal +5v of the power conversion circuit 101.

The ends of the forty-fifth resistors R45 in the four first signal feedback units, which are far away from the first optocoupler P1, are connected together and serve as first analog input ends of the feedback signal conversion circuit 205. The second input ends of the first optocouplers P1 in the four first signal feedback units are respectively four second analog input ends of the feedback signal conversion circuit 205. The second output ends of the first optocouplers P1 in the four first signal feedback units are respectively connected with the first signal input end to the fourth signal input end of the memory unit data processing circuit 203.

The sixteenth resistors R16 in the two second signal feedback units are respectively two third analog input ends of the feedback signal conversion circuit 205, wherein the ends of the sixteenth resistors R16 are far away from the second optocoupler P2. The second input ends of the second optocouplers P2 in the two second signal feedback units are respectively two fourth analog input ends of the feedback signal conversion circuit 205. The second output end of the second optocoupler P2 and the second output end of the third optocoupler P3 in the two second signal feedback units are respectively connected with the fifth signal input end to the eighth signal input end of the data processing circuit 203 of the memory unit.

As shown in fig. 15 and 16, the memory cell signal interface circuit 206 includes a second communication terminal block J15 and a sixteenth terminal block J16. Pins 7 and 9 of the second communication connection terminal row J15 are grounded, pins 11 and 13 are connected with the 5V output end +5V,1, 3 and 5 pins of the power conversion circuit 101, and are respectively connected with the third display output end DI, the second display output end CI and the first display output end SI of the memory unit data processing circuit 203. Pins 2, 4, 6, 8, 10, 12, 14, 16 of the second communication terminal block J15 are connected to the ninth to sixteenth signal inputs of the memory cell data processing circuit 203, respectively.

As shown in fig. 16, the 9 pins of the second transmission connection terminal row J16 are connected to the signal interaction end of the memory cell data processing circuit 203. The 1 pin and the 3 pin of the second transmission connection terminal row J16 are respectively connected to two third analog input ends of the feedback signal conversion circuit 205. Pins 2 and 4 of the second transmission wiring terminal row J16 are respectively connected with two fourth analog input ends of the feedback signal conversion circuit 205, pin 10 is connected with a first analog input end of the feedback signal conversion circuit 205, and pins 17, 18, 19 and 20 are respectively connected with four second analog input ends of the feedback signal conversion circuit 205. The other pins of the second communication terminal block J15 and the second transmission terminal block J16 are suspended.

Twenty pins of the first transmission terminal block J19 are connected to twenty pins of the second transmission terminal block J16 with a 20-wire bundle, respectively. Twenty pins of the first communication terminal block J4 are respectively connected with twenty pins of the second communication terminal block J15 by a 20-core wire bundle

The principle of the invention is as follows:

in the power conversion circuit 101, the fifth diode D5 prevents the power from being connected in reverse, and if the power is connected in reverse, the power is instantaneously burned out by short-circuiting, thereby protecting the following circuits. The first capacitor C1 and the second capacitor C2 are input filter capacitors, so that the input voltage is more stable. The power module U7 is an isolation voltage stabilizing module, and electrically isolates the voltage input by the main board power supply from the voltage output to other circuits, so that the main board power supply and the other circuits cannot be interfered in front-back. And the power module U7 can output 12V voltage to the first voltage stabilizing chip U1 and the second voltage stabilizing chip U2. The first voltage stabilizing chip U1 converts the 12V voltage into the 3.3V voltage. The second voltage stabilizing chip U2 converts the 12V voltage into the 5V voltage. The third capacitor C3, the fourth capacitor C4, the sixth capacitor C7, the seventh capacitor C7, the eighth capacitor C8, and the ninth capacitor C9 are filter capacitors. The module provides a stable and reliable supply voltage for other circuits.

In the master control singlechip circuit 102, the first resistor R1 and the tenth capacitor C10 form a power-on reset circuit, so that the first singlechip U3 is ensured to be restarted after being completely powered on. The first crystal oscillator Z1, the eleventh capacitor C11 and the twelfth capacitor C12 form a system clock, and a stable machine period is given to the first singlechip U3. The first resistor RR1 and the second resistor RR2 are pull-up resistors at the P0 port of the singlechip U3 and are used for providing enough pushing capacity for the P0 port. The first buzzer LS1 is configured to emit operation prompt tones of the sixth button S6 and the seventh button S7. The user selects different operating states by the operation instructions of the sixth key S6 and the seventh key S7. The sixth light emitting tube D6, the seventh light emitting tube D7, the eighth light emitting tube D8 and the ninth light emitting tube D9 are used for displaying working states, and the first singlechip U3 is operated according to a preset program.

In the current sampling circuit 104, because the power supply network of the output port of the tested board is in a floating structure, the current sampling circuit 104 isolates the power supplies of the first digital voltage meter head BK1 and the second digital voltage meter head BK2 through the first power supply conversion chip IC1 and the second power supply conversion chip IC 2. Since the output current for the board to be measured is large, the output current value is obtained by sampling the voltage from both ends of the load and converting the voltage to ensure accuracy. The conversion formula is as follows (1):

In the formula (1), U is a voltage value displayed by a digital voltage meter; ui is the voltage value across the analog load; RP is a fourth potentiometer RP4 and a fifth potentiometer RP5; ra is the twenty-ninth resistor R29 and the thirty-third resistor R30 in the circuit; rb is the thirty-third resistor R33, the thirty-fourth resistor R34 in the circuit.

The main channel output indication circuit 105 is a TE output indication circuit. Taking as an example a separate output indication unit connected to the first analog load. If the voltage at two ends of the first analog load is larger than the parameter voltage value of the TVS tube D1, the third resistor R3 and the TVS tube D1 form a voltage stabilizing circuit, and the twenty-fourth light emitting tube D20 and the twenty-fourth light emitting tube D24 are driven after the parameter voltage of the TVS tube D1 is limited by the fourteenth resistor R14; if the voltage at the two ends of the first analog load is lower than the parameter voltage value of the TVS tube D1, the voltage at the two ends of the first analog load is directly limited by the third resistor R3 and the fourteenth resistor R14 and then drives the fifteenth light emitting tube D15 and the twenty-fourth light emitting tube D24. Since the voltage across the first dummy load has a positive and negative value, the twentieth light emitting tube D20 and the twenty-fourth light emitting tube D24 each show an operating state of positive and negative currents.

In the load cooling fan driving circuit 106, the inductance L1 is selected according to parameters such as the output voltage, the maximum input voltage, and the maximum load current of the switching regulator chip U7. The selection method comprises the following steps: first, a voltage microsecond constant (e·t) is calculated according to formula (2):

E.T= (Vin-Vout) ×Vout/Vinx1000/f (2)

In the formula (2), vin is the maximum input voltage of the switching regulator chip U7, vout is the output voltage of the switching regulator chip U7, and f is the operating oscillation frequency value (52 kHz) of the switching regulator chip U7. After e·t is determined, the inductance value L of the inductance L1 is found from the corresponding voltage·microsecond constant and load current curve in fig. 17.

The capacitance value C of the eighteenth capacitor C18 accords with the value (3)

C is more than or equal to 13300Vin/Vout xL type (3)

In the formula (3), L is an inductance value of the first inductance L1, and its unit is μh. The withstand voltage value of the eighteenth capacitor C18 should be 1.5-2 times larger than the rated output voltage. For a 12V voltage output, a capacitance with a withstand voltage of 25V is recommended.

The rated current value of the twenty-eighth diode D28 is greater than 1.2 times the maximum load current, and the rated current value of the twenty-eighth diode D28 is greater than the maximum current limit of the switching regulator chip U7 in consideration of the condition of a load short circuit. The reverse voltage of the twenty-eighth diode D28 is 1.25 times greater than the maximum input voltage of the switching regulator chip U7. In this embodiment, the twenty eighth diode D28 is a schottky diode of 1N582x series.

The voltage output by the main board power supply is directly input to pins 1 and 3 of the switch voltage stabilizing chip U7 after being filtered by a seventeenth capacitor C17; the 5 pin of the switching voltage stabilizing chip U7 is an output enabling end and is set to be effective after being grounded; the 4 pin is a high-impedance reference voltage end, and the 2 pin is an output end; a sixth wiring terminal row J6 is connected with a loaded heat radiation fan; the eighteenth capacitor C18 and the nineteenth capacitor C19 are output filter capacitors; the second resistor R2, the twenty-eighth resistor R28 and the fifth potentiometer RP5 are used for adjusting the voltage output to the heat dissipation fan, and the specific voltage value Uo output to the heat dissipation fan is as shown in formula (4):

In the equation (4), VREF is a reference voltage value of the switching regulator chip U7, here, 1.23V.

The device is suitable for aging of PCR driving boards with the models of BYQ5615, BYQ5071 and BYQ 5078. The PCR driver board, model BYQ5615, has three external ports, a control port, an output port, and a power port. The PCR driver board, model BYQ5071, has four external ports, a control port, an output port, an auxiliary output port, and a power port, respectively. The PCR driver board, model BYQ5071, has three external ports, a control port, an output port, and a power port.

The working principle of the invention for ageing the side plate of the type BYQ5078 is as follows:

step one, a third connection terminal row J3 in the driving signal interface circuit 103 is connected to a control port of the board under test. The output terminal block J21 in the output interface circuit 105 is connected to the output port of the board under test. The power port of the tested board is connected with the positive electrode HV+ and the negative electrode HV-of the main board power supply.

Step two, the user sets the aging mode through a sixth key S6 and a seventh key S7 in the master control singlechip circuit 102. The first singlechip U3 in the main control singlechip circuit 102 supplies corresponding control signals to the third wiring terminal row J3 in the driving signal interface circuit 103 according to a preset program, so that the tested board is powered on to the analog load from the output port. The first digital voltmeter BK1 and the second digital voltmeter BK2 in the current sampling circuit 104 show the current of two paths. Meanwhile, the voltage on the analog load is transmitted to the feedback signal conversion circuit 205 through the first transmission wiring terminal row J19 in the output interface circuit 105 and the second communication wiring terminal row J15 in the storage unit signal interface circuit 206 to be converted into switching value, and then transmitted to the storage unit data processing circuit 203 to be processed, if the component is normal, the detection code is displayed on the nixie tube M1 of the storage unit display circuit 201; if there is an error, the detected error code is displayed on the nixie tube M1 of the memory cell display circuit 201, and stored into the memory chip U5 in the data memory circuit 204, and the second buzzer LS2 in the memory cell data processing circuit 203 sounds an alarm.

Claims

The device for testing and aging the drive circuit board of the PCR instrument comprises a main board power supply, a control main board and an analog load group; the method is characterized in that: the simulated load group comprises a first simulated load, a second simulated load, a third simulated load, a fourth simulated load, a fifth simulated load and a sixth simulated load; the control main board comprises a power supply conversion circuit, a main control singlechip circuit, a current sampling circuit, an output interface circuit, an auxiliary channel output signal indicating circuit, a storage unit display circuit, a display key interface circuit, a storage unit data processing circuit, a data memory circuit, a feedback signal conversion circuit and a storage unit signal interface circuit; the power supply conversion circuit supplies power to the main control singlechip circuit, the current sampling circuit, the storage unit display circuit, the storage unit data processing circuit, the data memory circuit and the feedback signal conversion circuit through the power supply voltage reduction module, the first voltage stabilizing chip and the second voltage stabilizing chip; the master control singlechip circuit sends a driving signal to the driving signal interface circuit through the first singlechip; the current sampling circuit displays voltage values at two ends of a first analog load and a second analog load respectively through a first digital voltage gauge head and a second digital voltage gauge head; the feedback signal conversion circuit converts the received voltage value into switching value through the photoelectric coupler and transmits the switching value to the storage unit data processing circuit; the storage unit data processing circuit is connected with the storage unit display circuit;

The output interface circuit comprises a first transmission wiring terminal block and an output wiring terminal block; the pins 2 and 4 of the first transmission wiring terminal row are respectively connected with the first wiring ends of the first analog load and the second analog load, the pin 9 is connected with the signal interaction end of the main control singlechip circuit, the pin 10 is connected with the positive electrode of the main board power supply, and the pins 17, 18, 19 and 20 are respectively connected with the first wiring end of the third analog load, the first wiring end of the fourth analog load, the first wiring end of the fifth analog load and the first wiring end of the sixth analog load; the second wiring of the third analog load, the fourth analog load, the fifth analog load and the sixth analog load is connected with the positive electrode of the main board power supply;

pins 1, 2, 9 and 10 of the output wiring terminal row are connected with a second wiring terminal of a first analog load, pins 3, 4, 11 and 12 are connected with a first wiring terminal of the first analog load, pins 5, 6, 13 and 14 are connected with a second wiring terminal of the second analog load, and pins 7, 8, 15 and 16 are connected with a first wiring terminal of the second analog load;

the display key interface circuit comprises a first communication wiring terminal block; pins 8, 10, 12, 14 and 16 of the first communication wiring terminal row are respectively connected with one ends of a first key, a second key, a third key, a fourth key and a fifth key; the other ends of the first key, the second key, the third key, the fourth key and the fifth key are all grounded; pins 11 and 13 of the first communication wiring terminal row are connected with a 5V output end of the power conversion circuit, pins 7 and 9 are grounded, and pins 1, 3 and 5 are respectively connected with a first signal input end, a second signal input end and a third signal input end of the memory cell display circuit;

The storage unit signal interface circuit comprises a second communication wiring terminal row and a second transmission wiring terminal row; the pins 7 and 9 of the second communication wiring terminal row are grounded, the pins 11 and 13 are connected with the 5V output end of the power conversion circuit, and the pins 1, 3 and 5 are respectively connected with the third display output end, the second display output end and the first display output end of the storage unit data processing circuit; pins 2, 4, 6, 8, 10, 12, 14 and 16 of the second communication terminal block are respectively connected with a ninth signal input end to a sixteenth signal input end of the data processing circuit of the storage unit;

the 9 pins of the second transmission wiring terminal block are connected with the signal interaction end of the data processing circuit of the storage unit; the 1 pin and the 3 pin of the second transmission wiring terminal block are respectively connected with two third analog input ends of the feedback signal conversion circuit; the pins 2 and 4 of the second transmission wiring terminal block are respectively connected with two fourth analog input ends of the feedback signal conversion circuit; the 10 pins of the second transmission wiring terminal block are connected with the first analog input end of the feedback signal conversion circuit; pins 17, 18, 19 and 20 of the second transmission wiring terminal block are respectively connected with four second analog input ends of the feedback signal conversion circuit;

The driving signal interface circuit is a driving signal wiring terminal block; the 1 pin of the drive signal wiring terminal block is connected with the fourth data output end of the main control single-chip microcomputer circuit, the 3 pin is connected with the third data output end of the main control single-chip microcomputer circuit, and the 5 pin is connected with the first data output end of the main control single-chip microcomputer circuit; the 9 pin is connected with the second data output end of the master control singlechip circuit, the 13 pin is connected with the ninth control output end of the master control singlechip circuit, the 15 pin is connected with the eighth control output end of the master control singlechip circuit, the 25 pin is connected with the second control output end of the master control singlechip circuit, the 26 pin is connected with the first control output end of the master control singlechip circuit, the 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 and 29 pins are all connected with the 3.3V output end of the power conversion circuit, the 17 pin is connected with the third control output end of the master control singlechip circuit, the 19 pin is connected with the fourth control output end of the master control singlechip circuit, the 7 pin is connected with the seventh control output end of the master control singlechip circuit, the 27 pin is connected with the sixth control output end of the master control singlechip circuit, the 28 pin is connected with the fifth control output end of the master control singlechip circuit, and the 35 pin is grounded;

twenty pins of the first transmission wiring terminal block are respectively connected with twenty pins of the second transmission wiring terminal block by a 20-core wire bundle; twenty pins of the first communication terminal block are respectively connected with twenty pins of the second communication terminal block by a 20-core wire bundle.
2. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the power supply conversion circuit comprises a first voltage stabilizing chip, a second voltage stabilizing chip and a power supply voltage reducing module; the model of the power supply voltage reducing module is SUCS102412C; the model of the first voltage stabilizing chip is SP1117M3-3.3; the model of the second voltage stabilizing chip is NCP1117DT50G; the 1 pin of the power supply voltage reducing module is connected with the positive electrode of a main board power supply, the negative electrode of a fifth diode D5, the positive electrode of a first capacitor C1 and one end of a second capacitor C2, the 2 pin and the 3 pin are connected with the negative electrode of the main board power supply, the positive electrode of the fifth diode D5, the negative electrode of the first capacitor C1 and the other end of the second capacitor C2, the 4 pin is connected with the positive electrode of a seventh capacitor C7, one end of a third capacitor C3, the 1 pin of a first voltage stabilizing chip and the 1 pin of a second voltage stabilizing chip, the 5 pin is suspended, and the 6 pin is connected with the negative electrode of the seventh capacitor C7 and the other end of the third capacitor C3 and grounded; the 3 pin of the first voltage stabilizing chip is connected with one end of the fourth capacitor C4 and the anode of the eighth capacitor C8; the 2 pins of the first voltage stabilizing chip, the other end of the fourth capacitor C4 and the negative electrode of the eighth capacitor C8 are all grounded; the 3 pin of the second voltage stabilizing chip is connected with one end of the sixth capacitor C6 and the positive electrode of the ninth capacitor C9; the 2 pin of the second voltage stabilizing chip, the other end of the sixth capacitor C6 and the negative electrode of the ninth capacitor C9 are grounded; the 3 pin of the first voltage stabilizing chip is a 3.3V output end of the power supply conversion circuit; the 3 pin of the second voltage stabilizing chip is the 5V output end of the power supply conversion circuit.
3. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the master control singlechip circuit comprises a first singlechip; the model of the first singlechip is P89V51; the 29 pins of the first singlechip are connected with the 5V output end of the power conversion circuit, the 16 pins are grounded, and the 38 pins are connected with the 5V output end of the power conversion circuit, one end of the fifth capacitor C5 and the common pins of the first resistor bank and the second resistor bank; the other end of the fifth capacitor C5 is grounded; the four common pins of the first resistor bank are respectively connected with pins 34, 35, 36 and 37 of the first singlechip; the four common pins of the second row of resistors are respectively connected with pins 30, 31, 32 and 33 of the first singlechip; pins 32 and 33 of the first singlechip are respectively connected with one end of the seventh key and one end of the sixth key; the other ends of the sixth key and the seventh key are grounded; the 4 pin of the first singlechip is connected with one end of the first resistor R1 and the cathode of the tenth capacitor C10; the other end of the first resistor R1 is grounded; the positive electrode of the tenth capacitor C10 is connected with the 5V output end of the power conversion circuit; the 14 pin of the first singlechip is connected with one end of the first crystal oscillator Z1 and one end of the eleventh capacitor C11, and the 15 pin is connected with the other end of the first crystal oscillator Z1 and one end of the twelfth capacitor C12; the other end of the eleventh capacitor C11 and the other end of the twelfth capacitor C12 are grounded; the 12 pins of the first singlechip are connected with the cathode of the first buzzer; the positive electrode of the first buzzer is connected with the 5V output end of the power supply conversion circuit; the 18 pin of the first singlechip is connected with one end of a seventh resistor R7, the other end of the seventh resistor R7 is connected with the positive electrode of a ninth light emitting tube D9, and the negative electrode of the ninth light emitting tube D9 is grounded; the 19 pin of the first singlechip is connected with one end of an eighth resistor R8, the other end of the eighth resistor R8 is connected with the positive electrode of an eighth luminous tube D8, and the negative electrode of the eighth luminous tube D8 is grounded; the 20 pins of the first singlechip are connected with one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected with the positive electrode of a seventh luminous tube D7, and the negative electrode of the seventh luminous tube D7 is grounded; the pin 21 of the first singlechip is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is connected with the positive electrode of a sixth luminous tube D6, and the negative electrode of the sixth luminous tube D6 is grounded; pins 1, 3, 8, 9, 10, 11, 30, 36 and 37 of the first singlechip are respectively a first control output end to a ninth control output end of the main control singlechip circuit; pins 41, 42, 43 and 44 of the first singlechip are respectively a first data output end to a fourth data output end of the main control singlechip circuit; the 31 pins of the first singlechip are signal interaction ends of the main control singlechip circuit; the other pins of the first singlechip are suspended.
4. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the current sampling circuit comprises a first power supply conversion chip, a second power supply conversion chip, a first digital voltage meter and a second digital voltage meter; the model numbers of the first power conversion chip and the second power conversion chip are NMK0505SAC; the model numbers of the first digital voltmeter head and the second digital voltmeter head are FY5140B; the 1 pins of the first power conversion chip and the second power conversion chip are connected with the 5V output end of the power conversion circuit, and the 2 pins are grounded;

the 3 pin of the first power conversion chip is connected with a first wiring end of a first analog load, one end of a thirty-seventh resistor R37, one end of a twentieth capacitor C20, the 2 pin of the first digital voltmeter head, one end of a resistor in a first potentiometer and a movable contact; the 4 pin of the first power conversion chip is connected with the other end of the thirty-seventh resistor R37 and the 3 pin of the first digital voltage meter; the other end of the resistor body in the first potentiometer is connected with one end of a twenty-ninth resistor R29; the other ends of the twenty-ninth resistor R29 and the twenty-eighth capacitor C20 are connected with one end of the thirty-third resistor R33 and the 1 pin of the first digital voltmeter; the other end of the thirty-third resistor R33 is connected with a second terminal of the first analog load;

The 3 pin of the second power conversion chip is connected with a first wiring terminal of a second analog load, one end of a thirty-eighth resistor R38, one end of a twenty-first capacitor C21, the 2 pin of a second digital voltmeter head, one end of a resistor in a second potentiometer and a movable contact; the 4 pin of the second power conversion chip is connected with the other end of the thirty-eighth resistor R38 and the 3 pin of the second digital voltage meter; the other end of the inner resistor of the second potentiometer is connected with one end of a thirty-first resistor R30; the other ends of the thirty-fourth resistor R30 and the twenty-first capacitor C21 are connected with one end of the thirty-fourth resistor R34 and the 1 pin of the second digital voltmeter head; the other end of the thirty-fourth resistor R34 is terminated at a second terminal of the second analog load.
5. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the auxiliary channel output signal indicating circuit comprises a sixteenth luminous tube D16, a seventeenth luminous tube D17, an eighteenth luminous tube D18 and a nineteenth luminous tube D19; the anodes of the sixteenth light-emitting tube D16, the seventeenth light-emitting tube D17, the eighteenth light-emitting tube D18 and the nineteenth light-emitting tube D19 are respectively connected with one ends of an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14; the other ends of the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14 are all connected with the positive electrode of the main board power supply, and the negative electrodes of the sixteenth light emitting tube D16, the seventeenth light emitting tube D17, the eighteenth light emitting tube D18 and the nineteenth light emitting tube D19 are respectively connected with the first wiring end of the third simulation load, the first wiring end of the fourth simulation load, the first wiring end of the fifth simulation load and the first wiring end of the sixth simulation load.
6. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the storage unit data processing circuit comprises a second singlechip; the model of the second singlechip is P89V51; the 29 pins of the second singlechip are connected with the 5V output end of the power conversion circuit, the 16 pins are grounded, and the 38 pins are connected with the 5V output end of the power conversion circuit, one end of a twenty-fifth capacitor C25 and the common pins of the third resistor bank and the fourth resistor bank; the other end of the twenty-fifth capacitor C25 is grounded; the four common pins of the third row of resistors are respectively connected with pins 34, 35, 36 and 37 of the second singlechip; four common pins of the fourth row of resistors are respectively connected with pins 30, 31, 32 and 33 of the second singlechip; the 4 pin of the second singlechip is connected with one end of a fifteenth resistor R15 and the negative electrode of a twenty-sixth capacitor C26; the other end of the fifteenth resistor R15 is grounded; the positive electrode of the twenty-sixth capacitor C26 is connected with the 5V output end of the power conversion circuit; the 14 pin of the second singlechip is connected with one end of the second crystal oscillator and the twenty-seventh capacitor C27, and the 15 pin is connected with the other end of the second crystal oscillator and one end of the twenty-eighth capacitor C28; the other end of the twenty-seventh capacitor C27 and the twenty-eighth capacitor C28 are grounded; the 32 pins of the second singlechip are connected with the cathode of the second buzzer; the anode of the second buzzer is connected with the 5V output end of the power supply conversion circuit; pins 40, 41, 42, 43, 44, 1, 2, 3, 18, 19, 20, 21, 22, 23, 24 and 25 of the second singlechip are respectively a first signal input end to a sixteenth signal input end of the data processing circuit of the memory unit; pins 30 and 31 of the second singlechip are respectively an IIC clock end and an IIC bidirectional data end of the data processing circuit of the storage unit; pins 35, 36 and 37 of the second singlechip are respectively a first display output end, a second display output end and a third display output end of the data processing circuit of the storage unit; and a 33 pin of the second singlechip is a signal interaction end of the data processing circuit of the storage unit.
7. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the storage unit display circuit comprises a nixie tube driving chip and a nixie tube M1; the model of the nixie tube driving chip is TM1623; the model of the nixie tube M1 is S02848A-B; the pins 9 and 25 of the nixie tube driving chip are connected with one end of a twenty-fourth capacitor C24 and the 5V output end of the power supply conversion circuit; the other ends of pins 26, 29 and 32 and a twenty-fourth capacitor C24 of the nixie tube driving chip are grounded; pins 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 23, 24, 27, 28, 30 and 31 of the nixie tube driving chip are respectively connected with pins 14, 16, 13, 3, 5, 11, 15, 7, 12, 9, 10, 4, 8, 6, 2 and 1 of the nixie tube M1; the 3, 4 and 5 pins of the nixie tube driving chip are respectively a first signal input end, a second signal input end and a third signal input end of the memory cell display circuit.
8. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the data memory circuit comprises a memory chip; the model of the memory chip is 24C01; the pins 1, 2, 3, 4 and 7 of the memory chip are all grounded, and the pin 8 is connected with one end of a twenty-ninth capacitor C29 and the 5V output end of the power supply conversion circuit; the other end of the twenty-ninth capacitor C29 is grounded; and pins 5 and 6 of the memory chip are respectively connected with an IIC bidirectional data end and an IIC clock end of the memory unit data processing circuit.
9. The device for testing and burn-in of a drive wiring board of a PCR instrument as set forth in claim 1, wherein: the feedback signal conversion circuit comprises four first signal feedback units and two second signal feedback units; the first signal feedback unit comprises a first optical coupler; the first input end of the first optocoupler is connected with one end of a forty-fifth resistor R45, the first output end of the first optocoupler is connected with the ground, and the second output end of the first optocoupler is connected with one end of a forty-sixth resistor R46; the other end of the forty-sixth resistor R46 is connected with the 5V output end of the power conversion circuit;

the second signal feedback unit comprises a second optical coupler and a third optical coupler; the first input end of the second optical coupler and the second input end of the third optical coupler are connected with one end of a sixteenth resistor R16; the second input end of the second optical coupler is connected with the first input end of the third optical coupler; the first output ends of the second optical coupler and the third optical coupler are grounded; the second output end of the second optocoupler is connected with one end of a seventeenth resistor R17; the other end of the seventeenth resistor R17 is connected with the 5V output end of the power conversion circuit; the second output end of the third optocoupler is connected with one end of an eighteenth resistor R18; the other end of the eighteenth resistor R18 is connected with the 5V output end of the power conversion circuit;

the ends, far away from the first optocoupler, of the forty-fifth resistor R45 in the four first signal feedback units are connected together and serve as first analog input ends of the feedback signal conversion circuits; the second input ends of the first optocouplers in the four first signal feedback units are respectively four second analog input ends of the feedback signal conversion circuit; the second output ends of the first optocouplers in the four first signal feedback units are respectively connected with the first signal input end to the fourth signal input end of the data processing circuit of the storage unit;

The ends of the sixteenth resistor R16 in the two second signal feedback units, which are far away from the second optocoupler, are respectively two third analog input ends of the feedback signal conversion circuit; the second input ends of the second optocouplers in the two second signal feedback units are respectively two fourth analog input ends of the feedback signal conversion circuit; the second output ends of the second optocouplers and the third optocouplers in the two second signal feedback units are respectively connected with the fifth signal input end to the eighth signal input end of the data processing circuit of the storage unit.