CN206387856U - Low pressure SVG test circuits - Google Patents
Low pressure SVG test circuits Download PDFInfo
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- CN206387856U CN206387856U CN201621285352.7U CN201621285352U CN206387856U CN 206387856 U CN206387856 U CN 206387856U CN 201621285352 U CN201621285352 U CN 201621285352U CN 206387856 U CN206387856 U CN 206387856U
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Abstract
The utility model discloses a kind of low pressure SVG test circuits, it includes FPGA master controls and peripheral circuit, current sensor, auxiliary power circuit, drive circuit, relay module circuit, communicating circuit, FPGA master controls and peripheral circuit are connected with current sensor, current sensor is connected with drive circuit, drive circuit is connected with relay module circuit, relay module circuit is connected with communicating circuit, communicating circuit is connected with auxiliary power circuit, and auxiliary power circuit is connected with FPGA master controls and peripheral circuit.The utility model carries out preliminary test with low-voltage to SVG modules, prevents the great bodily injury caused by the device failure of some poor performance is to SVG modules when normal aging is tested of SVG modules.
Description
Technical field
The utility model is related to a kind of test circuit, more particularly to a kind of low pressure SVG test circuits.
Background technology
The SVG modules just produced are to be detected by the simulation normal work of more than eight hours, if out of question
It is considered as qualified products, but if having there is device failure if before during simulation normal work, that is then gently that module does not work,
Other devices that are serious then can causing module are damaged and cause whole module to be paralysed.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of low pressure SVG test circuits, and it is with low-voltage to SVG
Module carries out preliminary test, prevents SVG modules when normal aging is tested because the device failure of some poor performance is to SVG modules
Cause great bodily injury.
The utility model is to solve above-mentioned technical problem by following technical proposals：, a kind of low pressure SVG test electricity
Road, it is characterised in that it includes FPGA master controls and peripheral circuit, current sensor, auxiliary power circuit, drive circuit, relay
Device modular circuit, communicating circuit, FPGA master controls and peripheral circuit are connected with current sensor, and current sensor connects with drive circuit
Connect, drive circuit is connected with relay module circuit, relay module circuit is connected with communicating circuit, communicating circuit and auxiliary electricity
Source circuit is connected, and auxiliary power circuit is connected with FPGA master controls and peripheral circuit；
The auxiliary power circuit includes the 17th resistance, the 18th resistance, the 19th resistance, the 20th resistance, second
Ten electric capacity, the 21st electric capacity, the 22nd electric capacity, the 28th electric capacity, the 29th electric capacity, the 32nd electric capacity, the 3rd
12 electric capacity, fifth chip, the second inductance, the 32nd electric capacity are connected with the 32nd electric capacity, the 32nd electric capacity successively with
Second inductance, the 29th electric capacity, fifth chip be connected, the 19th resistance successively with the 20th resistance, the 32nd electric capacity phase
Even, the 18th resistance is connected with the 28th electric capacity, fifth chip successively, and the 22nd electric capacity is connected with fifth chip, and second
Ten electric capacity are connected with the 21st electric capacity, and the 21st electric capacity is connected with the 17th resistance, the 17th resistance and fifth chip phase
Even；
The drive circuit includes the 14th electric capacity, the 39th resistance, the 40th resistance, the 14th switching tube, second
17 diodes, the 28th diode, the 40th resistance are connected with the 39th resistance, the 39th resistance and the 14th electricity
Hold be connected, the 14th electric capacity is connected with the 14th switching tube, the 14th switching tube successively with the 27th diode, the 28th
Diode is connected.
Preferably, the relay module circuit includes the 6th power supply, the first relay, the second relay, the 3rd relay
Device, the 4th relay, the 5th relay, the 6th relay, the first relay, the second relay, the 3rd relay, the 4th relay
Device, the 5th relay, the 6th relay are all connected with the 6th power supply.
Preferably, the communicating circuit includes the 41st resistance, the 42nd resistance, the 43rd resistance, the 40th
Four resistance, the 45th resistance, the 46th resistance, the 57th resistance, the 58th resistance, the 8th chip, the 9th chip,
11st chip, the 35th chip, the 15th switching tube, sixteenmo close pipe, the 17th switching tube, the 46th electric capacity,
47th electric capacity, the 48th electric capacity, the 51st electric capacity, the 6th inductance, the 41st resistance are connected with the 8th chip, the
Eight chips are connected with the 15th switching tube, and the 15th switching tube is connected with the 42nd resistance, the 42nd resistance and the 50th
One electric capacity is connected, and the 46th resistance is connected with the 47th electric capacity, and the 47th electric capacity is connected with the 11st chip, and the 11st
Chip is connected with the 17th switching tube, and the 17th switching tube is connected with the 45th resistance, the 57th resistance, the 58th electricity
Resistance, the 48th electric capacity be all connected with the 35th chip, the 6th inductance is connected with the 57th resistance, the 43rd resistance and
9th chip is connected, and the 9th chip closes pipe with sixteenmo and is connected, and sixteenmo is closed to be connected with the 46th electric capacity, and the 46th
Electric capacity is connected with the 44th resistance.
Positive effect of the present utility model is：The utility model carries out preliminary survey with low-voltage to SVG modules
Examination, prevents the great bodily injury caused by the device failure of some poor performance is to SVG modules when normal aging is tested of SVG modules.
Brief description of the drawings
Fig. 1 is the circuit diagram of FPGA master controls and peripheral circuit in the utility model.
Fig. 2 is the circuit diagram of auxiliary power circuit in the utility model.
Fig. 3 is the circuit diagram of drive circuit in the utility model.
Fig. 4 is a circuit diagram of the utility model repeat circuit module.
Fig. 5 is the circuit diagram of communicating circuit in the utility model.
Fig. 6 is the structural representation of the utility model low pressure SVG test circuits.
Embodiment
The utility model preferred embodiment is provided below in conjunction with the accompanying drawings, to describe the technical solution of the utility model in detail.
As shown in fig. 6, the utility model low pressure SVG (Static Var Generator, static reacance generator) is tested
Circuit include FPGA (Field-Programmable Gate Array, field programmable gate array) master controls and peripheral circuit,
Current sensor, auxiliary power circuit, drive circuit, relay module circuit, communicating circuit, FPGA master controls and peripheral circuit with
Current sensor is connected, and current sensor is connected with drive circuit, and drive circuit is connected with relay module circuit, relay mould
Block circuit is connected with communicating circuit, and communicating circuit is connected with auxiliary power circuit, auxiliary power circuit and FPGA master controls and periphery
Circuit is connected.
As shown in Fig. 2 auxiliary power circuit include the 17th resistance R17, the 18th resistance R18, the 19th resistance R19,
20th resistance R20, the 20th electric capacity C20, the 21st electric capacity C21, the 22nd electric capacity C22, the 28th electric capacity C28,
29th electric capacity C29, the 32nd electric capacity C30, the 32nd electric capacity C32, fifth chip U5, the second inductance L2, the 30th
Two electric capacity C30 are connected with the 32nd electric capacity C32, the 32nd electric capacity C30 successively with the second inductance L2, the 29th electric capacity
C29, fifth chip U5 are connected, and the 19th resistance R19 is connected with the 20th resistance R20, the 32nd electric capacity C30 successively, and the tenth
Eight resistance R18 are connected with the 28th electric capacity C28, fifth chip U5 successively, the 22nd electric capacity C22 and fifth chip U5 phases
Even, the 20th electric capacity C20 is connected with the 21st electric capacity C21, and the 21st electric capacity C21 is connected with the 17th resistance R17, and the tenth
Seven resistance R17 are connected with fifth chip U5.Fifth chip U5 is power management chip, and model can be MP2307.
As shown in figure 3, drive circuit includes the 14th electric capacity C14, the 39th resistance R39, the 40th resistance R40, the
14 switching tube Q14, the 27th diode D27, the 28th diode D28, the electricity of the 40th resistance R40 and the 39th
Hinder R39 to be connected, the 39th resistance R39 is connected with the 14th electric capacity C14, the 14th electric capacity C14 and the 14th switching tube Q14 phases
Even, the 14th switching tube Q14 is connected with the 27th diode D27, the 28th diode D28 successively.
As shown in figure 4, relay module circuit includes the 6th power supply J6, the first relay K1, the second relay K2, the 3rd
Relay K3, the 4th relay K4, the 5th relay K5, the 6th relay K6, the first relay K1, the second relay K2,
Three relay K3, the 4th relay K4, the 5th relay K5, the 6th relay K6 are connected with the 6th power supply J6.
As shown in figure 5, communicating circuit includes the 41st resistance R41, the 42nd resistance R42, the 43rd resistance
R43, the 44th resistance R44, the 45th resistance R45, the 46th resistance R46, the 57th resistance R57, the 58th
Resistance R58, the 8th chip U8, the 9th chip U9, the 11st chip U11, the 35th chip U35, the 15th switching tube Q15,
Sixteenmo closes pipe Q16, the 17th switching tube Q17, the 46th electric capacity C46, the 47th electric capacity C47, the 48th electric capacity
C48, the 51st electric capacity C51, the 6th inductance L6, the 41st resistance R41 are connected with the 8th chip U8, the 8th chip U8 with
15th switching tube Q15 is connected, and the 15th switching tube Q15 is connected with the 42nd resistance R42, the 42nd resistance R42 and the
51 electric capacity C51 are connected, and the 46th resistance R46 is connected with the 47th electric capacity C47, the 47th electric capacity C47 and the tenth
One chip U11 is connected, and the 11st chip U11 is connected with the 17th switching tube Q17, the electricity of the 17th switching tube Q17 and the 45th
Hinder R45 be connected, the 57th resistance R57, the 58th resistance R58, the 48th electric capacity C48 all with the 35th chip U35
It is connected, the 6th inductance L6 is connected with the 57th resistance R57, and the 43rd resistance R43 is connected with the 9th chip U9, the 9th chip
U9 closes pipe Q16 with sixteenmo and is connected, and sixteenmo closes pipe Q16 and is connected with the 46th electric capacity C46, the 46th electric capacity C46
It is connected with the 44th resistance R44.
Operation principle：FPGA master controls and peripheral circuit and communicating circuit have signal to transmit and be signaled to driving electricity
Road, the communication between extraneous PC is realized in the reliable communicating circuits of this FPGA, also reliable drive circuit driving relay
Adhesive or the effect of disconnection.
Communicating circuit is to constitute the function module circuit with electric isolation type by communication chip SN75176 and photo-coupler,
FPGA realizes the communication with PC by communicating circuit.
Auxiliary power circuit be have chip MP2307 and some peripheral circuits realize by DC15V become the 5V that swaps out, 3.3V,
1.2V powers to FPGA, drive circuit, communicating circuit respectively.
The main function of drive circuit is FPGA to be sent the weaker signal of driving force to be converted into driving force stronger
Signal drives relay module.
The function of relay module has changes the step mode to SVG modules in the different time respectively, is carried out when to SVG
The when relay supply low pressure 30V alternating voltages of burn-in test are simulated, when the current sensor to SVG modules carries out parameter school
Timing relay supplies 6V alternating voltages；Relay will be driven to disconnect the confession to SVG when FPGA receives washout
Electrical testing.
Current sensor mainly provides a reference value when parameter correction is carried out to SVG modules.
As shown in figure 1, FPGA is as Master control chip, it may be seen that the extraneous pin of chip has power supply to connect from figure
Mouthful, the communication interface of RS485 agreements, relay driver interface (F_RY_C1 to F_RY_C15)；Power interface is mainly external
Accessory power supply is to chip power supply, and the main extraneous communicating circuit of the communication interface based on RS485 agreements realizes information transfer capability, after
Electrical equipment drive interface is to drive relay to send corresponding action when FPGA sends drive signal.
Accessory power supply mainly have chip MP2307 and some resistance capacitances also have 22uH inductor combination into one
Supply convertor, chip internal is integrated with switching tube and some discharge circuits etc., when 15V power supplys are added in the 2nd (IN) pipes of chip
When pin, the value for changing feedback voltage by adjusting resistance R20 and R19 resistance is given to the 5th pin (FB) of chip with regard to adjusting
Save the size of output voltage；Same principle becomes swap out 5V, 3.3V, 1.2V voltage with 15V.
When FPGA will make the second relay K2 send action (adhesive or disconnection), the signal that FPGA is sent leads to first
Crossing switching tube MOSFET (Q14) increasings draws tank current capacity just to make the coil adhesive of relay；When switch conduction after
The termination RY_C15 ground connection of electric apparatus coil one, the voltage for being now added in relay coil is 15V, and relay is in attracting state；When
When switching tube disconnects, RY_C15 voltages are 15V, and relay is off.
The function of relay module is mainly used for being respectively supplied to module 30VAC and detection and 6VAC short circuit current flows；When
When 4th relay K4, the 5th relay K5, the 6th relay K6 adhesives, tested SVG modules are powered in 30VAC
State, now other relays be off, then now MA, MB, MC are to provide with VSA, VSB, VSC connection function respectively
Voltage is detected to SVG modules；When the 4th relay K4, the 5th relay K5, the 6th relay K6 disconnect when, other after
When electrical equipment is all in attracting state, tested SVG modules are in 6VAC short circuits and provide analog current test correcting current
Sensor parameters correcting state.The utility model carries out preliminary test with low-voltage to SVG modules, prevents SVG modules just
The great bodily injury caused by the device failure of some poor performance is to SVG modules during normal burn-in test.
Communicating circuit mainly has photoelectrical coupler, the communication chip SN75176 of RS485 agreements, switching tube MOSFET and one
A little resistance capacitance compositions；The effect of photo-coupler is mainly used in electrical isolation, and letter can be sent when FPGA is with extraneous communicate
Number F_485TX is transferred to, at this moment switching tube can make corresponding action (on or off), the pole of internal illumination two of photo-coupler
Pipe also can light or extinguish, and signal is transferred to communication chip SN75176 like this, communication chip makes corresponding action again
Signal is sent out；When FPGA receives external signal, the work of photo-coupler and switching tube MOSFET is also same
Principle.
Particular embodiments described above, to the technical problem, technical scheme and beneficial effect of solution of the present utility model
It is further described, should be understood that and the foregoing is only specific embodiment of the utility model, not
For limiting the utility model, all any modifications within spirit of the present utility model and principle, made, equivalent substitution, change
Enter, should be included within protection domain of the present utility model.
Claims (3)
1. a kind of low pressure SVG test circuits, it is characterised in that it includes FPGA master controls and peripheral circuit, current sensor, auxiliary
Power circuit, drive circuit, relay module circuit, communicating circuit, FPGA master controls and peripheral circuit are connected with current sensor,
Current sensor is connected with drive circuit, and drive circuit is connected with relay module circuit, relay module circuit and communication electricity
Road is connected, and communicating circuit is connected with auxiliary power circuit, and auxiliary power circuit is connected with FPGA master controls and peripheral circuit；
The auxiliary power circuit includes the 17th resistance, the 18th resistance, the 19th resistance, the 20th resistance, the 20th electricity
Appearance, the 21st electric capacity, the 22nd electric capacity, the 28th electric capacity, the 29th electric capacity, the 32nd electric capacity, the 32nd
Electric capacity, fifth chip, the second inductance, the 32nd electric capacity are connected with the 32nd electric capacity, and the 32nd electric capacity is successively with second
Inductance, the 29th electric capacity, fifth chip are connected, and the 19th resistance is connected with the 20th resistance, the 32nd electric capacity successively, the
18 resistance are connected with the 28th electric capacity, fifth chip successively, and the 22nd electric capacity is connected with fifth chip, the 20th electric capacity
It is connected with the 21st electric capacity, the 21st electric capacity is connected with the 17th resistance, the 17th resistance is connected with fifth chip；
The drive circuit includes the 14th electric capacity, the 39th resistance, the 40th resistance, the 14th switching tube, the 27th
Diode, the 28th diode, the 40th resistance are connected with the 39th resistance, the 39th resistance and the 14th electric capacity phase
Even, the 14th electric capacity is connected with the 14th switching tube, the 14th switching tube successively with the 27th diode, the 28th pole
Pipe is connected.
2. low pressure SVG test circuits as claimed in claim 1, it is characterised in that the relay module circuit includes the 6th
Power supply, the first relay, the second relay, the 3rd relay, the 4th relay, the 5th relay, the 6th relay, first after
Electrical equipment, the second relay, the 3rd relay, the 4th relay, the 5th relay, the 6th relay are all connected with the 6th power supply.
3. low pressure SVG test circuits as claimed in claim 1, it is characterised in that the communicating circuit includes the 41st electricity
Resistance, the 42nd resistance, the 43rd resistance, the 44th resistance, the 45th resistance, the 46th resistance, the 57th
Resistance, the 58th resistance, the 8th chip, the 9th chip, the 11st chip, the 35th chip, the 15th switching tube, the tenth
Six switching tubes, the 17th switching tube, the 46th electric capacity, the 47th electric capacity, the 48th electric capacity, the 51st electric capacity,
Six inductance, the 41st resistance is connected with the 8th chip, and the 8th chip is connected with the 15th switching tube, the 15th switching tube and
42 resistance are connected, and the 42nd resistance is connected with the 51st electric capacity, and the 46th resistance is connected with the 47th electric capacity,
47th electric capacity is connected with the 11st chip, and the 11st chip is connected with the 17th switching tube, the 17th switching tube and the 4th
15 resistance are connected, and the 57th resistance, the 58th resistance, the 48th electric capacity are all connected with the 35th chip, and the 6th
Inductance is connected with the 57th resistance, and the 43rd resistance is connected with the 9th chip, and the 9th chip closes pipe with sixteenmo and is connected,
Sixteenmo is closed to be connected with the 46th electric capacity, and the 46th electric capacity is connected with the 44th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621285352.7U CN206387856U (en) | 2016-11-28 | 2016-11-28 | Low pressure SVG test circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621285352.7U CN206387856U (en) | 2016-11-28 | 2016-11-28 | Low pressure SVG test circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206387856U true CN206387856U (en) | 2017-08-08 |
Family
ID=59486671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621285352.7U Active CN206387856U (en) | 2016-11-28 | 2016-11-28 | Low pressure SVG test circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206387856U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108490343A (en) * | 2018-05-22 | 2018-09-04 | 杭州博日科技有限公司 | The driver circuit board test aging equipment of PCR instrument |
-
2016
- 2016-11-28 CN CN201621285352.7U patent/CN206387856U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108490343A (en) * | 2018-05-22 | 2018-09-04 | 杭州博日科技有限公司 | The driver circuit board test aging equipment of PCR instrument |
| CN108490343B (en) * | 2018-05-22 | 2023-07-25 | 杭州博日科技股份有限公司 | Drive circuit board test aging device of PCR instrument |
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