CN113489475B

CN113489475B - Digital and PWM composite controller

Info

Publication number: CN113489475B
Application number: CN202110862421.5A
Authority: CN
Inventors: 陈小龙; 张弢; 骆建勇
Original assignee: Shenzhen Double Cnc Technology Co ltd
Current assignee: Shenzhen Double Cnc Technology Co ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2024-05-10
Anticipated expiration: 2041-07-29
Also published as: CN113489475A

Abstract

The invention discloses a digital and PWM composite controller, which comprises a shell, wherein a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module; the digital quantity input and output, the analog quantity input and output and the PWM output module are integrated together, and compared with the existing various functional separated design modules, the connecting lines among the modules are realized by the layout of a circuit board, so that the trouble of wiring and the external interference during signal transmission are greatly reduced.

Description

Digital and PWM composite controller

Technical Field

The invention relates to the technical field of electronics, in particular to a digital and PWM composite controller.

Background

In the current EtherCAT bus laser scheme, if a PWM signal is required to control a laser, a PWM module is required to be added separately; in the existing module, digital quantity input and output, analog quantity input and output and high-precision PWM output are separately designed into independent circuit modules; aiming at the market of laser cutting machine tools, each module is independently separated, wiring is troublesome when the laser cutting machine is used on site, cost is high, the laser cutting machine is easily affected by external interference when signals are transmitted between the modules, and anti-interference performance is poor.

There is thus a need for improvements and improvements in the art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a digital and PWM composite controller, so as to solve the problems of troublesome wiring and poor interference caused by independent separation of the modules of the existing digital input/output, analog input/output and PWM output.

In order to achieve the above purpose, the invention adopts the following technical scheme:

The digital and PWM composite controller comprises an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module;

The analog quantity transmission module carries out analog-to-digital conversion on an analog quantity signal input from the outside, then transmits the analog quantity signal to the control module for processing, monitors the signal transmission state and feeds the signal back to the control module through the coding and decoding module; the analog output signal output by the control module is output after digital-to-analog conversion by the analog transmission module;

the digital quantity transmission module isolates the digital quantity signals input from the outside and transmits the signals to the control module for processing through the encoding and decoding module; the digital quantity output signal output by the control module is transmitted to the analog quantity transmission module through the coding and decoding module, and the analog quantity transmission module is isolated and then output;

The coding and decoding module is used for expanding the interface of the control module and transmitting signals;

the hand wheel processing module transmits hand wheel data to the control module through the coding and decoding module, isolates hand wheel signals and transmits the hand wheel signals to the control module, and also isolates hand wheel control signals output by the control module and outputs the hand wheel control signals;

The PWM output module is used for isolating, converting voltage and outputting corresponding PWM signals after driving the PWM control signals output by the control module;

The communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer.

In the digital and PWM composite controller, the analog quantity transmission module comprises an analog quantity input unit and an analog quantity output unit; the analog input unit is connected with the analog output unit and the control module, and the analog output unit is connected with the coding and decoding module;

The analog input unit filters, amplifies and analog-to-digital converts an externally input analog signal and transmits the externally input analog signal to the control module;

The analog output unit monitors the signal transmission state and feeds the signal transmission state back to the control module through the coding and decoding module; the analog output signal output by the control module is output after digital-to-analog conversion through the analog output unit.

In the digital and PWM composite controller, the analog input unit comprises a first interface, an analog input chip, a first operational amplifier circuit, a second operational amplifier circuit, a third operational amplifier circuit and a fourth operational amplifier circuit;

The 1 st pin and the 2 nd pin of the first interface are connected with the first input pin and the second input pin of the first operational amplifier circuit one by one; the 3 rd pin and the 4 th pin of the first interface are connected with the first input pin and the second input pin of the second operational amplifier circuit one by one; the 5 th pin and the 6 th pin of the first interface are connected with the first input pin and the second input pin of the third operational amplifier circuit one by one; the 7 th pin and the 8 th pin of the first interface are connected with the first input pin and the second input pin of the fourth operational amplifier circuit one by one; the 9 th pin of the first interface is connected with the 10 th pin and shielding ground; the first output pin and the second output pin of the first operational amplifier circuit are connected with the AIN_0P pin and the AIN_0GND pin of the analog input chip one by one; the first output pin and the second output pin of the second operational amplifier circuit are connected with the AIN_1P pin and the AIN_1GND pin of the analog input chip one by one; the first output pin and the second output pin of the third operational amplifier circuit 3 are connected with the AIN_2P pin and the AIN_2GND pin of the analog input chip one by one; the first output pin and the second output pin of the fourth operational amplifier circuit are connected with the AIN_3P pin and the AIN_3GND pin of the analog input chip one by one; the AVDD pin of the analog input chip inputs a first voltage, the DVDD pin of the analog input chip inputs a second voltage, and the AUX_IN pin of the analog input chip is connected with the AUX_GND pin and analog ground; the REFIO pin and the REFCAP pin of the analog input chip are respectively connected with analog ground through a capacitor; analog quantity input chip Foot,/>The feet and the ALARM feet are connected with the control module; the SCLK pin, the SDI pin and the SDO pin of the analog input chip are connected with the analog output unit and the control module; RDFGND pins of analog quantity input chip,/>Foot, AGND foot, DA/SY foot, DGND foot are all grounded.

In the digital and PWM composite controller, the analog output unit comprises a second interface, an analog output chip, a fifth resistor, a sixth resistor, a first output circuit, a second output circuit, a third output circuit and a fourth output circuit;

The DVcc pin of the analog output chip inputs the third voltage, and the analog output chip outputs the third voltage The foot is connected with digital ground; /> analog output chipFoot,/>Foot and/>The feet are connected with the control module; the SCLK pin of the analog output chip is connected with the SCLK pin of the analog input chip and the control module, the SDIN pin of the analog output chip is connected with the SDI pin of the analog input chip and the control module, the SDO pin of the analog output chip is connected with the SDO pin of the analog input chip and the control module, the REFIN/REFOUT pin of the analog output chip is connected with the GND pin of the analog output chip and the digital ground through a capacitor, and the AVdd pin of the analog output chip inputs a first voltage; the VoutA pin, the VoutB pin, the VoutC pin and the VoutD pin of the analog output chip are connected with the first input pin of the first output circuit, the first input pin of the second output circuit, the first input pin of the third output circuit and the first input pin of the fourth output circuit one by one; the AVss pin, the SIG_GND pin, the DAC_GND pin and the EPAD pin of the analog quantity output chip are all connected with an analog ground; the first output pin and the second output pin of the first output circuit are connected with the 10 th pin and the 9 th pin of the second interface one by one; the first output pin and the second output pin of the second output circuit are connected with the 8 th pin and the 7 th pin of the second interface one by one; the first output pin and the second output pin of the third output circuit are connected with the 6 th pin and the 5 th pin of the second interface one by one; the first output pin and the second output pin of the fourth output circuit are connected with the 4 th pin and the 3 rd pin of the second interface one by one; the 1 st pin of the second interface is connected with the 2 nd pin and shielding ground, and the third output pins of the first output circuit to the fourth output circuit are connected with the coding and decoding module; one end of the fifth resistor is input with the first voltage, the other end of the fifth resistor is connected with one end of the sixth resistor and the second input pins of the output circuits, and the other end of the sixth resistor is connected with the analog ground.

In the digital and PWM composite controller, the digital quantity transmission module comprises a third interface, a fourth interface, a fifth interface, a sixth interface, a seventh interface, 48 digital quantity input units, 8 digital quantity output units and a monitoring feedback unit;

The 1 st pin of the third interface is connected with the input pin of the first digital quantity input unit, the 2 nd pin is connected with the input pin of the second digital quantity input unit, and the 15 th pin of the third interface is connected with the input pin of the sixteenth digital quantity input unit; each pin of the fourth interface is correspondingly connected with the seventeenth digital quantity input unit to the input pin of the thirty-third digital quantity input unit, each pin of the fifth interface is correspondingly connected with the input pins of the thirty-third digital quantity input unit to the forty-eighth digital quantity input unit, and the output pins of the digital quantity input units are all connected with the coding and decoding module; each output pin of the first digital quantity output unit to the fourth digital quantity output unit is connected with a sixth interface, each output pin of the fifth digital quantity output unit to the eighth digital quantity output unit is connected with a seventh interface, and each input pin of the digital quantity output unit is connected with a coding and decoding module.

In the digital and PWM composite controller, the control module comprises a main control chip and a burning interface; the PA0_WKUP pin, the PA1 pin and the PD13 pin of the main control chip are all connected with a hand wheel processing module; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip are all connected with the communication module; the PA8 pin and the PD15 pin of the main control chip are both connected with the PWM output module; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip are connected with the 2 nd pin, the 1 st pin, the 5 th pin and the 6 th pin of the burning interface one to one; PB8 pin, PB9 pin, PB12 pin and analog output chip of main control chipA foot part,Foot,/>The feet are connected one by one; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin, PE15 pin and analog input chip of main control chip/>Foot, ALARM foot, SCLK foot, SDO foot, SDI foot,/>The feet are connected one by one; and the PC0 pin to the PC7 pin, the PD0 pin to the PD12 pin and the PE5 pin of the main control chip are all connected with the coding and decoding module.

In the digital and PWM composite controller, the coding and decoding module comprises 9 decoding units and 4 latching units; each decoding unit and each latch unit are connected with the control module;

The first decoding unit is connected with the digital quantity transmission module, and the seventh decoding unit is used for decoding the digital quantity signal input by the digital quantity transmission module and transmitting the digital quantity signal to the control module;

The eighth decoding unit is connected with the analog quantity transmission module and is used for decoding the monitoring signal output by the analog quantity transmission module and transmitting the monitoring signal to the control module;

The ninth decoding unit is connected with the hand wheel processing module and is used for decoding the hand wheel data transmitted by the hand wheel processing module and transmitting the decoded hand wheel data to the control module;

the first latch unit to the fourth latch unit are connected with the control module and the digital quantity transmission module and are used for latching the digital quantity output signals output by the control module and outputting the digital quantity output signals to the digital quantity transmission module.

In the digital and PWM composite controller, the hand wheel processing module comprises a hand wheel interface, a third optocoupler, a fourth optocoupler, a fifth optocoupler, a sixth optocoupler, a fourth resistor, a fifth resistor, a twelfth resistor, a thirteenth resistor, a seventh capacitor and an eighth capacitor;

The 1 st pin and the 2 nd pin of the hand wheel interface input a fifth voltage, and the 9 th pin and the 10 th pin of the hand wheel interface are connected with an isolated ground; the 3 rd leg, the 4 th leg, the 5 th leg and the 6 th leg of the hand wheel interface are connected with the 1 st leg, the 3 rd leg, the 5 th leg and the 7 th leg of the third optocoupler one to one; 11 th, 12 th, 13 th, 7 th and 3 rd, 5 th, 7 th, 1 st of the hand wheel interface are connected one-to-one; the 14 th pin and the 15 th pin of the hand wheel interface are connected with the 1 st pin and the 4 th pin of the sixth optocoupler one by one; the 8 th pin of the hand wheel interface J1 is connected with the E pin of the fifth optocoupler; the 2 nd, 4 th, 6 th and 8 th pins of the third optocoupler are respectively grounded and isolated through an indicator lamp; the 2 nd, 4 th, 6 th and 8 th pins of the fourth optocoupler are respectively grounded and isolated through an indicator lamp; the 16 th pin, the 14 th pin, the 12 th pin and the 10 th pin of the third optocoupler are connected with the 1 st pin, the 2 nd pin, the 3 rd pin and the 4 th pin of the fourth resistor one to one; the fourth pin of the third optocoupler is connected with the fourth pin of the fourth resistor and the A1 pin of the logic chip in the ninth decoding unit, the fourth pin of the third optocoupler is connected with the 2 pin of the fourth resistor and the A2 pin of the logic chip in the ninth decoding unit, the fourth pin of the third optocoupler is connected with the 3 pin of the fourth resistor and the A3 pin of the logic chip in the ninth decoding unit, the 10 pin of the third optocoupler is connected with the 4 pin of the fourth resistor and the A4 pin of the logic chip in the ninth decoding unit, the 16 pin of the fourth optocoupler is connected with the 1 pin of the fifth resistor and the A5 pin of the logic chip in the ninth decoding unit, the 14 pin of the fourth optocoupler is connected with the 2 pin of the fifth resistor and the A6 pin of the logic chip in the ninth decoding unit, the 12 pin of the fourth optocoupler is connected with the 3 pin of the fifth resistor and the A7 pin of the logic chip in the ninth decoding unit, and the 10 pin of the fourth optocoupler is connected with the fourth pin of the fourth resistor and the A8 pin of the fourth decoding unit, and the fourth voltage is input to the fourth resistor and the fourth resistor is 8; the 15 th pin, the 13 th pin, the 11 th pin and the 9 th pin of the third optocoupler and the fourth optocoupler are all connected with digital ground; the C pin of the fifth optocoupler inputs a fifth voltage, the A pin of the fifth optocoupler inputs a fourth voltage, the K pin of the fifth optocoupler is connected with the PD13 pin of the main control chip, and the 1 st pin of the sixth optocoupler is connected with one end of the seventh capacitor and one end of the thirteenth resistor; the 2 nd pin of the sixth optocoupler is connected with the other end of the seventh capacitor, the other end of the thirteenth resistor and shielding ground; the 4 th pin of the sixth optocoupler is connected with one end of the eighth capacitor and one end of the twelfth resistor; the 3 rd pin of the sixth optical coupler is connected with the other end of the eighth capacitor, the other end of the twelfth resistor and shielding ground, the 8 th pin of the sixth optical coupler inputs fourth voltage, and the 7 th pin and the 6 th pin of the sixth optical coupler are connected with the PA0-WKUP pin and the PA1 pin of the main control chip one by one; the 5 th pin of the sixth optocoupler is connected with digital ground.

In the digital and PWM composite controller, the PWM output module comprises an output voltage isolation chip, a second driving chip, a third driving chip, a fourth driving chip, a serial port, a first transient state suppressor, a second transient state suppressor, a fourteenth resistor and a fifteenth resistor;

the VCC1 pin of the output voltage isolation chip inputs a fourth voltage, the INA pin of the output voltage isolation chip is connected with one end of a fourteenth resistor and the PD15 pin of the main control chip, and the INB pin of the output voltage isolation chip is connected with one end of the fifteenth resistor and the PA8 pin of the main control chip; the GND1 pin of the output voltage isolation chip is connected with the other end of the fourteenth resistor, the other end of the fifteenth resistor and digital ground; the VCC2 pin of the output voltage isolation chip inputs a sixth voltage, the GND2 pin of the output voltage isolation chip is connected with an isolated ground, the OUTA pin of the output voltage isolation chip is connected with the INA pin of the second driving chip and the IN+ pin of the fourth driving chip, and the OUTB pin of the output voltage isolation chip is connected with the INB pin of the second driving chip and the IN+ pin of the third driving chip; the ENA pin, the ENB pin and the VDD pin of the second driving chip are all input with a sixth voltage; the GND pin of the second driving chip is connected with the isolated ground, the OUTA pin of the second driving chip is connected with the 2 nd pin of the first transient suppressor and the 4 th pin of the serial port, the OUTB pin of the second driving chip is connected with the 1 st pin of the first transient suppressor and the 5 th pin of the serial port, the EN pins of the third driving chip and the fourth driving chip are all input with sixth voltage, the GND pins of the third driving chip and the fourth driving chip are all connected with the isolated ground, the VDD pins of the third driving chip and the fourth driving chip are all input with fifth voltage, the OUT pin of the third driving chip is connected with the 2 nd pin of the second transient suppressor and the 1 st pin of the serial port, and the OUT pin of the fourth driving chip is connected with the 1 st pin of the second transient suppressor and the 2 nd pin of the serial port; the 3 rd pin of the first transient suppressor, the 3 rd pin of the second transient suppressor, the 6 th pin, the 7 th pin, the 3 rd pin, the 8 th pin and the 9 th pin of the serial port are all connected with an isolation ground; the shell of the serial port is connected with shielding ground.

In the digital and PWM composite controller, the communication module comprises a communication chip, a first ESD protection tube, a second ESD protection tube, a first network port, a second network port, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a twelfth capacitor;

The OE_EXT/LRDn/SCLK pin, OUTVLD/LWRn/MOSI pin, SOF/LECSn/SCS_ESC pin, WD_TRIG/LINT/SINT pin, SYNC_LATCH [0] pin, SYNC_LATCH [1] pin, LAT_IN/LRDY/MISO pin, EEP_DONE pin are connected with PA5 pin, PA7 pin, PA4 pin, AP2 pin, PC8 pin, PC9 pin, AP6 pin and PA3 pin of the main control chip IN a one-to-one manner; the P0-TXOP pin of the communication chip is connected with the TD+ pin of the first network port and the IO2 pin of the first ESD protection tube, the P0-TXON pin of the communication chip is connected with the TD-pin of the first network port and the IO3 pin of the first ESD protection tube, the P0-RXIP pin of the communication chip is connected with the RD+ pin of the first network port and the IO4 pin of the first ESD protection tube, the P0-RXIN pin of the communication chip is connected with the RD-pin of the first network port and the IO1 pin of the first ESD protection tube, the P0-ACT pin of the communication chip is connected with the LED 2-yellow+ pin of the first network port, the TDC pin of the first network port sequentially passes through a sixteenth resistor and a ninth capacitor to be connected with digital ground, the RDC pin of the first network port sequentially passes through a seventeenth resistor and the tenth capacitor to be connected with digital ground, the P1-TXpin of the communication chip is connected with the RD 2 pin of the first ESD protection tube, the P1-TXON pin of the communication chip is connected with the TD-pin of the second network port and the IO1 pin of the second ESD protection tube, the P1-pin of the communication chip is sequentially connected with the P1-pin of the first ESD protection tube through the LED 2-yellow+ pin of the second network port and the first capacitor to be sequentially connected with the RDC 1 of the first capacitor to be connected with the RDC 1 of the first capacitor.

Compared with the prior art, the digital and PWM composite controller provided by the invention comprises a shell, wherein a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module; the analog quantity transmission module carries out analog-to-digital conversion on an analog quantity signal input from the outside, then transmits the analog quantity signal to the control module for processing, monitors the signal transmission state and feeds the signal back to the control module through the coding and decoding module; the analog output signal output by the control module is output after digital-to-analog conversion by the analog transmission module; the digital quantity transmission module isolates the digital quantity signals input from the outside and transmits the signals to the control module for processing through the encoding and decoding module; the digital quantity output signal output by the control module is transmitted to the analog quantity transmission module through the coding and decoding module, and the analog quantity transmission module is isolated and then output; the coding and decoding module is used for expanding the interface of the control module and transmitting signals; the hand wheel processing module transmits hand wheel data to the control module through the coding and decoding module, isolates hand wheel signals and transmits the hand wheel signals to the control module, and also isolates hand wheel control signals output by the control module and outputs the hand wheel control signals; the PWM output module is used for isolating, converting voltage and outputting corresponding PWM signals after driving the PWM control signals output by the control module; the communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer. The digital quantity input and output, the analog quantity input and output and the PWM output module are integrated together, and compared with the existing various functional separated design modules, the connecting lines among the modules are realized by the layout of a circuit board, so that the trouble of wiring and the external interference during signal transmission are greatly reduced.

Drawings

Fig. 1 is a block diagram of a digital and PWM composite controller according to the present invention.

Fig. 2 is a circuit diagram of an analog input unit provided by the present invention.

Fig. 3 is a circuit diagram of a portion of an analog output unit according to the present invention.

Fig. 4 is a circuit diagram of another part of the analog output unit provided by the present invention.

Fig. 5 is a circuit diagram of a portion of a digital quantity transmission module provided by the present invention.

Fig. 6 is a circuit diagram of another part of the digital quantity transmission module provided by the invention.

Fig. 7 is a circuit diagram of a first digital input unit according to the present invention.

Fig. 8 is a circuit diagram of a first digital quantity output unit provided by the present invention.

Fig. 9 is a circuit diagram of a monitoring feedback unit provided by the invention.

Fig. 10 is a circuit diagram of a control module provided by the present invention.

Fig. 11 is a block diagram of 9 decoding units according to the present invention.

Fig. 12 is a block diagram of the structure of 4 latch units according to the present invention.

Fig. 13 is a circuit diagram of a first decoding unit according to the present invention.

Fig. 14 is a circuit diagram of a seventh decoding unit according to the present invention.

Fig. 15 is a circuit diagram of an eighth decoding unit according to the present invention.

Fig. 16 is a circuit diagram of a ninth decoding unit according to the present invention.

Fig. 17 is a circuit diagram of a first latch unit according to the present invention.

Fig. 18 is a circuit diagram of a portion of a handwheel processing module provided by the present invention.

Fig. 19 is a circuit diagram of another portion of a handwheel processing module provided by the present invention.

Fig. 20 is a circuit diagram of a PWM output module provided by the present invention.

Fig. 21 is a circuit diagram of a first portion of a communication module according to the present invention.

Fig. 22 is a circuit diagram of a second portion of the communication module according to the present invention.

Fig. 23 is a circuit diagram of a third portion of the communication module according to the present invention.

Detailed Description

The invention provides a digital and PWM composite controller. In order to make the objects, technical solutions and effects of the present invention clearer and more specific, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, a digital and PWM composite controller (having a housing with a circuit board therein) provided in an embodiment of the present invention is disposed on a machine tool and communicates with a CNC system on an upper computer; the circuit board integrates an analog quantity transmission module 10, a digital quantity transmission module 20, a control module 30, a coding and decoding module 40, a hand wheel processing module 50, a PWM output module 60 and a communication module 70. The control module 30 is connected with the analog quantity transmission module 10, the coding and decoding module 40, the hand wheel processing module 50, the PWM output module 60 and the communication module 70; the coding and decoding module 40 is connected with the hand wheel processing module 50, the analog quantity transmission module 10 and the digital quantity transmission module 20.

The analog quantity transmission module 10 performs analog-to-digital conversion on an externally input analog quantity signal, transmits the analog quantity signal to the control module 30 (the processing mode is the prior art), monitors the signal transmission state (whether short circuit, overload or overheat occurs, DACSTAT [1..4] signals are transmitted) and feeds back the signal to the control module 30 through the encoding and decoding module; the control module 30 controls the voltage (e.g. 0-10 v) of the analog output signal to be output, and outputs and controls the working state (e.g. height, gas size, proportional valve, rotation speed of motor, energy of laser, etc.) of the connected equipment after digital-to-analog conversion by the analog transmission module 10.

The digital quantity transmission module 20 isolates the externally input digital quantity signal (24V), and then transmits the isolated digital quantity signal to the control module 30 for processing (the processing mode is the prior art); the control module 30 transmits the digital quantity output signal db_ [0..7] to be output to the analog quantity transmission module 10 through the coding and decoding module, and outputs and controls the working state (such as the on-off of a relay) of the connected equipment after isolation.

The codec module 40 is used for expanding the interface of the control module 30 and performing parallel port communication.

The hand wheel processing module 50 transmits hand wheel data input from the outside to the control module 30 through the coding and decoding module 40, and transmits the hand wheel signal to the control module 30 after isolating, and also outputs the hand wheel control signal output from the control module 30 after isolating.

The PWM output module 60 isolates the PWM control signals (FOUT signal and PWM signal) output from the control module 30, converts the voltage, and outputs corresponding PWM signals (FOUT 5V signal, FOUT24V signal, PWM5V signal and PWM24V signal) after driving.

The communication module 70 is externally connected with an upper computer, and is used for realizing the data link layer communication between the control module 30 and the upper computer.

In specific implementation, for example, the distances between a cutting head on a machine tool and a steel plate to be cut are different, the generated voltages are also different (the voltage ranges are 0-10V), the voltage fed back by the cutting head (such as 5V) is an analog signal, the analog signal is transmitted to the control module 30 for processing after being subjected to analog-to-digital conversion by the analog transmission module 10, the control module 30 uploads a voltage value to a CNC system on an upper computer through the communication module 70, the CNC system can judge whether the current distance is proper (too high cutting cannot be achieved and too low steel plate burning can be caused) according to the voltage value, the CNC system outputs the height value of a shaft to be adjusted according to the distance, the height value is transmitted to the control module 30 through the communication module 70, and the control module 30 transmits the height value to the analog transmission module 10 for digital-to-analog conversion and then outputs the corresponding height voltage to the shaft, so that the height of the shaft can be adjusted.

The digital quantity signal is similar to the analog quantity signal, except that the input path sequentially passes through the digital quantity transmission module 20, the coding and decoding module 40 and the control module 30 and then passes through the communication module 70, and is uploaded to the upper computer for processing through the EtherCAT bus; the output path is opposite to the input path. The digital quantity signal is used to implement other controls, such as all switches being controlled by the digital quantity signal.

The input and output of the analog quantity transmission module 10, the digital quantity transmission module 20, the hand wheel processing module 50, the PWM output module 60 and the communication module 70 are not sequential, and each module can work as long as signals are externally or are required to be output.

In this embodiment, various functions are integrated on a circuit board, and the modules are connected by wires on the circuit board, as compared with the existing separate and independent designs of the modules. One integrated module can completely solve all application scenes without redundant control modules; the connecting wires required by connection between the independent modules are omitted, the trouble of wiring and external interference during signal transmission are greatly reduced, and the anti-interference performance is improved while the cost is saved.

Referring to fig. 2, the analog transmission module 10 includes an analog input unit 110 and an analog output unit 120; the analog input unit 110 is connected to the analog output unit 120 and the control module 30, and the analog output unit 120 is connected to the codec module 40. The analog input unit filters, amplifies and analog-to-digital converts an externally input analog signal and transmits the externally input analog signal to the control module; the analog output unit monitors the signal transmission state and feeds the signal transmission state back to the control module through the coding and decoding module; the analog output signal output by the control module is output after digital-to-analog conversion through the analog output unit.

It will be appreciated that in each circuit diagram, triangles represent sequentially shortened lines of analog ground representing digital ground, with EARTH reference numerals representing shielded ground (connection housing), and 0V reference numerals representing 24V isolated ground.

In this embodiment, the analog input unit 110 includes a first interface P1, an analog input chip U1 with a model of ADS8664IDBT, a first operational amplifier circuit 111, a second operational amplifier circuit 112, a third operational amplifier circuit 113, and a fourth operational amplifier circuit 114; the 1 st pin and the 2 nd pin of the first interface P1 are connected with the first input pin and the second input pin of the first operational amplifier circuit 111 one to one; the 3 rd pin and the 4 th pin of the first interface P1 are connected with the first input pin and the second input pin of the second operational amplifier circuit 112 one to one; the 5 th pin and the 6 th pin of the first interface P1 are connected with the first input pin and the second input pin of the third operational amplifier circuit 113 one to one; the 7 th pin and the 8 th pin of the first interface P1 are connected with the first input pin and the second input pin of the fourth operational amplifier 114 one to one; pin 9 of the first interface P1 connects pin 10 and the shielding ground (all EARTH in this embodiment denote shielding ground); the first output pin and the second output pin of the first operational amplifier circuit 111 are connected with the AIN_0P pin and the AIN_0GND pin of the analog input chip U1 one to one; the first output pin and the second output pin of the second operational amplifier circuit 112 are connected with the AIN_1P pin and the AIN_1GND pin of the analog input chip U1 one by one; the first output pin and the second output pin of the third operational amplifier circuit 113 are connected with the ain_2p pin and the ain_2gnd pin of the analog input chip U1 one to one; the first output pin and the second output pin of the fourth operational amplifier circuit 114 are connected with the ain_3p pin and the ain_3gnd pin of the analog input chip U1 one to one; the AVDD pin of the analog input chip U1 inputs a first voltage +5v (connected to the first power supply terminal, the AVDD pin may be grounded through two capacitors connected IN parallel during implementation, the capacitors filter the input first voltage +5v), the DVDD pin of the analog input chip U1 inputs a second voltage +3v3_ad (connected to the second power supply terminal, the DVDD pin may be grounded through two capacitors connected IN parallel during implementation, the capacitors filter the second voltage +3v3_ad), and the aux_in pin of the analog input chip U1 is connected (may be connected through a resistor) to the aux_gnd pin and to an analog ground (triangle symbol represents an analog ground); the REFIO pin and the REFCAP pin of the analog input chip U1 are respectively connected with analog ground through a capacitor; analog input chip U1Foot,/>The feet and the ALARM feet are connected with the control module 30; the SCLK pin, the SDI pin and the SDO pin of the analog input chip U1 are connected with the analog output unit 120 and the control module 30; RDFGND pins of an analog input chip U1,Foot, AGND foot, DA/SY foot, DGND foot are all grounded.

The first interface P1 transmits 4 analog signals (a first analog signal AIN0±, a second analog signal AIN1±, a third analog signal AIN2±and a fourth analog signal AIN3±) input from the outside to corresponding op-amp circuits, each op-amp circuit filters and amplifies the analog signals of the corresponding channel and outputs the filtered and amplified analog signals to a 4-channel analog input chip U1 with the precision of 12 bits, the voltage range of the 4 analog is 0V to +10v, the analog input chip U1 can directly bear the voltage of 10V and directly input, a middle high-precision operational amplifier is saved, and the SPI interface is provided, so that the analog input chip U1 can directly communicate with a master control chip in the control module 30.

The functions and circuit structures of each operational amplifier circuit are the same, but the input and output signals are different, and here, the first operational amplifier circuit 111 is taken as an example, and comprises a first operational amplifier M1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first protection diode DS1, a first capacitor C1 and a second capacitor C2; one end of the first resistor R1 (i.e., the first input pin of the first op-amp circuit 111 is connected to the 1 st pin of the first interface P1) is connected to one end of the second resistor R2, and the other end of the first resistor R1 (i.e., the second input pin of the first op-amp circuit 111 is connected to the 2 nd pin of the first interface P1) is connected to one end of the third resistor R3; the other end of the second resistor R2 is connected with one end of the first capacitor C1, one end of the first protection diode DS1 and the non-inverting input pin of the first operational amplifier; the other end of the third resistor R3 (i.e., the second output pin of the first operational amplifier circuit 111) is connected to the other end of the first capacitor C1, the other end of the first protection diode DS1, and the ain_0gnd pin of the analog input chip U1; the inverting input pin of the first operational amplifier is connected with the output pin of the first operational amplifier and one end of a fourth resistor R4, the other end of the fourth resistor R4 (namely the first output pin of the first operational amplifier circuit 111) is connected with one end of a second capacitor C2 and an AIN_0P pin of an analog input chip U1, and the other end of the second capacitor C2 is grounded.

The first resistor R1 is used for providing a voltage bit, R2, R3 and C1 form a pi-type filter circuit, the first protection diode DS1 is used for protecting an operational amplifier, and R4 and C2 form an RC filter circuit. It should be understood that in the implementation, a four-operational amplifier chip with a model LM224 may be used, and four operational amplifiers are integrated therein, so that the operational amplifier in each operational amplifier circuit may be replaced, and the integration level of the circuit is further improved. As shown in fig. 2, the letter A, B, C, D in each op-amp represents four op-amps in the four op-amp chip, and pins 1-14 at the periphery of the four op-amps are pins of the four op-amp chip.

Referring to fig. 3 and 4 together, the analog output unit 120 includes a second interface P2, an analog output chip U2 with a model of AD5724R, a fifth resistor R5, a sixth resistor R6, a first output circuit (consisting of two parts, respectively numbered 121_1 and 121_2), a second output circuit (consisting of two parts, respectively numbered 122_1 and 122_2), a third output circuit (consisting of two parts, respectively numbered 123_1 and 123_2), and a fourth output circuit (consisting of two parts, respectively numbered 124_1 and 124_2); the DVcc pin of the analog output chip U2 inputs a third voltage +3V3_DAC (connected with a third power supply end), and the analog output chip U2The foot is connected with digital ground; analog output chip U2/>A foot part,Foot and/>The feet are connected with the control module 30; the SCLK pin of the analog output chip U2 is connected with the SCLK pin of the analog input chip U1 and the control module 30, the SDIN pin of the analog output chip U2 is connected with the SDI pin of the analog input chip U1 and the control module 30, the SDO pin of the analog output chip U2 is connected with the SDO pin of the analog input chip U1 and the control module 30, the REFIN/REFOUT pin of the analog output chip U2 is connected with the GND pin of the analog output chip U2 and the digital ground through a capacitor, and the AVdd pin of the analog output chip U2 inputs the first voltage +5V; the VoutA pin, the VoutB pin, the VoutC pin and the VoutD pin of the analog output chip U2 are connected with the first input pin of the first output circuit, the first input pin of the second output circuit, the first input pin of the third output circuit and the first input pin of the fourth output circuit one by one; the AVss pin, the SIG_GND pin, the DAC_GND pin and the EPAD pin of the analog quantity output chip U2 are all connected with an analog ground; the first output pin and the second output pin of the first output circuit are connected with the 10 th pin and the 9 th pin of the second interface P2 one by one; the first output pin and the second output pin of the second output circuit are connected with the 8 th pin and the 7 th pin of the second interface P2 one by one; the first output pin and the second output pin of the third output circuit are connected with the 6 th pin and the 5 th pin of the second interface P2 one by one; the first output pin and the second output pin of the fourth output circuit are connected with the 4 th pin and the 3 rd pin of the second interface P2 one by one; the 1 st pin of the second interface P2 is connected with the 2 nd pin and shielding ground, and the third output pins of the first output circuit to the fourth output circuit are connected with the encoding and decoding module 40; one end of the fifth resistor R5 is input with the first voltage +5V, the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the second input pin of each output circuit, and the other end of the sixth resistor R6 is connected with analog ground.

The voltage range of the analog output unit 120 is 0 v-10 v, and the SPI signal (including the SPI2_sclk signal, the SPI2_ MOSIO signal, and the SPI2_miso signal) is directly connected to and communicated with the main control chip in the control module 30, where the data in the SPI signal is used to control the output state of the analog output chip U2, for example, which of the VoutA pins to VoutD pins outputs, and whether several paths of signals are output simultaneously or one path of signals.The signal is a serial interface frame synchronous signal, the falling edge of the signal is used for data transmission, and the rising edge is used for data locking; /(I)The signal is used to select whether to update the analog output or latch control if during the write cycle/>The signal remains high, the input of the DAC register is updated, but at/>The output is not updated before the falling edge of the signal, all analog outputs can be at/>Updating the falling edge of the signal simultaneously; /(I)The signal is used to set the DAC register built in the analog output chip U2 to a zero level code or an intermediate level code. The second interface P2 is an output terminal, and equipment needing analog quantity signals, such as a proportional valve, laser power control and the like, can be connected to the outside; the output analog quantity signals (DA_OUT1+/-, DA_OUT4+/-) are used for controlling the working states of the devices.

The function and circuit structure of each output circuit are the same, but the input and output signals are different, and the first output circuit is taken as an example here and comprises a second operational amplifier M2, a third operational amplifier M3, a first common-mode inductor L1, a seventh resistor R7 and a first switching tube Q1 (NMOS tube); the in-phase input pin of the second op-amp M2 (i.e., the first input pin of the first output circuit) is connected to the VoutA pin of the analog output chip U2, the inverting input pin of the second op-amp M2 is connected to the output pin of the second op-amp M2 and the 1 st pin of the first common-mode inductor, the 2 nd pin of the first common-mode inductor (i.e., the first output pin of the first output circuit) is connected to the 10 th pin of the second interface P2, the 3 rd pin of the first common-mode inductor is grounded, the 4 th pin of the first common-mode inductor (i.e., the second output pin of the first output circuit) is connected to the 9 th pin of the second interface P2, the output pin of the second op-amp M2 is connected to the inverting input pin of the third op-amp M3, the in-amp M3 (i.e., the second input pin of the first output circuit) is connected to the other end of the fifth resistor R5, the output pin of the third op-amp M3 is connected to one end of the seventh resistor R7 and the gate of the first switch tube Q1, the other end of the seventh resistor R7 is connected to the gate of the first switch tube Q1, and the other end of the seventh resistor V7 is connected to the first switch tube Q1, and the drain of the first switch 40 is connected to the first amplifier 40 (i.e.e., the first amplifier 40).

The second operational amplifier M2 plays an isolating role, and is used for preventing the analog output chip U2 from being burned out, and increasing the driving capability. The circuit in fig. 4 is used for monitoring whether the analog signal has output, the divided voltages of R5 and R6 provide a fixed reference level, when the analog output chip U2 does not output or outputs a low level (at this time, the voltage of the dig_da1 signal is 0v to 0.5 v), the third op amp M3 (comparator) outputs a high level to control Q1 to be turned on, the DACSTAT signal is a low level, and the signal is fed back to the main control chip through the codec module. When the analog signal is output (at this time, the voltage of the dig_da1 signal is greater than 0.5V and less than or equal to 10V), the third operational amplifier M3 outputs a low level, Q1 is turned off, and DACSTAT signals are high. The main control chip can judge whether the analog quantity signals (DA_OUT1+/-, DA_OUT4+/-) are output or not according to the high level and the low level of DACSTAT [1..4] signals, and which way is output.

Referring to fig. 5 and 6 together, the digital quantity transmission module 20 includes a third interface P3, a fourth interface P4, a fifth interface P5, a sixth interface P6, a seventh interface P7, 48 digital quantity input units (a first digital quantity input unit to a forty-eight digital quantity input unit 48), 8 digital quantity output units (a first digital quantity output unit to an eighth digital quantity output unit), and a monitoring feedback unit; the 1 st pin of the third interface P3 is connected to the input pin of the first digital input unit, the 2 nd pin is connected to the input pin of the second digital input unit, and so on until the 15 th pin of the third interface P3 is connected to the input pin of the sixteenth digital input unit; similarly, each pin of the fourth interface P4 is correspondingly connected to the input pins of the seventeenth digital quantity input unit to the thirty-third digital quantity input unit, each pin of the fifth interface P5 is correspondingly connected to the input pins of the thirty-third digital quantity input unit to the forty-eighth digital quantity input unit, and the output pins of the digital quantity input units are all connected to the encoding and decoding module 40; each output pin of the first digital quantity output unit to the fourth digital quantity output unit is connected with a sixth interface P6, each output pin of the fifth digital quantity output unit to the eighth digital quantity output unit is connected with a seventh interface P7, and each input pin of the digital quantity output unit is connected with a coding and decoding module 40.

The functions and circuit structures of the digital quantity input units are the same, but the input and output signals are different, and herein, the first digital quantity input unit is taken as an example, please refer to fig. 7, which includes a first optocoupler A1, a first indicator light G1, an eighth resistor R8, a ninth resistor R9, a third capacitor C3 and a fourth capacitor C4; one end of the third capacitor C3 is connected to one end of the eighth resistor R8 and the 1 st pin of the first optocoupler A1 (i.e., the input pin of the first digital input unit), the other end of the third capacitor C3 is connected to the other end of the eighth resistor R8, the negative electrode of the first indicator lamp G1 and the isolated ground, the 2 nd pin of the first optocoupler A1 is connected to the positive electrode of the first indicator lamp G1, and the 3 rd pin of the first optocoupler A1 is connected to the digital ground; the 4 th pin (i.e. the output pin of the first digital input unit) of the first optocoupler A1 is connected to one end of the ninth resistor R9, one end of the fourth capacitor C4, and the codec module 40, and the other end of the ninth resistor R9 is input with the fourth voltage +3v3 (connected to the fourth power supply end), where the other end of the fourth capacitor C4 is grounded digitally.

The third to fifth interfaces P3 to P5 are 24V INPUT terminals connected to an external 24V voltage INPUT, and have 48 INPUTs (i.e., digital signal input_1..48 ]), and output corresponding input_cpu_1..48 signals after being isolated by each digital INPUT unit, and are transmitted to the main control chip through the encoding and decoding module. As shown in fig. 7, the first optocoupler A1 is used for isolating 3.3V from 24V, and when the input_1 signal is at a high level of 24V, the first indicator light G1 is turned on, the first optocoupler A1 is turned on, and the input_cpu_1 signal is at a low level. When the input_1 signal is at the low level 24V, the first indicator light G1 is turned off, the first optocoupler A1 is turned off, and the input_cpu_1 signal is pulled up to the high level by R9. The corresponding data is transmitted through the high-low level change of the input_1 signal.

In the implementation, in order to improve the integration level, a group of four digital quantity input units can be adopted, and a photoelectric coupler with the model of TCMT4100 is adopted, wherein 4 photoelectric couplers are integrated in the photoelectric coupler to replace the photoelectric coupler in each digital quantity input unit; similarly, the resistances of 4 output pins (corresponding to R9) in the four digital quantity input units may be replaced by resistors integrated with 4 resistances, and the capacitances of 4 output pins (corresponding to C4) may be replaced by capacitors integrated with 4 capacitances.

The digital quantity output units have the same functions and circuit structures, but the input and output signals are different, and herein, as an example, the first digital quantity output unit is taken as a reference to fig. 8, and the digital quantity output unit includes a first driving chip U3 with a model of preferably BTS716G, a second optocoupler A2 with a model of preferably TCMT4100, a first resistor RP1 (only 4 resistors are integrated together to reduce the volume of the PCB board and are not connected with each other), a second resistor RP2, a third resistor RP3 and a first capacitor CP1 (only 4 capacitors are integrated together to reduce the volume of the PCB board and are not connected with each other); the 1 st, 3 rd, 5th and 7th pins of the second optocoupler A2 are connected with the 4th, 3 rd, 2 nd and 1 st pins of the first resistor RP1 one to one; the 2 nd, 4th, 6 th and 8 th pins (i.e. the 4 input pins of the first digital output unit) of the second optocoupler A2 are all connected with the coding and decoding module 40; the 16 th, 14 th, 12 th and 10 th pins of the second optocoupler A2 are connected with the 1 st, 2 nd, 3 rd and 4th pins of the second resistor RP2 in a one-to-one manner; the 15 th pin of the second optocoupler A2 is connected with the 1 st pin of the third resistor RP3, the 1 st pin of the first capacitor CP1 and the IN1 pin of the first driving chip U3; the 13 th pin of the second optocoupler A2 is connected with the 2 nd pin of the third resistor RP3, the 2 nd pin of the first capacitor CP1 and the IN2 pin of the first driving chip U3; the 11 th pin of the second optocoupler A2 is connected to the 3 rd pin of the third resistor RP3, the 3 rd pin of the first capacitor CP1 and the IN3 pin of the first driving chip U3; the 9th pin of the second optocoupler A2 is connected to the 4th pin of the third resistor RP3, the 4th pin of the first capacitor CP1, and the IN4 pin of the first driving chip U3; the fourth voltage +3v.3 is input from the 5th to 8 th pins of the first resistor RP1, the fifth voltage +24v is input from the 5th to 8 th pins of the second resistor RP2 (connected to the fifth power supply terminal), the fifth voltage +24v is input from the VBB pin of the first driving chip U3 from the 5th to 8 th pins of the third resistor RP3 and from the 5th to 8 th pins of the first capacitor CP1 are grounded; the pin OUT1, the pin OUT2, the pin OUT3 and the pin OUT4 of the first driving chip U3 are connected with the 16 th pin, the 15 th pin, the 14 th pin and the 13 th pin of the sixth interface P6 one to one; the ST1/2 pin of the first driving chip U3 is connected with the ST2/4 pin and is connected with the monitoring feedback unit.

The main control chip outputs the digital signal to be output through the coding and decoding module, namely the O_CPU_ [1..32] signal, is isolated through the corresponding digital output unit, is driven by the first driving chip U3 (the high-side output first driving chip), and is output through the two output terminals of the sixth interface P6 and the seventh interface P7. When the o_cpu_1 signal OUTPUTs a low level and A2 is turned on, the signal of the IN1 interface of U3 is pulled up to a high level by a resistor IN RP3, and U3 OUTPUTs a digital value signal OUTPUT1 of 24V. When the o_cpu_1 signal OUTPUTs a high level and A2 is turned off, the voltage of the signal of the IN1 interface of U3 is changed to a low level by discharging the corresponding capacitor IN CP1 to the ground, and U3 OUTPUTs a digital quantity signal OUTPUT1 of a low level.

The circuit shown in fig. 9 is used for monitoring the OUTPUT of the digital quantity signal OUTPUT [1..32], when the OUTPUT is short-circuited or overloaded or the temperature is too high, the first driving chip U3 OUTPUTs a diag_signal with a high level, the corresponding optocoupler is turned on, and the nOUTATAT signal is pulled down to a low level; nOUTATAT [1..8] signals are fed back to the main control chip through the coding and decoding module, and the main control chip can realize short circuit, overload or over-temperature monitoring according to the high and low levels of the signals. The pins OUT1 to OUT4 of the first driving chip U3 are respectively connected with an indicator lamp, and the corresponding indicator lamp is lightened when the OUTPUT1-4 signals are transmitted, so that a user can know the current digital quantity OUTPUT conveniently.

Referring to fig. 10, the control module 30 includes a main control chip U4 (preferably a single chip microcomputer with a model of STM32F103 VC) and a recording interface JP; the PA0_WKUP pin, the PA1 pin and the PD13 pin of the main control chip U4 are all connected with the hand wheel processing module 50; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip U4 are all connected with the communication module 70; the PA8 pin and the PD15 pin of the main control chip U4 are both connected with the PWM output module 60; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip U4 are connected with the 2 nd pin, the 1 st pin, the 5 th pin and the 6 th pin of the burning interface JP one to one; PB8 pin, PB9 pin, PB12 pin and analog output chip U2 of main control chip U4Foot,/>Foot,/>The feet are connected one by one; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin, PE15 pin of main control chip U4 and/> of analog input chip U1Foot, ALARM foot, SCLK foot, SDO foot, SDI foot,/>The feet are connected one by one; the main control chip U4 is connected with the encoding and decoding module 40 from the PC0 pin to the PC7 pin, from the PD0 pin to the PD12 pin and from the PE5 pin.

The main control chip U4 is a main stream enhanced ARM Cortex-M3 MCU, and is internally provided with modules and functions of a CPU, motor control, USB, CAN and the like of 256 KB Flash, 48KB RAM and 72 MHz; the communication chip U11 in the communication module 70 communicates with DA and AD through SPI interface, and the digital input and output communicate through IO port. Among the signals, the ENCA signal is a hand wheel A phase signal input, the ENCB signal is a hand wheel B phase signal input, the signals are transmitted to the main control chip through the hand wheel processing module, and the signal processing is carried out by the timer coding module in the main control chip (the specific processing mode is the prior art). The SINT signal is an EtherCAT communication interrupt signal, the EEP_DONE signal is an XML file loading success signal, the SCS_ESC signal is an EtherCAT communication chip selection signal, the SCLK signal is a clock signal of an EtherCAT communication SPI, the SMISO signal is an input signal of the EtherCAT communication SPI, the SMOSI signal is an output signal of the EtherCAT communication SPI, the SYNC_L0 signal is an EtherCAT communication synchronous signal 0, and the SYNC_L1 signal is an EtherCAT communication synchronous signal 1; these signals constitute EtherCAT communication, which is communicated with the host computer through a communication chip (AX 58100) in the communication module 70. The PWM signal is output by the main control chip and used for realizing PWM control, and is used when the cutting is slow; the FOUT signal is a fast PWM output signal that is used when fast cutting is required. And UART1_TX signals (serial port communication output signals) and UART1_RX signals (serial port communication input signals) transmitted between the main control chip and the burning interface JP are used for printing data during debugging so as to conveniently observe various working states. The uC_ SWDIO signal (data input and output of SW interface) and the uC_SWCLK signal (clock signal of SW interface) transmitted between the main control chip and the programming interface JP are used for debugging, programming and simulating the program. The BOOT1 signal and the BOOT0 signal are input into a configuration pin of the main control chip and are used for determining where to start running a program after the singlechip is started. Output of main control chipSignal to configure DAC register built-in analog output chip U2,/>The signal is used to update the DAC register and thus the analog output,/>The signal is a serial interface frame sync signal, the ADC_CS signal is used for chip select,/>The signal is used for resetting, and the ADC_ALARM signal is an ALARM signal when the input analog quantity signal and the digital quantity signal are detected to be abnormal. The SPI2_SCLK signal is a clock signal of the communication bus SPI2, the SPI2_MISO signal is an input signal of the communication bus SPI2, the SPI2_MOSI signal is an output signal of the communication bus SPI2, the signals are used for SPI2 bus communication and are shared by the ADC and the DAC, and when the communication with which chip is needed, a control pin can be disabled. The DB_0-DB_7 signals are 8-bit parallel port bus communication signals, and can be input or output. The OE 0-OE 7 signals are enable signals, when the enable signals are low, the chips in the decoding units are enabled, and then the data on the DB_0-DB_7 interfaces are real-time data on the INPUT_CPU_1-INPUT_CPU_8; when not in use, the main control chip pulls the level of the corresponding OE signal high. The LE 0-LE 3 signals are latch control pins of the 74HC373 chip in the latch unit, output on the falling edge, latch on the rising edge, and update until the next data. The oe_do signal is an enable chip select signal of the output chip of the latch unit, when the main control chip controls the enable chip select signal to be at a low level, data on db_0 to db_7 are input to the 4 latch chips, and specifically, which chip is selected to output, and the data is updated by the LE0 to LE3 signals. The OUT_LED signal is used to control LED lamps to indicate the operational status of a product, such as standby, running, or malfunctioning.

Referring to fig. 11 and 12, the encoding and decoding module 40 includes 9 decoding units and 4 latch units, each of which is connected to the control module; the first decoding unit is connected with the digital quantity transmission module, and the seventh decoding unit is used for decoding the digital quantity signal input by the digital quantity transmission module and transmitting the digital quantity signal to the control module; the eighth decoding unit is connected with the analog quantity transmission module (specifically, the analog quantity output unit) and is used for decoding the monitoring signal output by the analog quantity transmission module and transmitting the monitoring signal to the control module; the ninth decoding unit is connected with the hand wheel processing module and is used for decoding the hand wheel data transmitted by the hand wheel processing module and transmitting the decoded hand wheel data to the control module; the first latch unit to the fourth latch unit are connected with the control module and the digital quantity transmission module and are used for latching the digital quantity output signals output by the control module and outputting the digital quantity output signals to the digital quantity transmission module.

The function and circuit structure of each decoding unit are the same, and only the input signals are different, the corresponding external pins are different, and here, taking the first decoding unit as an example, please refer to fig. 13, which includes a first logic chip U5 with a preferred model number NXP74HC244PW, a tenth resistor R10, and a fifth capacitor C5; the first logic chip U5Foot connection/>One end of the pin, a tenth resistor R10 and a PD0 pin of the main control chip U4; the other end of the tenth resistor R10 is input with a fourth voltage +3V.3, and the pin A1, the pin A2, the pin A3, the pin A4, the pin A5, the pin A6, the pin A7 and the pin A8 of the first logic chip U5 are connected with the output pin of the first digital quantity input unit (namely the 4 th pin of the internal optocoupler), the output pin of the second digital quantity input unit, the output pin of the third digital quantity input unit, the output pin of the fourth digital quantity input unit, the output pin of the fifth digital quantity input unit, the output pin of the sixth digital quantity input unit, the output pin of the seventh digital quantity input unit and the output pin of the eighth digital quantity input unit in a one-to-one manner; the VCC pin of the first logic chip U5 inputs a fourth voltage +3V3 and is also connected with digital ground through a fifth capacitor C5; the Y1 pin, the Y2 pin, the Y3 pin, the Y4 pin, the Y5 pin, the Y6 pin, the Y7 pin and the Y8 pin of the first logic chip U5 are connected with the PC0 pin, the PC1 pin, the PC2 pin, the PC3 pin, the PC4 pin, the PC5 pin, the PC6 pin and the PC7 pin of the main control chip U4 one to one.

The OE0-OE8 signal is used for selecting a chip to be communicated, namely when the OE0-OE8 signal is effective (such as low level), the A1 pin is communicated with the Y1 pin, and the signal on the A1 pin is transmitted to the Y1 pin; the A2 pin is communicated with the Y2 pin, signals on the A2 pin are transmitted to the Y2 pin, and so on.

The input signals of the seventh to ninth decoding units are different from those of the other decoding units, the specific circuit of the seventh decoding unit is shown in fig. 14, the specific circuit of the eighth decoding unit is shown in fig. 15, and the specific circuit of the ninth decoding unit is shown in fig. 16.

The functions and circuit structures of the latch units are the same, and only the output signals are different, and the corresponding external pins are different, and herein, the first latch unit is taken as an example, please refer to fig. 17, which includes a first latch chip (preferably a latch with a model of 74HC 373) U6, an eleventh resistor R11, a twelfth resistor R12, and a sixth capacitor C6; the first latch chip U6The pin is connected with one end of an eleventh resistor R11 and a PE5 pin of the main control chip U4, a fourth voltage +3V3 is input at the other end of the eleventh resistor R11, and a D0 pin, a D1 pin, a D2 pin, a D3 pin, a D4 pin, a D5 pin, a D6 pin and a D7 pin of the first latch chip U6 are connected with XX one to one; the VCC pin of the first latch chip U6 inputs a fourth voltage +3V3 and is also connected with digital ground through a sixth capacitor C6; the Q0 pin, the Q1 pin, the Q2 pin and the Q3 pin of the first latch chip U6 are connected with the 4 input pins (namely the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the second optocoupler A2) of the first digital quantity output unit one to one; the Q4 pin, the Q5 pin, the Q6 pin and the Q7 pin of the first latch chip U6 are connected with the 4 input pins of the first digital quantity output unit one by one; the LE pin of the first latch chip U6 is connected with the PD9 pin of the main control chip U4 and is also connected with the digital ground through a twelfth resistor R12.

When the master control chip controls the oe_do signal to be at a low level, the first latch chip U6 is selected and is in a latch state, and when the LE0 signal is valid (e.g., at a high level), the db_0 signal is output as a corresponding o_cpu_1 signal through the first latch chip U6, and other signals are similarly and correspondingly output, i.e., the D0 pin and the Q0 pin are connected and output, the D1 pin and the Q1 pin are connected and output, and so on. .

Referring to fig. 18 and 19 together, the hand wheel processing module 50 includes a hand wheel interface J1 (model TCMT4100 is preferred), a third optocoupler A3 and a fourth optocoupler A4 (model TCMT4100 is preferred), a fifth optocoupler A5 (HCPL-181 000E is preferred), a sixth optocoupler A6 (dual-channel high-speed optocoupler) of EL0631 (model EL0631 is preferred), a fourth resistor RP4, a fifth resistor RP5, a twelfth resistor R12, a thirteenth resistor R13, a seventh capacitor C7, and an eighth capacitor C8; the 1 st pin and the 2 nd pin of the hand wheel interface J1 input a fifth voltage +24V, and the 9 th pin and the 10 th pin of the hand wheel interface J1 are connected with an isolated ground; the 3 rd leg, the 4 th leg, the 5 th leg and the 6 th leg of the hand wheel interface J1 are connected with the 1 st leg, the 3 rd leg, the 5 th leg and the 7 th leg of the third optocoupler A3 one by one; 11 th, 12 th, 13 th, 7 th feet of the hand wheel interface J1 are connected with 3 rd, 5 th, 7 th and 1 st feet of the fourth optical coupler A4 one to one; the 14 th pin and the 15 th pin of the hand wheel interface J1 are connected with the 1 st pin and the 4 th pin of the sixth optocoupler A6 one by one; the 8 th pin of the hand wheel interface J1 is connected with the E pin of the fifth optocoupler A5; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the third optical coupler A3 are respectively grounded and isolated through an indicator lamp; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the fourth optical coupler A4 are respectively grounded and isolated through an indicator lamp; the 16 th, 14 th, 12 th, 10 th pins of the third optocoupler A3 are connected with the 1 st, 2 nd, 3 rd, 4 th pins of the fourth resistor RP4 one to one; the 16 th pin of the third optocoupler A3 is connected with the 1 st pin of the fourth resistor RP4 and the A1 pin of the logic chip in the ninth decoding unit, the 14 th pin of the third optocoupler A3 is connected with the 2 nd pin of the fourth resistor RP4 and the A2 pin of the logic chip in the ninth decoding unit, the 12 th pin of the third optocoupler A3 is connected with the 3 rd pin of the fourth resistor RP4 and the A3 pin of the logic chip in the ninth decoding unit, the 10 th pin of the third optocoupler A3 is connected with the 4 th pin of the fourth resistor RP4 and the A4 pin of the logic chip in the ninth decoding unit, the 16 th pin of the fourth optocoupler A4 is connected with the 1 st pin of the fifth resistor RP5 and the A5 pin of the logic chip in the ninth decoding unit, the 14 th pin of the fourth optocoupler A4 is connected with the 2 nd pin of the fifth resistor RP5 and the A6 pin of the logic chip in the ninth decoding unit, the 12 th pin of the fourth optocoupler A4 is connected with the 3 th pin of the fifth resistor RP5 and the A4 pin of the logic chip in the ninth decoding unit, and the fourth optocoupler A4 is connected with the voltage of the fourth resistor RP5 and the fifth resistor RP 8; the 15 th pin, the 13 th pin, the 11 th pin and the 9 th pin of the third optocoupler A3 and the fourth optocoupler A4 are all connected with digital ground; the C pin of the fifth optocoupler A5 inputs a fifth voltage +24V, the A pin of the fifth optocoupler A5 inputs a fourth voltage +3V3, the K pin of the fifth optocoupler A5 is connected with the PD13 pin of the main control chip U4, and the 1 st pin of the sixth optocoupler A6 is connected with one end of a seventh capacitor C7 and one end of a thirteenth resistor R13; the 2 nd pin of the sixth optocoupler A6 is connected with the other end of the seventh capacitor C7, the other end of the thirteenth resistor R13 and shielding ground; the 4 th pin of the sixth optocoupler A6 is connected with one end of the eighth capacitor C8 and one end of the twelfth resistor R12; the 3 rd pin of the sixth optical coupler A6 is connected with the other end of the eighth capacitor C8, the other end of the twelfth resistor R12 and shielding ground, the 8 th pin of the sixth optical coupler A6 inputs a fourth voltage +3V.3, and the 7 th pin and the 6 th pin of the sixth optical coupler A6 are connected with the PA0-WKUP pin and the PA1 pin of the main control chip U4 one to one; the 5 th pin of the sixth optocoupler A6 is connected with digital ground.

The hand wheel interface J1 plays an isolating role, and hand wheel data input by an external hand wheel are transmitted to a data processing unit in the main control chip for processing. In the hand wheel data, X, Y, Z, 4 and 5 represent that 5 axial selections can be provided, and X1, X10 and X100 correspond to the hand wheel multiplying power selection. A and B are corresponding to hand wheel signals expressed as A phase and B phase, and corresponding ENCA signals and ENCB signals are output after isolation through a sixth optocoupler A6. And a hand wheel control signal OUT_LED output by the main control chip is isolated by a fifth optocoupler A5 and then is output from a hand wheel interface J1.

It should be understood that other elements, such as resistors, capacitors, and indicator lamps connected to the 1 st to 8 th pins of the third and fourth optocouplers A3 and A4, are also included in the hand wheel processing module 50, and the structures and functions of the elements are the same as those of the corresponding elements in the first digital input unit, and the 7 th and 6 th pins of the sixth optocoupler A6 are connected to pull-up resistors, as shown in fig. 18 in detail.

Referring to fig. 20 together, the PWM output module 60 includes an output voltage isolation chip U7 with a model of preferably ISO7342C, a second driving chip U8 with a model of preferably UCC27524D, a third driving chip U9 with a model of preferably UCC27537DBVT, a fourth driving chip U10 with a model of preferably UCC27537DBVT, a serial port J2, a first transient suppressor D1 with a model of preferably PESD5V2S2UT, a second transient suppressor D2, a fourteenth resistor R14, and a fifteenth resistor R15; the VCC1 pin of the output voltage isolation chip U7 inputs a fourth voltage +3V.3, the INA pin of the output voltage isolation chip U7 is connected with one end of a fourteenth resistor R14 and the PD15 pin of the main control chip U4, and the INB pin of the output voltage isolation chip U7 is connected with one end of the fifteenth resistor R15 and the PA8 pin of the main control chip U4; the GND1 pin of the output voltage isolation chip U7 is connected with the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15 and digital ground; the VCC2 pin of the output voltage isolation chip U7 inputs a sixth voltage of 5V0 (is connected with a sixth power supply end), the GND2 pin of the output voltage isolation chip U7 is connected with an isolated ground, the OUTA pin of the output voltage isolation chip U7 is connected with the INA pin of the second driving chip U8 and the IN+ pin of the fourth driving chip U10, and the OUTB pin of the output voltage isolation chip U7 is connected with the INB pin of the second driving chip U8 and the IN+ pin of the third driving chip U9; the ENA pin, the ENB pin and the VDD pin of the second driving chip U8 are all input with a sixth voltage of 5V0; the GND pin of the second driving chip U8 is connected with the isolation ground, the OUTA pin of the second driving chip U8 is connected with the 2 nd pin (the cathode of one diode) of the first transient suppressor D1 and the 4 th pin of the serial port J2, the OUTB pin of the second driving chip U8 is connected with the 1 st pin (the cathode of the other diode) of the first transient suppressor D1 and the 5 th pin of the serial port J2, the EN pins of the third driving chip U9 and the fourth driving chip U10 are both input with the sixth voltage 5V0, the GND pins of the third driving chip U9 and the fourth driving chip U10 are both connected with the isolation ground, the VDD pin of the third driving chip U9 and the VDD pin of the fourth driving chip U10 are both input with the fifth voltage +24V, the OUT pin of the third driving chip U9 is connected with the 2 nd pin (the cathode of one diode) of the second transient suppressor D2 and the 1 st pin of the serial port J2, and the OUT pin of the fourth driving chip U10 is connected with the 1 th pin of the second transient suppressor D2 (the cathode of the other diode) and the serial port J2; the 3 rd pin (the positive poles of the two diodes) of the first transient suppressor D1 and the 3 rd pin of the second transient suppressor D2 are connected with an isolated ground through the 6 th pin, the 7 th pin, the 3 rd pin, the 8 th pin and the 9 th pin of the serial port J2; the housings (PE 1 and PE 2) of the serial port J2 are connected with shielding ground.

The FOUT signal and the PWM signal output by the main control chip are 3.3V signals, but actually require 5V and 24V, the FOUT signal and the PWM signal are isolated by the output voltage isolation chip U7, then the zFOUT V signal and the zPWM signal are output, the zFOUT signal is driven by the second driving chip U8, then the FOUT5V signal of 5V is output, the zFOUT signal is driven by the fourth driving chip U10, then the FOUT24V signal of 24V is output, the zPWM signal is driven by the second driving chip U8, then the PWM5V signal of 5V is output, the zPWM signal is driven by the third driving chip U9, then the PWM24V signal of 24V is output, and these signals are output to the external laser through the serial port J2, thus PWM control can be realized.

Preferably, the OUT pin of the third driving chip U9 can be grounded and isolated through a resistor and an indicator lamp in sequence, so that the indicator lamp is lightened when a PWM24V signal is output, and the observation is convenient; the OUT pin of the fourth driving chip U10 is also provided with a corresponding element.

Referring to fig. 21, 22 and 23, the communication module 70 includes a communication chip U11 with a model of AX58100, a first ESD protection tube U12 with a model of AZ1213-04S, a second ESD protection tube U13 (AZ 1213-04S), a first port HR1, a second port HR2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11 and a twelfth capacitor C12; the OE_EXT/LRDn/SCLK pin, OUTVLD/LWRn/MOSI pin, SOF/LECSn/SCS_ESC pin, WD_TRIG/LINT/SINT pin, SYNC_LATCH [0] pin, SYNC_LATCH [1] pin, LAT_IN/LRDY/MISO pin, EEP_DONE pin are connected with PA5 pin, PA7 pin, PA4 pin, AP2 pin, PC8 pin, PC9 pin, AP6 pin and PA3 pin of the main control chip U4 IN a one-to-one manner; the P0_TXOP pin of the communication chip U11 is connected with the TD+ pin of the first network port HR1 and the IO2 pin of the first ESD protection tube U12, the P0_ TXON pin of the communication chip U11 is connected with the TD-pin of the first network port HR1 and the IO3 pin of the first ESD protection tube U12, the P0_ RXIP pin of the communication chip U11 is connected with the RD+ pin of the first network port HR1 and the IO4 pin of the first ESD protection tube U12, the P0_ RXIN pin of the communication chip U11 is connected with the RD-pin of the first network port HR1 and the IO1 pin of the first ESD protection tube U12, the P0_ACT pin of the communication chip U11 is connected with the LED2_yellow+ pin of the first network port HR1, the TDC pin of the first network port HR1 is sequentially connected with digital ground through a sixteenth resistor R16 and a ninth capacitor C9, the RDC pin of the first network port HR1 is sequentially connected with digital ground through a seventeenth resistor R17 and a tenth capacitor C10, the P1_TXOP pin of the communication chip U11 is connected with the TD+ pin of the second network port HR2 and the IO2 pin of the first ESD protection tube U12, the P1_ TXON pin of the communication chip U11 is connected with the TD-pin of the second network port HR2 and the IO3 pin of the second ESD protection tube U13, the P1_ RXIP pin of the communication chip U11 is connected with the RD+ pin of the second network port HR2 and the IO4 pin of the second ESD protection tube U13, the P1_ RXIN pin of the communication chip U11 is connected with the RD-pin of the second network port HR2 and the IO1 pin of the second ESD protection tube U13, the P1_ACT pin of the communication chip U11 is connected with the LED2_yellow+ pin of the second network port HR2, the TDC pin of the second network port HR2 is sequentially connected with digital ground through a nineteenth resistor R18 and an eleventh capacitor C11, and the RDC pin of the second network port HR2 is sequentially connected with digital ground through a nineteenth resistor R19 and a twelfth capacitor C12.

The sixteenth resistor R16, the seventeenth resistor R17, the ninth capacitor C9 and the tenth capacitor C10 form an impedance matching circuit of the first network port HR 1; the eighteenth resistor R18, the nineteenth resistor R19, the eleventh capacitor C11 and the twelfth capacitor C12 form an impedance matching circuit of the second network port HR 2. The communication chip U11 is a 2/3 port EtherCAT slave station controller (ESC) integrating two fast Ethernet PHYs supporting 100Mbps full duplex operation and HP Auto-MDIX functionality. The communication chip U11 supports CANopen (CoE), TFTP (FoE), voE and other standard EtherCAT protocols, and is suitable for industrial automation, motor control, motion control, robots, digital signal I/O control, analog-to-digital converter (ADC)/digital-to-analog converter (DAC) converter control, sensor data acquisition and the like, and various real-time industrial control product applications. In this embodiment, the communication chip U11 provides a three-channel PWM controller or a step controller, an incremental/Hall encoder interface for closed loop control, a SPI MASTER interface for SPI device data acquisition and output, 32 digitally controlled I/Os suitable for industrial real-time I/O control applications, and an I/O watch to provide a monitor I/O status for proper handling to ensure product functional safety. Two kinds of Process Data Interfaces (PDI), a Local Bus interface and a SPI Slav serial interface are provided, and the communication chip U11 can be connected to an external traditional MCU/DSP industrial control machine through the interfaces so as to support EtherCAT function. The communication chip U11 has two memory spaces corresponding to ESC memory and Function register, respectively, and a designer can determine which memory space to access by selecting pins through the chip. The internal bridge automatically synchronizes the contents of the ESC memory and the function buffer according to the set synchronization conditions, and provides ETHERCAT MASTER functions (PWM, SPI Master, etc.) for remotely controlling AX 58100. The communication chip U11 reflects ESCs and application interrupt events in the interrupt state buffer and notifies the external MCU/DSP via a conditional or edge interrupt trigger mode to manage these ESCs and application interrupt events.

In summary, the digital and PWM composite controller provided by the present invention integrates 48 digital inputs, 32 digital outputs, 4 16 high-precision analog inputs, 4 12 high-precision PWM outputs of 24V and 5V, a digital IO hand wheel transceiver interface, an RS485 expansion interface, and an EtherCAT bus communication interface into one module, and compared with the existing various functional separate design modules, one module can completely solve all application scenarios without redundant control modules; the connecting wires among the modules are omitted, the trouble of connecting wires and external interference during signal transmission are greatly reduced, and the anti-interference performance is improved while the cost is saved.

The above-mentioned division of the functional modules is only for illustration, and in practical application, the above-mentioned functional allocation may be implemented by different functional modules according to need, that is, by dividing the functional allocation into different functional modules to implement all or part of the functions described above.

It will be understood that equivalents and modifications will occur to those skilled in the art in light of the present invention and their spirit, and all such modifications and substitutions are intended to be included within the scope of the present invention as defined in the following claims.

Claims

1. The digital and PWM composite controller comprises a shell, and is characterized in that a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module;

The communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer;

the analog quantity transmission module comprises an analog quantity input unit and an analog quantity output unit; the analog input unit is connected with the analog output unit and the control module, and the analog output unit is connected with the coding and decoding module;

The analog output unit monitors the signal transmission state and feeds the signal transmission state back to the control module through the coding and decoding module; the analog output signal output by the control module is output after digital-to-analog conversion through the analog output unit;

the analog input unit comprises a first interface, an analog input chip, a first operational amplifier circuit, a second operational amplifier circuit, a third operational amplifier circuit and a fourth operational amplifier circuit;

The 1 st pin and the 2 nd pin of the first interface are connected with the first input pin and the second input pin of the first operational amplifier circuit one by one; the 3 rd pin and the 4 th pin of the first interface are connected with the first input pin and the second input pin of the second operational amplifier circuit one by one; the 5 th pin and the 6 th pin of the first interface are connected with the first input pin and the second input pin of the third operational amplifier circuit one by one; the 7 th pin and the 8 th pin of the first interface are connected with the first input pin and the second input pin of the fourth operational amplifier circuit one by one; the 9 th pin of the first interface is connected with the 10 th pin and shielding ground; the first output pin and the second output pin of the first operational amplifier circuit are connected with the AIN_0P pin and the AIN_0GND pin of the analog input chip one by one; the first output pin and the second output pin of the second operational amplifier circuit are connected with the AIN_1P pin and the AIN_1GND pin of the analog input chip one by one; the first output pin and the second output pin of the third operational amplifier circuit 3 are connected with the AIN_2P pin and the AIN_2GND pin of the analog input chip one by one; the first output pin and the second output pin of the fourth operational amplifier circuit are connected with the AIN_3P pin and the AIN_3GND pin of the analog input chip one by one; the AVDD pin of the analog input chip inputs a first voltage, the DVDD pin of the analog input chip inputs a second voltage, and the AUX_IN pin of the analog input chip is connected with the AUX_GND pin and analog ground; the REFIO pin and the REFCAP pin of the analog input chip are respectively connected with analog ground through a capacitor; analog quantity input chip Foot,/>The feet and the ALARM feet are connected with the control module; the SCLK pin, the SDI pin and the SDO pin of the analog input chip are connected with the analog output unit and the control module; RDFGND pins of analog quantity input chip,/>The foot, the AGND foot, the DA/SY foot and the DGND foot are all grounded;

The first operational amplifier circuit comprises a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first protection diode, a first capacitor and a second capacitor; one end of the first resistor is connected with one end of the second resistor, and the other end of the first resistor is connected with one end of the third resistor; the other end of the second resistor is connected with one end of the first capacitor, one end of the first protection diode and the in-phase input pin of the first operational amplifier; the other end of the third resistor is connected with the other end of the first capacitor, the other end of the first protection diode and an AIN_0GND pin of the analog input chip; the inverting input pin of the first operational amplifier is connected with the output pin of the first operational amplifier and one end of a fourth resistor, the other end of the fourth resistor is connected with one end of a second capacitor and the AIN_0P pin of the analog input chip, and the other end of the second capacitor is grounded.

2. The digital and PWM hybrid controller according to claim 1, wherein the analog output unit includes a second interface, an analog output chip, a fifth resistor, a sixth resistor, a first output circuit, a second output circuit, a third output circuit, and a fourth output circuit;

3. The digital and PWM composite controller according to claim 2, wherein the digital quantity transmission module includes a third interface, a fourth interface, a fifth interface, a sixth interface, a seventh interface, 48 digital quantity input units, 8 digital quantity output units, and a monitoring feedback unit;

4. The digital and PWM hybrid controller according to claim 3, wherein the control module comprises a main control chip and a burn interface; the PA0_WKUP pin, the PA1 pin and the PD13 pin of the main control chip are all connected with a hand wheel processing module; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip are all connected with the communication module; the PA8 pin and the PD15 pin of the main control chip are both connected with the PWM output module; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip are connected with the 2 nd pin, the 1 st pin, the 5 th pin and the 6 th pin of the burning interface one to one; PB8 pin, PB9 pin, PB12 pin and analog output chip of main control chipFoot,/>Foot,/>The feet are connected one by one; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin, PE15 pin and analog input chip of main control chip/>Foot, ALARM foot, SCLK foot, SDO foot, SDI foot,/>The feet are connected one by one; and the PC0 pin to the PC7 pin, the PD0 pin to the PD12 pin and the PE5 pin of the main control chip are all connected with the coding and decoding module.

5. The digital and PWM hybrid controller according to claim 4, wherein the codec module includes 9 decoding units and 4 latch units; each decoding unit and each latch unit are connected with the control module;

6. The digital and PWM hybrid controller of claim 5, wherein the hand wheel processing module comprises a hand wheel interface, a third optocoupler, a fourth optocoupler, a fifth optocoupler, a sixth optocoupler, a fourth resistor, a fifth resistor, a twelfth resistor, a thirteenth resistor, a seventh capacitor, and an eighth capacitor;

7. The digital and PWM composite controller of claim 6, wherein the PWM output module comprises an output voltage isolation chip, a second drive chip, a third drive chip, a fourth drive chip, a serial port, a first transient suppressor, a second transient suppressor, a fourteenth resistor, and a fifteenth resistor;

8. The digital and PWM hybrid controller according to claim 7, wherein the communication module comprises a communication chip, a first ESD protection tube, a second ESD protection tube, a first net gape, a second net gape, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor;