CN108461472B - A kind of device and method being bonded configuration chip using lead frame - Google Patents
A kind of device and method being bonded configuration chip using lead frame Download PDFInfo
- Publication number
- CN108461472B CN108461472B CN201810271767.6A CN201810271767A CN108461472B CN 108461472 B CN108461472 B CN 108461472B CN 201810271767 A CN201810271767 A CN 201810271767A CN 108461472 B CN108461472 B CN 108461472B
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- Prior art keywords
- configuration
- chip
- hole
- lead frame
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
This application involves a kind of device and method for being bonded configuration chip using lead frame, the logic control circuit in configuration the bonding hole and chip interior that there is described device chip package to reserve, the configuration bonding hole and the logic control circuit are used cooperatively to configure chip functions, the application reasonably configures bonding hole, and it is adapted with chip functions, the function control and optimization pin configuration of chip can be greatly improved, and improves the utilization rate in bonding hole.
Description
[technical field]
The invention belongs to chip controls field, especially a kind of device and method for being bonded configuration chip using lead frame.
[background technique]
The production of integrated circuit generally comprises material preparation and processing, chip manufacturing, three big links of encapsulation.Wherein, core
Piece packaging technology mainly include be thinned, cutting-up, bonding die, baking-curing, cleaning, bonding, plastic packaging, the different processes such as rib cutting.Wherein
Bonding is the welding procedure that chip top electrode and metal lead wire frame are connected one to one.In recent years, chip package
The development speed of technology is gradually accelerated, and the continuous development and constantly bringing forth new ideas for packaging technology due to material technology simplify tradition
Packaging technology.The hanging lead key closing process such as bonding wire exactly realizes lead and welding after wire bonding
The separation of pin eliminates subsequent rib cutting process, realizes recycling for lead frame, save packaging cost.
Chip carrier of the lead frame as integrated circuit is that one kind is drawn by means of bonding material realization chip internal circuits
The electrical connection of outlet and outer pin, and the key structure part of electric loop is formed, it plays the bridge connected with outer lead
Beam effect requires to be basis important in electronics and information industry using lead frame in most semiconductor integrated blocks
Material.
Lead frame bonding is exactly a kind of technology that bonding hole (PAD) is connected with lead frame, but most of at present integrated
The lead frame of circuit package technique is linked together with the ground of printed circuit board (PCB).But there can be the bonding of redundancy
Hole, these bonding holes cannot be effectively used, and for the chip of an inch of land is an inch of gold, this is undoubtedly a kind of huge wave
Take.
[summary of the invention]
In order to solve the above problem in the prior art, configuration chip is bonded using lead frame the present invention provides a kind of
Device, it is characterised in that: the logic control circuit in configuration the bonding hole and chip interior that there is described device chip package to reserve,
The configuration bonding hole and the logic control circuit are used cooperatively to configure chip functions.It is described configuration bonding hole quantity be
N, n are natural number, the n times side that the configurable modes quantity of the configuration chip functions is 2.The configuration bonding hole and logic
Control circuit corresponds.The state for configuring bonding hole is to be bonded the lead frame company in hanging hole or bonding hole and ground connection
It connects.The logic control circuit circuit and trigger with are constituted, and the output end of circuit is cooperated to connect the input terminal of trigger,
The output end control cooperation circuit of trigger, the output end of the cooperation circuit are also used as the output end of logic control circuit.Institute
Cooperation circuit is stated to be made of pull-up resistor, PMOS switch pipe, configuration bonding hole (ConfigPad), phase inverter (INV_1), wherein
PMOS controls its on or off by the output end of trigger, and the output end of PMOS and the input terminal in configuration bonding hole are connected to
The input terminal of phase inverter, the output end of the phase inverter are the output end for cooperating circuit.The logic control circuit output " 0 ",
" 1 " two states.The trigger is the trigger with latch function.The configuration mode is that chip selects analog-digital converter
Resolution ratio and conversion speed or chip selection different capabilities embedded memory or chip selection friction speed running frequency.
And further disclose a kind of method for being bonded configuration chip using lead frame, the configuration reserved using chip package
The logic control circuit for being bonded hole and chip interior configures chip functions.The state in configuration bonding hole be bonding hole it is hanging or
Person is bonded hole and the lead frame of ground connection connects.When bonding hole is hanging, cooperate the output end output logic signal " 0 " of circuit, and
It is latched by trigger, the output end of trigger will be kept output low level, control PMOS conducting；It is connect when bonding hole is connected to
When the lead frame on ground, cooperate the output end output logic signal " 1 " of circuit, and latched by trigger, the output end of trigger will
It is kept output high level, control PMOS shutdown.The quantity in configuration bonding hole is n, and n is natural number, with the grouping key
It closes the one-to-one logic control circuit in hole and generates " 1 ", " 0 " two states, by the output of n logic control circuit through decoder
The configurable modes of the configurable chip functions in n times side of output 2 afterwards.
The application reasonably configures bonding hole, and is adapted with chip functions, can greatly improve the function of chip
It can control and optimize pin configuration, and improve the utilization rate in bonding hole.
[Detailed description of the invention]
Described herein the drawings are intended to provide a further understanding of the invention, constitutes part of this application, but
It does not constitute improper limitations of the present invention, in the accompanying drawings:
Fig. 1 is the configuration relation figure for being bonded hole (PAD) and lead frame
Fig. 2 is the internal logic control circuits figure for being bonded hole (PAD) configuration chip
Fig. 3 is the use schematic diagram for configuring signal
[specific embodiment]
Come that the present invention will be described in detail below in conjunction with attached drawing and specific embodiment, illustrative examples therein and says
It is bright to be only used to explain the present invention but not as a limitation of the invention.
As shown in Figure 1, there are several chip bonding holes (PAD) on chip, it is most of to be attached structure with lead frame
It is bonded at lead frame, but has reserved 6 for configuring the bonding hole (PAD) used, this 6 for configuring the bonding hole used in chip
Can be there are two types of state, one is bonding hole is hanging when encapsulation, another kind is the lead frame connection for being bonded hole and ground connection.In Fig. 1
Middle bonding hole 1-3 be it is hanging, bonding hole 4-6 be bonded to grounding lead wire frame.
In conjunction with attached drawing 2 to how by bonding hole generate configuration chip functions logical signal be described in detail, in Fig. 2
In, for being bonded the configuration in hole 1, DFFR_1 is trigger, clock terminal ck and clock signal of system SYSTEM_CLK phase
Even, reseting terminal is connected with the power on signal SYSTEM_POR_B of system, the output of the input terminal and cooperation circuit of trigger
Terminal FS1 is connected, and the output of FS1 will be latched by trigger.Cooperate circuit by pull-up resistor, PMOS switch pipe, configuration bonding hole
(ConfigPad), phase inverter (INV_1) is constituted, and wherein PMOS is controlled its conducting by enable signal PullUP_Enable or closed
Disconnected, the input terminal that the output end of PMOS is bonded hole with configuration is connected to the input terminal of phase inverter.
When a system is powered up, it is connected due to reseting terminal with the power on signal SYSTEM_POR_B of system, trigger
Output end q will be reset to 0, that is, enable signal PullUP_Enable is reset to 0.At this point, according to the two of bonding hole
The work of kind state, corresponding cooperation circuit also has two states, and one is when bonding hole is hanging, system electrification causes
PMOS conducting, the input terminal of phase inverter will access pull-up resistor, by input high level, after phase inverter, cooperate circuit
Output terminal FS1 will export low level, output logic signal " 0 ", at the same time, FS1 will be latched by trigger DFFR_1, touching
The output end q of hair device will be kept output low level, i.e. output logic signal " 0 " goes to control the conducting of PMOS；Another kind works as key
When conjunction hole is connected to the lead frame of ground connection, although enable signal PullUP_Enable is reset to 0 and controls when system electrification
PMOS conducting, but the input terminal of phase inverter, by input low level, therefore, the output FS1 of phase inverter will export high level, output
Logical signal " 1 ", at the same time, FS1 will be latched by trigger DFFR_1, and the output end q of trigger will be kept the high electricity of output
Flat, i.e., output logic signal " 1 " goes control PMOS shutdown, avoids the constantly on waste electric energy of PMOS.
Therefore, for being bonded hole 1, the output of FS1 is matched with the state for being bonded hole, can export " 0 ", " 1 " two
The configuration signal of kind state.Similarly, " 0 ", " 1 " two states can be exported for other 5 bonding hole 2-6, therefore, for
For chip with 6 configuration bonding holes, so that it may generate 6 configuration signals, this 6 configuration signals can be sent to decoding
Device, as shown in figure 3, FS1-FS6 is respectively connected to the input terminal of decoder, since each configuration signal all has two kinds of " 0 ", " 1 "
State, therefore can produce 26 powers i.e. 64 kind configuration mode, the function for selecting chip can be numbered with 0-63
It can and configure.For example the function of resolution ratio and conversion speed that number 0-10 is chip selection analog-digital converter can be set to expire
The different use demand of foot, or using number 11-20 is the embedded memory that chip selects different capabilities；Use number 21-
30 select the running frequency of friction speed to use for different occasions for chip.
The above description is only a preferred embodiment of the present invention, thus it is all according to the configuration described in the scope of the patent application of the present invention,
The equivalent change or modification that feature and principle are done, is included in the scope of the patent application of the present invention.
Claims (7)
1. a kind of device for being bonded configuration chip using lead frame, it is characterised in that: there is described device chip package to reserve
The logic control circuit in configuration bonding hole and chip interior, the configuration bonding hole and the logic control circuit are with the use of next
Chip functions are configured, the quantity in configuration bonding hole is n, and n is natural number, the configurable modes number of the configuration chip functions
Amount is 2 n times side, and the state for configuring bonding hole is to be bonded the lead frame connection in hanging hole or bonding hole and ground connection,
The logic control circuit circuit and trigger with are constituted, and the output end of circuit is cooperated to connect the input terminal of trigger, touching
The output end control cooperation circuit of device is sent out, the output end of the cooperation circuit is also used as the output end of logic control circuit, passes through
So that each configuration bonding hole is in state that is hanging or connecting with the lead frame of ground connection, obtain being bonded hole one with the configuration
One corresponding one group n configuration signal, and a configurable modes for being used to configure chip functions in n times side that chip is configured to 2
In a corresponding configuration mode；Wherein, each configuration signal is the state of " 1 " or " 0 ".
2. as described in claim 1 using the device of lead frame bonding configuration chip, which is characterized in that the configuration is bonded hole
It is corresponded with logic control circuit.
3. as described in claim 1 using lead frame bonding configuration chip device, which is characterized in that the cooperation circuit by
Pull-up resistor, PMOS switch pipe, configuration bonding hole, phase inverter are constituted, and wherein PMOS controls its conducting by the output end of trigger
Or shutdown, the input terminal in the output end of PMOS and configuration bonding hole are connected to the input terminal of phase inverter, the phase inverter it is defeated
Outlet is the output end for cooperating circuit.
4. as described in claim 1 using the device of lead frame bonding configuration chip, which is characterized in that the logic control electricity
Road exports " 0 ", " 1 " two states.
5. as described in claim 1 using the device of lead frame bonding configuration chip, which is characterized in that the trigger is tool
There is the trigger of latch function.
6. as claimed in claim 2 using the device of lead frame bonding configuration chip, which is characterized in that the configuration mode is
Chip selects the resolution ratio of analog-digital converter and the embedded memory or chip selection of conversion speed or chip selection different capabilities
The running frequency of friction speed.
7. a kind of method for being bonded configuration chip using lead frame, it is characterised in that: be bonded using the configuration that chip package is reserved
The logic control circuit of hole and chip interior configures chip functions, and the state in configuration bonding hole is that bonding hole is hanging or key
The lead frame for closing hole and ground connection connects, and the quantity in configuration bonding hole is n, and n is natural number, by making each configuration
Bonding hole is in state that is hanging or connecting with the lead frame of ground connection, obtains being bonded one-to-one one group of hole with the configuration
N configuration signal, and a one be used to configure in the configurable modes of chip functions in n times side that chip is configured to 2 is corresponding
Configuration mode；Wherein, each configuration signal is the state of " 1 " or " 0 ", is bonded hole with the configuration and patrols correspondingly
It collects control circuit and generates " 1 ", " 0 " two states, the output of n logic control circuit is exported to 2 n times side after decoder
The configurable modes of configurable chip functions cooperate the output end output logic signal " 0 " of circuit when bonding hole is hanging, and
It is latched by trigger, the output end of trigger will be kept output low level, control PMOS conducting；It is connect when bonding hole is connected to
When the lead frame on ground, cooperate the output end output logic signal " 1 " of circuit, and latched by trigger, the output end of trigger will
It is kept output high level, control PMOS shutdown.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810271767.6A CN108461472B (en) | 2018-03-29 | 2018-03-29 | A kind of device and method being bonded configuration chip using lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810271767.6A CN108461472B (en) | 2018-03-29 | 2018-03-29 | A kind of device and method being bonded configuration chip using lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108461472A CN108461472A (en) | 2018-08-28 |
| CN108461472B true CN108461472B (en) | 2019-11-01 |
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| CN201810271767.6A Active CN108461472B (en) | 2018-03-29 | 2018-03-29 | A kind of device and method being bonded configuration chip using lead frame |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19936606C1 (en) * | 1999-08-04 | 2000-10-26 | Siemens Ag | Integrated circuit voltage supply via pad e.g. for microprocessors and microcontrollers |
| DE19946495C2 (en) * | 1999-09-28 | 2002-10-24 | Infineon Technologies Ag | Method of reducing the number of pads on a semiconductor chip |
| US6938235B2 (en) * | 2002-11-14 | 2005-08-30 | Cirrus Logic, Inc. | Integrated circuit with authomatic pin-strapping configuration |
| CN100356379C (en) * | 2005-09-22 | 2007-12-19 | 北京中星微电子有限公司 | System and method for identifying electronic element |
| CN101488465B (en) * | 2009-02-18 | 2012-01-11 | 北京天碁科技有限公司 | Chip feature configuring method and chip |
| CN204046568U (en) * | 2014-09-02 | 2014-12-24 | 淮安信息职业技术学院 | The memory configuration circuit of a kind of FPGA |
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- 2018-03-29 CN CN201810271767.6A patent/CN108461472B/en active Active
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Effective date of registration: 20191009 Address after: 224100 No.3, Mengmeng Avenue, Xinfeng Town, Dafeng District, Yancheng City, Jiangsu Province Applicant after: Jiangsu Jurun Silicon Valley New Materials Technology Co., Ltd. Address before: 215000 No. 5 Xinghan Street, Suzhou Industrial Park, Jiangsu Province Applicant before: Deng Li Ping |
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Denomination of invention: A device and method for configuring a chip using lead frame bonding Effective date of registration: 20210812 Granted publication date: 20191101 Pledgee: China Construction Bank Corporation Yancheng Dafeng sub branch Pledgor: JIANGSU JURUN GUIGU NEW MATERIAL TECHNOLOGY Co.,Ltd. Registration number: Y2021980007593 |