CN100356379C - System and method for identifying electronic element - Google Patents
System and method for identifying electronic element Download PDFInfo
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- CN100356379C CN100356379C CNB2005101049567A CN200510104956A CN100356379C CN 100356379 C CN100356379 C CN 100356379C CN B2005101049567 A CNB2005101049567 A CN B2005101049567A CN 200510104956 A CN200510104956 A CN 200510104956A CN 100356379 C CN100356379 C CN 100356379C
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Abstract
The present invention relates to a system for identifying electronic elements, which comprises a bus, at least one configuration terminal and a decoding strobe circuit, wherein each of the configuration terminals comprises tube core bonding pads and input buffers which are connected with one another, and the input buffers are used for identifying the state of electrical level of the tube core bonding pads and obtaining digital signals; all the configuration terminals are respectively connected with the decoding strobe circuit through the input buffers, and the digital signals obtained by identifying the state of electrical level of the tube core bonding pads of the pads are sent to the encoding strobe circuit by the input buffers; the decoding strobe circuit is respectively connected with the input buffers in all the configuration terminals and also connected with the bus, receives the digital signal transmitted by the input buffers in all the configuration terminals to carry out the operation of circuit strobe, obtains identifying marks and sends the identifying marks to the bus. The present invention also provides the method for identifying electronic elements, and the system and method provided by the present invention realizes the goal that the information used for identifying electronic elements can not be easily falsified.
Description
Technical field
The present invention relates to integrated circuit (IC) design and manufacturing field, particularly a kind of system and method for identifying electronic element.
Background technology
Include a large amount of electronic components in electronic product, and different electronic product often comprised a large amount of general or similar electronic components, this just need self identify the electronic component of same model so that use in design electronic products.Usually, electronic component manufacturer can identify the electronic component of same type with identification of the manufacturer (ID) and product IDs jointly, and will guarantee and can not be distorted.
At present, the method for identifying electronic element has two kinds:
First method, employing adds erasable device on electronic component, as add erasable programmable read only memory (EEPROM) or Flash ROM (read-only memory) (ROM), vendor id and product IDs etc. is used for the erasable device of the information stores of identifying electronic element in setting.
Fig. 1 is first kind of system applies synoptic diagram of identifying electronic element in the prior art, suppose that this electronic component is a signal Processing control chip 11, comprise host interface circuit 13, signal processing unit A～N that is connected with main frame 12 and the peripheral interface circuit 15 that is connected with peripheral hardware 14.Wherein, host interface circuit 13, signal processing unit A～N and peripheral interface circuit 15 all hang on the bus 16 of chip, carry out the mutual of data; Also be connected to each other between signal processing unit A～N, and signal processing unit A is connected with peripheral interface circuit 15, carries out the mutual of data.In order to identify this chip, this chip need add an EEPROM, and in chip, there is an EEPROM controller 17 that hangs over bus 16 to be connected with EEPROM, wherein, EEPROM is used for the sign of storage chip, EEPROM controller 17 after receiving the order of reading chip identification that is sent by main frame 12 from bus 16 reads out the chip identification that EEPROM stored, and finally sends to send by bus and reads the main frame 12 of chip identification order.
Second method adopts existing programmable storage circuits on electronic component, and as programming ROM, the information stores that vendor id and product IDs etc. is used for identifying electronic element is in this programmable storage circuits.
Fig. 2 is second kind of system applies synoptic diagram of identifying electronic element in the prior art, suppose that this electronic component is a signal Processing control chip 21, the peripheral interface circuit 15 that comprises the host interface circuit 13, signal processing unit A～N, the programming ROM that are connected with main frame 12 and be erasable ROM on the sheet and be connected with peripheral hardware 14.Wherein, erasable ROM and peripheral interface circuit 15 all hang on the bus 16 of chip on host interface circuit 13, signal processing unit A～N, the sheet, carry out the mutual of data; Also be connected to each other between signal processing unit A～N, and signal processing unit A is connected with peripheral interface circuit 15, carries out the mutual of data.In order to identify this chip, the sign of this chip is stored on the sheet among the erasable ROM, after receiving the order of reading chip identification that sends by main frame 12 from bus 16 as erasable ROM on the sheet, the chip identification of being stored finally sent to send by bus 16 read the main frame 12 of chip identification order.
But, these two kinds of methods all exist shortcoming: in first method, for identifying electronic element, must in electronic component, increase a circuit that is used for the circuit of store electrons element identifier and reads institute's store electrons element identifier, such as increase an eeprom chip on the signal Processing control chip, this can increase the electronic component volume, and cost is higher, and owing to realize identifying electronic element by software, the electronic component sign that causes possibly being stored is distorted; In the second approach, though existing memory circuitry stores electronic component sign in the use electronic component, such as erasable ROM on the sheet in the signal Processing control core, but because complex process, cost is higher, and owing to also be to realize identifying electronic element by software, the electronic component sign that causes possibly being stored is distorted.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of system of identifying electronic element, can make that the information that is used for identifying electronic element is not easy to be distorted.
Another object of the present invention is to provide a kind of method of identifying electronic element, can make that the information that is used for identifying electronic element is not easy to be distorted.
According to above-mentioned purpose, technical scheme of the present invention is achieved in that
A kind of system of identifying electronic element comprises bus, and this system also comprises: at least one configuration terminal, decoding gating circuit;
Each configuration terminal comprises pipe core welding disc and the input buffer that is connected, and input buffer obtains digital signal in order to the level state of identification pipe core welding disc;
All configuration terminals respectively by wherein input buffer with decipher gating circuit and be connected, and will discern the digital signal that the level state of pipe core welding disc obtains by input buffer and send to the decoding gating circuit;
Input buffer is connected respectively in decoding gating circuit and all configuration terminals, and links to each other with bus, receives the digital signal that all dispose input buffer transmission in terminals, carries out the circuit gating, and the sign that obtains electronic component sends on the bus.
This system also comprises at least one pair of chip pin, and in described at least one pair of chip pin, a chip pin is connected with the power supply of electronic system, and another chip pin is connected with the ground of electronic system; There is a chip pin also to be connected in every pair of chip pin with a pipe core welding disc that disposes in the terminal.
Described each configuration terminal further comprises pull-up resistor, and described pull-up resistor one end connects the power ring of chip-die; The other end is connected in the pipe core welding disc in the configuration terminal.
Described input buffer is the input buffer that comprises pull-up resistor.
This system also comprises chip pin, and described chip pin is connected with pipe core welding disc in one or more configuration terminals, and chip pin is connected with the ground of electronic system simultaneously.
Described each configuration terminal further comprises pull down resistor, and described pull down resistor one end connects the ground ring of chip-die; The other end is connected in the pipe core welding disc in the configuration terminal.
Described input buffer is the input buffer that comprises pull down resistor.
This system also comprises chip pin, and described chip pin is connected with pipe core welding disc in one or more configuration terminals, and chip pin is connected with the power supply of electronic system simultaneously.
A kind of method of identifying electronic element is provided with at least one configuration terminal in chip-die, the method includes the steps of:
A, connect the input buffer of each configuration in terminal and pipe core welding disc, be connected in each configuration terminal input buffer with the decoding gating circuit, be connected the bus of deciphering gating circuit and electronic component;
Input buffer is discerned the level state of the pipe core welding disc that is connected with self respectively in b, each configuration terminal, obtains digital signal, and sends to the decoding gating circuit;
C, decoding gating circuit receive the digital signal that input buffer sends in each configuration terminal, carry out the circuit gating, obtain the sign of electronic component, and send on the bus of electronic component.
At least one pair of chip pin is set, described step a further comprises: connect the chip pin in described at least one pair of chip pin and the power supply of electronic system, connect another chip pin in described at least one pair of chip pin and the ground of electronic system, connect pipe core welding disc and chip pin in each configuration terminal;
What connect when pipe core welding disc is the chip pin that is connected with the power supply of electronic system, and the level state of the pipe core welding disc that input buffer is discerned among the step b is a high level, obtains digital signal " 1 ";
What connect when pipe core welding disc is the chip pin that is connected with the ground of electronic system, and the level state of the pipe core welding disc that input buffer is discerned among the step b is a low level, obtains digital signal " 0 ".
Described step a further comprises:
Pipe core welding disc in power ring and the configuration terminal is connected by pull-up resistor, and it is pipe core welding disc is unsettled; Perhaps pipe core welding disc in ground ring and the configuration terminal is connected by pull down resistor, and connects pipe core welding disc and the chip pin that is connected power supply.
The level state of the pipe core welding disc of input buffer identification is a high level among the step b, obtains digital signal " 1 ".
Described step a further comprises:
Pipe core welding disc in ground ring and the configuration terminal is connected by pull down resistor, and it is pipe core welding disc is unsettled; Perhaps pipe core welding disc in power ring and the configuration terminal is connected by pull-up resistor, and connects pipe core welding disc and the chip pin that is connected ground.
The level state of the pipe core welding disc of input buffer identification is a low level among the step b, obtains digital signal " 0 ".
The present invention adopts the hardware configuration mode that electronic component is identified, and promptly introduces the configuration terminal in the design phase of electronic component, and the different conditions of the logic identification configuration terminal of electronic component inside produces different codings, and this coding is the sign of electronic component.The present invention has following beneficial effect:
1) the present invention is configured hardware at the encapsulated phase of electronic component, and the sign of electronic component produces according to the hardware configuration situation, therefore adopts the present invention, can be not easy to be distorted so that be used for the information of identifying electronic element.
2) the configuration terminal volume that adopts among the present invention is little, can not change the volume and the shape of original electronic component substantially, and can save cost compared with prior art.
3) adopt the input buffer of band pull-up resistor or pull down resistor among the present invention, owing to only need a chip pin that connects the chip pin of power supply or connect ground, can avoid intersecting line and the short circuit that causes easily the reliability height.
Description of drawings
Fig. 1 is first kind of system applies synoptic diagram of identifying electronic element in the prior art;
Fig. 2 is second kind of system applies synoptic diagram of identifying electronic element in the prior art;
Fig. 3 is the system architecture synoptic diagram that the embodiment of the invention 1 is utilized configuration terminal identifying electronic element;
Fig. 4 is the system applies synoptic diagram that the embodiment of the invention 1 is utilized configuration terminal identifying electronic element;
First kind of system architecture synoptic diagram when Fig. 5 comprises pull-up resistor for the embodiment of the invention 2 configuration terminals;
Second kind of system architecture synoptic diagram when Fig. 6 comprises pull-up resistor for the embodiment of the invention 2 configuration terminals;
The third system architecture synoptic diagram when Fig. 7 comprises pull-up resistor for the embodiment of the invention 2 configuration terminals;
System applies synoptic diagram when Fig. 8 comprises pull-up resistor for the embodiment of the invention 2 configuration terminals;
First kind of system architecture synoptic diagram when Fig. 9 comprises pull down resistor for the embodiment of the invention 3 configuration terminals;
Second kind of system architecture synoptic diagram when Figure 10 comprises pull down resistor for the embodiment of the invention 3 configuration terminals;
The third system architecture synoptic diagram when Figure 11 comprises pull down resistor for the embodiment of the invention 3 configuration terminals;
System applies synoptic diagram when Figure 12 comprises pull down resistor for the embodiment of the invention 3 configuration terminals;
Figure 13 is the process flow diagram of identifying electronic element method one among the present invention;
Figure 14 is the process flow diagram of identifying electronic element method two among the present invention.
Embodiment
Usually, chip comprises Chip Packaging and chip-die, solder joint on the Chip Packaging is chip pin or pin (PIN), solder joint on the chip-die is pipe core welding disc or pad (PAD), generally, chip pin on each Chip Packaging all has at least one pipe core welding disc that is attached thereto corresponding with it on chip-die, and to establish a capital a chip pin on the Chip Packaging corresponding with it and the pipe core welding disc on each chip-die differs.
Among the present invention, in order to guarantee that the information that is used for identifying electronic element is not easy to be distorted, adopt the hardware configuration mode that electronic component is identified, detailed process is: introduce the configuration terminal in the design phase of electronic component, the different conditions of the logic identification configuration terminal of electronic component inside, produce different codings through decoding gating circuit gating, this coding is the sign of electronic component.The state of certain configuration terminal can be determined by the Chip Packaging inner lead, also can directly obtain by pull-up resistor or pull down resistor in the configuration terminal, herein, inner lead is meant the line that connects pipe core welding disc and chip pin, described chip pin is connected to the power supply or the ground of electronic system, wherein, electronic system is meant the system that comprises described electronic component, such as: the electronic product that comprises described electronic component.
Below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Embodiment 1: utilize configuration terminal identifying electronic element.
See also Fig. 3, Fig. 3 is for utilizing the system architecture synoptic diagram of configuration terminal identifying electronic element, system shown in Figure 3 comprises: chip pin be power pin VDD0/ ground pin VSS0～power pin VDDn/ ground pin VSSn altogether n+1 to chip pin, configuration terminal 0～n altogether n+1 configuration terminal, decipher gating circuit 31, wherein, each power pin/ground pin is to being VDDi/VSSi, configuration terminal i corresponding with it comprises input buffer ID[i] and pipe core welding disc i, n is a natural number, i=0～n.
Among Fig. 3, n+1 is connected with the power supply or the ground of electronic system respectively an end of chip pin, and n+1 is connected with n+1 pipe core welding disc that disposes in the terminal to the other end of the chip pin of n+1 in the chip pin.Specifically: n+1 is in the chip pin, and the end of VDD0～VDDn is connected with the power supply of electronic system respectively, and the end of VSS0～VSSn is connected with the ground of electronic system respectively; VDDi among the every couple of chip pin VDDi/VSSi or VSSi are connected with pipe core welding disc i among the configuration terminal i.
The end of configuration terminal 0～n is connected to the chip pin of the n+1 among chip pin VDD0/VSS0～VDDn/VSSn with n+1 respectively, the other end is connected with decoding gating circuit 31, that is: the pipe core welding disc i among the configuration terminal i is connected with chip pin VDDi or VSSi; Input buffer ID[i among the configuration terminal i] be connected with decoding gating circuit 31.Herein, configuration terminal i comprises pipe core welding disc i and the input buffer ID[i that is connected], input buffer ID[i] in order to the level state of identification pipe core welding disc i, obtain digital signal; And with digital signal send to decoding gating circuit 31.As for the level state of pipe core welding disc, when pipe core welding disc i is connected with the VDDi that is connected power supply, input buffer ID[i] the pipe core welding disc level state of identification is high level, obtains digital signal " 1 ", i.e. ID[i]=1; As pipe core welding disc i and the VSSi that is connected ground when being connected, input buffer ID[i] the pipe core welding disc level state of identification is low level, obtains digital signal " 0 ", i.e. ID[i]=0.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, herein, decoding gating circuit 31 will carry out the circuit gating from the digital signal that configuration terminal 0～n sends, obtain the sign of electronic component, and the sign of electronic component is sent on the bus of electronic component by data read bus 32.
Because each configuration terminal all can obtain one-bit digital signal " 0 " or " 1 ", n+1 configuration terminal will obtain the n+1 position digital signal, therefore utilize system shown in Figure 3, by each configuration terminal and the different connections that connect power supply or connect the chip pin on ground in n+1 the configuration terminal, finally can obtain from " 00..000 " to " 11..111 " totally 2
N+1Individual different n+1 position coding, i.e. electronic component sign.
Among Fig. 3, disposed n+1 to chip pin VDD0/VSS0～VDDn/VSSn for n+1 pipe core welding disc 0～n, wherein n+1 pipe core welding disc is connected with n+1 chip pin, and promptly pipe core welding disc i is connected with chip pin VDDi or VSSi.In the practical application, be less than the right chip pin of n+1 also can for n+1 pipe core welding disc configuration, such as n+2 interconnected chip pin of VDD and VSS etc., every pair of pipe core welding disc still can be connected to one among the VDD/VSS with chip pin at this moment.
See also Fig. 4, Fig. 4 is the system applies synoptic diagram of the embodiment of the invention 1 identifying electronic element, as shown in Figure 4, suppose that this electronic component is a signal Processing control chip 41, comprise host interface circuit 13, signal processing unit A～N that is connected with main frame 12 and the peripheral interface circuit 15 that is connected with peripheral hardware 14.Wherein, host interface circuit 13, signal processing unit A～N and peripheral interface circuit 15 all hang on the bus 16 of chip, carry out the mutual of data; Also be connected to each other between signal processing unit A～N, and signal processing unit A is connected with peripheral interface circuit 15, carries out the mutual of data.In order to identify this chip, the described system of Fig. 3 is hung on the bus 16 of chip, specifically: decoding gating circuit 47 comprises decoding gating circuit 31 among Fig. 3, input buffer ID[0 among Fig. 4 among Fig. 4]～ID[n], identical among pipe core welding disc 0～n, chip pin VDD0～VDDn, VSS0～VSSn and Fig. 3.After decoding gating circuit 47 receives the order of reading chip identification that is sent by main frame 12, obtain chip identification by system shown in Figure 3, and the bus 16 by chip the most at last chip identification send to send and read the main frame 12 of chip identification order.
The present invention also proposes to comprise pull-up resistor as embodiment 2 configuration terminals, and the scheme that comprises pull down resistor as embodiment 3 configuration terminals.
Embodiment 2: the configuration terminal comprises pull-up resistor.
Among the embodiment 2, each configuration terminal i comprises: input buffer ID[i] and coupled pipe core welding disc i, pull-up resistor i, wherein, the end of pull-up resistor i connects the power ring (Power Ring) of chip-die, and the other end connects pipe core welding disc i.According to prior art, circuit design stage at electronic component, the power ring of chip-die has been connected to the power pad (PAD) of chip-die, power pad has been connected to the power pin (PIN) of Chip Packaging, power pad herein and power pin are not specially for pull-up resistor configuration, but electronic component itself also needs when not having pull-up resistor.
See also Fig. 5, first kind of system architecture synoptic diagram when Fig. 5 comprises pull-up resistor for the configuration terminal.As shown in Figure 5, when the configuration terminal comprised pull-up resistor, the system of identifying electronic element comprised: configuration terminal 0～n is total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull-up resistor i, n is a natural number, i=0～n.
Among Fig. 5, the end of configuration terminal 0～n is unsettled, the other end is connected with decoding gating circuit 31, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, at this moment, the level state of all pipe core welding discs obtains by pull-up resistor, be high level, all input buffers all obtain digital signal " 1 ", be ID[0]=1, ID[1]=1, ..., ID[n]=1, configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that process decoding gating circuit 31 obtains is designated the data " 111...11 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
An end of configuration terminal also can connect chip pin, as Fig. 6, shown in Figure 7 except unsettled among Fig. 5.
See also Fig. 6, second kind of system architecture synoptic diagram when Fig. 6 comprises pull-up resistor for the configuration terminal.The system of identifying electronic element as shown in Figure 6 comprises: chip pin VSS, configuration terminal 0～n are total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull-up resistor i, n is a natural number, i=0～n.
Among Fig. 6, the end of chip pin VSS is connected with the ground of electronic system, and the other end is connected with the pipe core welding disc 1 of configuration in the terminal 1.
The end of configuration terminal 0～n is connected with decoding gating circuit 31, the other end of configuration terminal 0,2～n is unsettled, the other end of configuration terminal 1 is connected with chip pin VSS, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, wherein, the level state of the pipe core welding disc that the other end is unsettled is obtained by pull-up resistor, is high level, input buffer obtains digital signal " 1 ", i.e. ID[0]=1, ID[2]=1 ..., ID[n]=1; The other end be connected with VSS pipe core welding disc level state by be connected ground chip pin VSS obtain, be low level, input buffer obtains digital signal " 0 ", be ID[1]=0, configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that process decoding gating circuit 31 obtains is designated the data " 101...11 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
See also Fig. 7, the third system architecture synoptic diagram when Fig. 7 comprises pull-up resistor for the configuration terminal.The system of identifying electronic element as shown in Figure 7 comprises: chip pin VSS, configuration terminal 0～n are total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull-up resistor i, n is a natural number, i=0～n.
Among Fig. 7, the end of chip pin VSS is connected with the ground of electronic system, and the other end is connected with n+1 pipe core welding disc that disposes in the terminal.
The end of configuration terminal 0～n is connected with decoding gating circuit 31, the other end all is connected with chip pin VSS, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, at this moment, the level state of pipe core welding disc obtains by the chip pin VSS that connects ground, be low level, input buffer all obtains digital signal " 0 ", be ID[0]=0, ID[1]=0, ..., ID[n]=0, configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that process decoding gating circuit 31 obtains is designated the data " 00..000 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
Embodiment when Fig. 5, Fig. 6, Fig. 7 comprise pull-up resistor for the configuration terminal, by changing being connected or not connecting of pipe core welding disc 0～n and chip pin VSS among configuration terminal 0～n, dispose system that terminal comprises the identifying electronic element of pull-up resistor finally can obtain from " 00..000 " to " 11..111 " totally 2
N+1Individual different n+1 position coding, i.e. electronic component sign.
See also Fig. 8, system applies synoptic diagram when Fig. 8 comprises pull-up resistor for the configuration terminal, as shown in Figure 8, suppose that this electronic component is a signal Processing control chip 81, comprise host interface circuit 13, signal processing unit A～N that is connected with main frame 12 and the peripheral interface circuit 15 that is connected with peripheral hardware 14.Wherein, host interface circuit 13, signal processing unit A～N and peripheral interface circuit 15 all hang on the bus 16 of chip, carry out the mutual of data; Also be connected to each other between signal processing unit A～N, and signal processing unit A is connected with peripheral interface circuit 15, carries out the mutual of data.In order to identify this chip, Fig. 5, Fig. 6 or the described system of Fig. 7 can be hung on the bus 16 of chip, Figure 8 shows that wherein the described system of Fig. 7 hangs on the bus 16 of chip, specifically: decoding gating circuit 47 comprises decoding gating circuit 31 among Fig. 7, input buffer ID[0 among Fig. 8 among Fig. 8]～ID[n], identical among pipe core welding disc 0～n, chip pin VSS and Fig. 7.After decoding gating circuit 47 received the order of reading chip identification that is sent by main frame 12, the bus 16 of the chip identification that obtains by system shown in Figure 7 by chip finally sent to send and reads the main frame 12 of chip identification order.
Among the embodiment 2, the configuration terminal comprises: in the practical application, there are the input buffer that self has pull-up resistor in pipe core welding disc, input buffer, pull-up resistor, in this case, the configuration terminal just comprises: the input buffer of pipe core welding disc and band pull-up resistor.
Embodiment 3: the configuration terminal comprises pull down resistor.
Among the embodiment 3, each configuration terminal i comprises: input buffer ID[i] and coupled pipe core welding disc i, pull down resistor i, wherein, the end of pull down resistor i connects the ground ring (GroundRing) of chip-die, and the other end connects pipe core welding disc i.According to prior art, circuit design stage at electronic component, the ground ring of chip-die has been connected to the ground pad (PAD) of chip-die, the ground pad has been connected to the ground pin (PIN) of Chip Packaging, ground pad herein and ground pin are not specially for pull down resistor disposes, but electronic component itself also needs when not having pull down resistor.
See also Fig. 9, first kind of system architecture synoptic diagram when Fig. 9 comprises pull down resistor for the configuration terminal.As shown in Figure 9, when the configuration terminal comprised pull down resistor, the system of identifying electronic element comprised: configuration terminal 0～n is total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull down resistor i, n is a natural number, i=0～n.
Among Fig. 9, the end of configuration terminal 0～n is unsettled, the other end is connected with decoding gating circuit 31, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, at this moment, the level state of all pipe core welding discs obtains by pull down resistor, be low level, input buffer all obtains digital signal " 0 ", be ID[0]=0, ID[1]=0, ..., ID[n]=0, configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that process decoding gating circuit 31 obtains is designated the data " 00...000 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
The other end of configuration terminal also can connect chip pin, as Figure 10, shown in Figure 11 except unsettled among Fig. 9.
See also Figure 10, first kind of system architecture synoptic diagram when Figure 10 comprises pull down resistor for the configuration terminal.The system of identifying electronic element as shown in figure 10 comprises: chip pin VDD, configuration terminal 0～n are total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull down resistor i, n is a natural number, i=0～n.
Among Figure 10, the end of chip pin VDD is connected with the power supply of electronic system, and the other end is connected with the pipe core welding disc 1 of configuration in the terminal 1.
The end of configuration terminal 0～n is connected with decoding gating circuit 31, the other end of configuration terminal 0,2～n is unsettled, the other end of configuration terminal 1 is connected with chip pin VDD, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, wherein, the level state of the pipe core welding disc that the other end is unsettled is obtained by pull down resistor, is low level, input buffer obtains digital signal " 0 ", i.e. ID[0]=0, ID[2]=0 ..., ID[n]=0; Be connected with the VDD level state of pipe core welding disc of the other end is obtained by the chip pin VDD that is connected power supply, be high level, input buffer obtains digital signal " 1 ", be ID[1]=1 configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that obtains through decoding gating circuit 31 is designated the data " 010...00 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
See also Figure 11, the third system architecture synoptic diagram when Figure 11 comprises pull down resistor for the configuration terminal.The system of identifying electronic element as shown in figure 11 comprises: chip pin VDD, configuration terminal 0～n are total to n+1 configuration terminal, decoding gating circuit 31, wherein, configuration terminal i comprises input buffer ID[i], pipe core welding disc i, pull down resistor i, n is a natural number, i=0～n.
Among Figure 11, the end of chip pin VDD is connected with the power supply of electronic system, and the other end is connected with n+1 pipe core welding disc that disposes in the terminal.
The end of configuration terminal 0～n is connected with decoding gating circuit 31, the other end all is connected with chip pin VDD, input buffer ID[i among the configuration terminal i] level state of identification pipe core welding disc i obtains digital signal, at this moment, the level state of all pipe core welding discs obtains by the chip pin VDD that connects power supply, be high level, input buffer obtains digital signal " 1 ", be ID[0]=1, ID[1]=1, ..., ID[n]=1, configuration terminal 0～n sends to decoding gating circuit 31 with the digital signal of this n+1 position, and the electronic component that process decoding gating circuit 31 obtains is designated the data " 11..111 " of n+1 position.
Input buffer ID[0 in deciphering gating circuit 31 and disposing terminal 0～n]～ID[n] be connected, and be connected with the bus of electronic component by data read bus 32, digital signal that will input buffer sends from configuration terminal 0～n is carried out the circuit gating, obtain the sign of electronic component, the sign of electronic component is sent on the bus of electronic component by data read bus 32.
Embodiment when Fig. 9, Figure 10, Figure 11 comprise pull down resistor for the configuration terminal, by changing being connected or not connecting of pipe core welding disc 0～n and chip pin VDD among configuration terminal 0～n, dispose system that terminal comprises the identifying electronic element of pull down resistor finally can obtain from " 00..000 " to " 11..111 " totally 2
N+1Individual different n+1 position coding, i.e. electronic component sign.
See also Figure 12, system applies synoptic diagram when Figure 12 comprises pull down resistor for the configuration terminal, as shown in figure 12, suppose that this electronic component is a signal Processing control chip 121, comprise host interface circuit 13, signal processing unit A～N that is connected with main frame 12 and the peripheral interface circuit 15 that is connected with peripheral hardware 14.Wherein, host interface circuit 13, signal processing unit A～N and peripheral interface circuit 15 all hang on the bus 16 of chip, carry out the mutual of data; Also be connected to each other between signal processing unit A～N, and signal processing unit A is connected with peripheral interface circuit 15, carries out the mutual of data.In order to identify this chip, Fig. 9, Figure 10 or the described system of Figure 11 can be hung on the bus 16 of chip, Figure 12 shows that wherein the described system of Figure 11 hangs on the bus 16 of chip, specifically: decoding gating circuit 47 comprises decoding gating circuit 31 among Figure 11, input buffer ID[0 among Figure 12 among Figure 12]～ID[n], identical among pipe core welding disc 0～n, chip pin VDD and Figure 11.After decoding gating circuit 47 received the order of reading chip identification that is sent by main frame 12, the bus 16 of the chip identification that obtains by system shown in Figure 11 by chip finally sent to send and reads the main frame 12 of chip identification order.
Among the embodiment 3, the configuration terminal comprises: in the practical application, there are the input buffer that self has pull down resistor in pipe core welding disc, input buffer, pull down resistor, in this case, the configuration terminal just comprises: the input buffer of pipe core welding disc and band pull down resistor.
The present invention proposes the method one of identifying electronic element according to the system of identifying electronic element among the embodiment 1.See also Figure 13, Figure 13 is the process flow diagram of identifying electronic element method one, and as shown in figure 13, the method one of identifying electronic element comprises following steps:
Step 131: connect the input buffer that comprises in the configuration terminal and pipe core welding disc, be connected input buffer and decoding gating circuit in n+1 the configuration terminal, be connected the bus of deciphering gating circuit and electronic component, the power supply that is connected chip pin and electronic system or, n is a natural number.Herein, to a pair of chip pin of each configuration terminal assignment, one of them chip pin is connected with the power supply of electronic system usually, and another chip pin is connected with the ground of electronic system.
Step 131 is carried out at the circuit design stage of electronic component.
Step 132: the pipe core welding disc in n+1 the configuration terminal is connected the chip pin connection on the chip pin or the connection ground of power supply respectively with one.
Step 132 is that the encapsulated phase at electronic component carries out.
Input buffer is discerned the level state of coupled pipe core welding disc respectively in step 133:n+1 the configuration terminal, obtains digital signal, and sends to the decoding gating circuit.
In the step 133, the connected chip pin of level state of the pipe core welding disc of input buffer identification is relevant in the configuration terminal: when the pipe core welding disc connection is the chip pin that is connected with the power supply of electronic system, the level state of the pipe core welding disc of input buffer identification is a high level, obtains digital signal " 1 "; What connect when pipe core welding disc is the chip pin that is connected with the ground of electronic system, and the level state of the pipe core welding disc that input buffer is discerned is a low level, obtains digital signal " 0 ".
Step 134: the decoding gating circuit receives the digital signal that input buffer sends in the configuration terminal, carries out the circuit gating, obtains the sign of electronic component, and the sign of electronic component is sent on the bus of electronic component.Normally main frame sends the order of reading the electronic component sign to the decoding gating circuit herein, after the decoding gating circuit receives the order of reading the electronic component sign, carries out the circuit gating, obtains the sign of electronic component.
The present invention proposes the method two of identifying electronic element according to the system of identifying electronic element among embodiment 2, the embodiment 3.See also Figure 14, Figure 14 is the process flow diagram of identifying electronic element method two, and as shown in figure 14, the method two of identifying electronic element comprises following steps:
Step 141: connect input buffer pull-up resistor or pull down resistor in the input buffer that comprises in the configuration terminal and pipe core welding disc, the configuration terminal, be connected that input buffer is a natural number with deciphering gating circuit, being connected the bus, the n that decipher gating circuit and electronic component in n+1 the configuration terminal.
In the step 141, described input buffer pull-up resistor, be meant with power ring with the configuration terminal in pipe core welding disc be connected by pull-up resistor; Described input buffer pull down resistor, be meant with the ground ring with the configuration terminal in pipe core welding disc be connected by pull down resistor.
Step 141 is carried out at the circuit design stage of electronic component.
Step 142:n+1 pipe core welding disc that disposes in the terminal can be unsettled, also can connect with some or all of in the pipe core welding disc that the input buffer of pull-up resistor is connected with the chip pin that is connected ground, with in the pipe core welding disc that the input buffer of pull down resistor is connected some or all of also can with the chip pin connection that is connected power supply.
Step 142 is that the encapsulated phase at electronic component carries out.
Input buffer is discerned the level state of coupled pipe core welding disc respectively in step 143:n+1 the configuration terminal, obtains digital signal, and sends to the decoding gating circuit.
In the step 143, input buffer pull-up resistor and pipe core welding disc are unsettled in the configuration terminal, or input buffer pull down resistor and pipe core welding disc are connected with the chip pin that is connected power supply in the configuration terminal, the level state that then disposes the pipe core welding disc of input buffer identification in the terminal is a high level, obtains digital signal " 1 "; Input buffer pull down resistor and pipe core welding disc are unsettled in the configuration terminal, or input buffer pull-up resistor and pipe core welding disc are connected with the chip pin that is connected ground in the configuration terminal, then the level state of the pipe core welding disc of input buffer identification is a low level, obtains digital signal " 0 ".
Step 144: the decoding gating circuit receives the digital signal that input buffer sends in the configuration terminal, carries out the circuit gating, obtains the sign of electronic component, and the sign of electronic component is sent on the bus of electronic component.Normally main frame sends the order of reading the electronic component sign to the decoding gating circuit herein, after the decoding gating circuit receives the order of reading the electronic component sign, carries out the circuit gating, obtains the sign of electronic component.
Among Figure 14, input buffer pull-up resistor or pull down resistor in the configuration terminal during practical application, also can directly use the input buffer of band pull-up resistor or band pull down resistor.
Among the present invention, the input buffer with pull-up resistor or pull down resistor can not utilize normal component of the prior art; The input buffer of band pull-up resistor or pull down resistor also can utilize normal component of the prior art.Among the present invention, the decoding gating circuit 31 that is used to generate the electronic component sign can be to increase newly, also can be to increase the part that disposes terminal corresponding to n+1 on the original decoding gating circuit of electronic component.
The above is preferred embodiment of the present invention only, is not to be used to limit the present invention.
Claims (14)
1, a kind of system of identifying electronic element comprises bus, it is characterized in that, this system also comprises: at least one configuration terminal, decoding gating circuit;
Each configuration terminal comprises pipe core welding disc and the input buffer that is connected, and input buffer obtains digital signal in order to the level state of identification pipe core welding disc;
All configuration terminals respectively by wherein input buffer with decipher gating circuit and be connected, and will discern the digital signal that the level state of pipe core welding disc obtains by input buffer and send to the decoding gating circuit;
Input buffer is connected respectively in decoding gating circuit and all configuration terminals, and links to each other with bus, receives the digital signal that all dispose input buffer transmission in terminals, carries out the circuit gating, and the sign that obtains electronic component sends on the bus.
2, system according to claim 1, it is characterized in that this system also comprises at least one pair of chip pin, in described at least one pair of chip pin, a chip pin is connected with the power supply of electronic system, and another chip pin is connected with the ground of electronic system; There is a chip pin also to be connected in every pair of chip pin with a pipe core welding disc that disposes in the terminal.
3, system according to claim 1 is characterized in that, described each configuration terminal further comprises pull-up resistor, and described pull-up resistor one end connects the power ring of chip-die; The other end is connected in the pipe core welding disc in the configuration terminal.
4, system according to claim 1 is characterized in that, described input buffer is the input buffer that comprises pull-up resistor.
5, according to claim 3 or 4 described systems, it is characterized in that this system also comprises chip pin, described chip pin is connected with pipe core welding disc in one or more configuration terminals, and chip pin is connected with the ground of electronic system simultaneously.
6, system according to claim 1 is characterized in that, described each configuration terminal further comprises pull down resistor, and described pull down resistor one end connects the ground ring of chip-die; The other end is connected in the pipe core welding disc in the configuration terminal.
7, system according to claim 1 is characterized in that, described input buffer is the input buffer that comprises pull down resistor.
8, according to claim 6 or 7 described systems, it is characterized in that this system also comprises chip pin, described chip pin is connected with pipe core welding disc in one or more configuration terminals, and chip pin is connected with the power supply of electronic system simultaneously.
9, a kind of method of identifying electronic element is characterized in that, at least one configuration terminal is set in chip-die, and the method includes the steps of:
A, connect the input buffer of each configuration in terminal and pipe core welding disc, be connected in each configuration terminal input buffer with the decoding gating circuit, be connected the bus of deciphering gating circuit and electronic component;
Input buffer is discerned the level state of the pipe core welding disc that is connected with self respectively in b, each configuration terminal, obtains digital signal, and sends to the decoding gating circuit;
C, decoding gating circuit receive the digital signal that input buffer sends in each configuration terminal, carry out the circuit gating, obtain the sign of electronic component, and send on the bus of electronic component.
10, method according to claim 9, it is characterized in that, at least one pair of chip pin is set, described step a further comprises: connect the chip pin in described at least one pair of chip pin and the power supply of electronic system, connect another chip pin in described at least one pair of chip pin and the ground of electronic system, connect pipe core welding disc and chip pin in each configuration terminal;
What connect when pipe core welding disc is the chip pin that is connected with the power supply of electronic system, and the level state of the pipe core welding disc that input buffer is discerned among the step b is a high level, obtains digital signal " 1 ";
What connect when pipe core welding disc is the chip pin that is connected with the ground of electronic system, and the level state of the pipe core welding disc that input buffer is discerned among the step b is a low level, obtains digital signal " 0 ".
11, method according to claim 9 is characterized in that, described step a further comprises:
Pipe core welding disc in power ring and the configuration terminal is connected by pull-up resistor, and it is pipe core welding disc is unsettled; Perhaps pipe core welding disc in ground ring and the configuration terminal is connected by pull down resistor, and connects pipe core welding disc and the chip pin that is connected power supply.
12, method according to claim 11 is characterized in that, the level state of the pipe core welding disc of input buffer identification is a high level among the step b, obtains digital signal " 1 ".
13, method according to claim 9 is characterized in that, described step a further comprises:
Pipe core welding disc in ground ring and the configuration terminal is connected by pull down resistor, and it is pipe core welding disc is unsettled; Perhaps pipe core welding disc in power ring and the configuration terminal is connected by pull-up resistor, and connects pipe core welding disc and the chip pin that is connected ground.
14, method according to claim 13 is characterized in that, the level state of the pipe core welding disc of input buffer identification is a low level among the step b, obtains digital signal " 0 ".
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101049567A CN100356379C (en) | 2005-09-22 | 2005-09-22 | System and method for identifying electronic element |
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| CNB2005101049567A CN100356379C (en) | 2005-09-22 | 2005-09-22 | System and method for identifying electronic element |
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| CN100356379C true CN100356379C (en) | 2007-12-19 |
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| CN106332453A (en) * | 2015-06-16 | 2017-01-11 | 中兴通讯股份有限公司 | Method and device for determining manufacturing information of printed circuit board |
| CN108461472B (en) * | 2018-03-29 | 2019-11-01 | 江苏聚润硅谷新材料科技有限公司 | A kind of device and method being bonded configuration chip using lead frame |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2287860A (en) * | 1994-03-25 | 1995-09-27 | Rood Technology | Method and means for the identification of electronic components and assemblies |
| DE10329655A1 (en) * | 2003-07-01 | 2005-02-03 | Infineon Technologies Ag | Electronic component |
| JP2005038492A (en) * | 2003-07-18 | 2005-02-10 | Teac Corp | Identification method for mounting parts of electronic device, and electronic device which can identify mounting parts |
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2005
- 2005-09-22 CN CNB2005101049567A patent/CN100356379C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2287860A (en) * | 1994-03-25 | 1995-09-27 | Rood Technology | Method and means for the identification of electronic components and assemblies |
| DE10329655A1 (en) * | 2003-07-01 | 2005-02-03 | Infineon Technologies Ag | Electronic component |
| JP2005038492A (en) * | 2003-07-18 | 2005-02-10 | Teac Corp | Identification method for mounting parts of electronic device, and electronic device which can identify mounting parts |
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| CN1744095A (en) | 2006-03-08 |
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