CN108445735A - A kind of bearing calibration of hierarchy type TDC using delay chain structure - Google Patents
A kind of bearing calibration of hierarchy type TDC using delay chain structure Download PDFInfo
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- CN108445735A CN108445735A CN201810311310.3A CN201810311310A CN108445735A CN 108445735 A CN108445735 A CN 108445735A CN 201810311310 A CN201810311310 A CN 201810311310A CN 108445735 A CN108445735 A CN 108445735A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The bearing calibration of hierarchy type TDC using delay chain structure a kind of, is related to time-to-digital converter technical field.The present invention is to solve in digital delay chain TDC, and the leading edge position relationship of external input signal is uncertain, and then the problem of cause DFF to will appear mistake output code.A kind of bearing calibration to the hierarchy type TDC using delay chain structure of the present invention, it is corrected along the time interval between the relative position by sampled signal between, and two signals obtained by delay chain survey by comparing DFF sampled signals because being unsatisfactory for TDC measuring errors caused by DFF settling times and retention time.
Description
Technical field
The invention belongs to when a kind of m- digital conversion technique field more particularly to hierarchical architecture time -- number conversion
The bearing calibration of device (TDC).
Background technology
TDC is a kind of circuit that current application is very extensive, and function is by the time interval conversion between two signals
For digital quantity, general operation principle is all based on delay chain.Fig. 2 is that a typical digital delay chain TDC is tied substantially
Composition is touched by N number of delay cell (buffer) delay chain in series and to the output sampling of each delay cell
Hair device (DFF) is composed.Assuming that each buffer is t to the delay time of input signal, according to Start in Fig. 1 and
The signal waveform of Stop it is found that the TDC output digital code QN-1...Q2Q1Q0Form be 0 ... 01 ... 1.If low level exports " 1 "
Number be N, then the TDC measure Start and Stop rising edges between time interval can be expressed as Δ=N*t.
The sample waveform of trigger DFF is as shown in figure 3, Stop samples Start signals, in left hand view in Fig. 2
Stop signal rising edges are located at the left side of Start signal rising edges, and the output of DFF at this time is " 0 "；The Stop signals in right part of flg
Rising edge is located at the right side of Start signal rising edges, and the output of DFF at this time is " 1 ".But in actual circuit, if Stop believes
It number rising edge distance Start signal rising edges close (either on left side or right side) or even overlaps, then because dff circuit
Mistake may all occur for the output result of the influence of the factors such as the delay of middle device and noise, DFF.This namely digital circuit
In one need the well-known design principle that meets：Only when establishing of DFF is met when sampling and by two signals of sampling
Between and the retention time requirement when, DFF, which just can guarantee, exports correct result.
However from digital delay chain TDC principles shown in Fig. 2 it is found that as externally input Start signals rising edge,
Position relationship between Stop signals rising edge and clock CLK rising edges is uncertain, is spaced closely together even to overlap and all may
Occur.Therefore, the output end of some of which DFF will appear the output code of mistake, such as correct output is 0 ... 0111, and Q1 pairs
0101 is exported and become for 0 ... when the DFF answered occurs wrong.
Invention content
The present invention is to solve in digital delay chain TDC, and the leading edge position relationship of external input signal is uncertain, into
And the problem of causing DFF to will appear mistake output code, a kind of correction side of the hierarchy type TDC using delay chain structure is now provided
Method.
The bearing calibration of hierarchy type TDC using delay chain structure a kind of, the method are：
When commencing signal Start arrives, reference clock counter counts reference clock CLK, meanwhile, commencing signal
Start is admitted to delay chain, and obtains time interval X, 0≤X≤T of commencing signal Start and reference clock CLK, wherein T tables
Show the time of reference clock CLK a cycles,
When stop signal Stop arrives, reference clock counter stops counting and obtains commencing signal Start and stopping
Reference clock cycle number N between signal Stop, meanwhile, stop signal Stop is admitted to delay chain, and obtains stop signal
Time interval Y, 0≤Y≤T of Stop and reference clock CLK,
The bearing calibration includes being corrected to reference clock cycle number N, and this approach includes the following steps：
If intermediate judgment value Z meets 0<Z<T,
Step 1：If the rising edge of commencing signal Start is located at the left side of reference clock CLK rising edges and X<Z, then N=
Then N-1 executes step 2；
If the rising edge of commencing signal Start is located at the right side of reference clock CLK rising edges and X>Z, then N=N+1, then
Execute step 2；
If the rising edge of commencing signal Start is located at the right side of reference clock CLK rising edges and X<Z, commencing signal Start
Rising edge be located at left side and the X of reference clock CLK rising edges>Z, or X=Z, then N=N, then executes step 2；
Step 2：If the rising edge of stop signal Stop is located at the left side of reference clock CLK rising edges and Y<Z, then N=N+
1, complete the correction of N；
If the rising edge of stop signal Stop is located at the right side of reference clock CLK rising edges and Y>Z, then N=N-1, completes N
Correction；
If the rising edge of stop signal Stop is located at the left side of reference clock CLK rising edges and Y>Z, stop signal Stop
Rising edge is located at the right side of reference clock CLK rising edges and Y<Z, or Y=Z, then N=N, completes the correction of N.
The bearing calibration further includes the correction of the time interval between commencing signal Start and end signal Stop,
This method is：N after step 2 is corrected substitutes into following formula：
Δ=NT-X+Y
Time interval Δ between commencing signal Start after being corrected and end signal Stop.
The optimal values of Z areIn practical application, most convenient is chosen.
Time interval Δ between the commencing signal Start and end signal Stop is：
Time interval, Start failing edges between Start rising edges and Stop rising edges and between Stop failing edges when
Between time interval between interval, Start failing edges and Stop rising edges or between Start rising edges and Stop failing edges when
Between be spaced.
The present invention proposes a kind of bearing calibration to the hierarchy type TDC using delay chain structure.This method is by comparing
DFF sampled signals along and by between relative position of the sampled signal between, and two signals obtained by delay chain survey when
Between interval correct because being unsatisfactory for TDC measuring errors caused by DFF settling times and retention time.The present invention, which solves, to adopt
With the hierarchy type TDC output result of delay chain structure under specific circumstances measuring error the problem of.
Description of the drawings
Fig. 1 is the hierarchy type TDC measuring principle schematic diagrames that delay chain structure is used in specific implementation mode one；
Fig. 2 is digital delay chain TDC basic structure schematic diagrams in background technology；
Fig. 3 is the sample waveform figure of DFF in Fig. 2.
Specific implementation mode
Specific implementation mode one：Present embodiment is illustrated referring to Fig.1, it is a kind of using delay described in present embodiment
The bearing calibration of the hierarchy type TDC of chain structure,
When commencing signal Start arrives, reference clock counter counts reference clock CLK, meanwhile, commencing signal
Start is admitted to delay chain, and obtains time interval X, 0≤X≤T of commencing signal Start and reference clock CLK, wherein T tables
Show the time of reference clock CLK a cycles,
When stop signal Stop arrives, reference clock counter stops counting and obtains commencing signal Start and stopping
Reference clock cycle number N between signal Stop, meanwhile, stop signal Stop is admitted to delay chain, and obtains stop signal
Time interval Y, 0≤Y≤T of Stop and reference clock CLK.
Reference clock cycle number N is corrected,
If intermediate judgment value Z meets
The rising edge of commencing signal Start is located at the right side of reference clock CLK rising edges and X>Z, then N=N+1,
The rising edge of stop signal Stop is located at the right side of reference clock CLK rising edges and Y>Z, then N=N-1,
Correction by above-mentioned two step to N finally can determine that N values are constant.
N after correction is substituted into following formula：
Δ=NT-X+Y
The time interval measured between commencing signal Start rising edges and end signal Stop rising edges after being corrected
Δ。
Claims (4)
1. the bearing calibration of hierarchy type TDC using delay chain structure a kind of, the method are：
When commencing signal Start arrives, reference clock counter counts reference clock CLK, meanwhile, commencing signal Start
It is admitted to delay chain, and obtains time interval X, 0≤X≤T of commencing signal Start and reference clock CLK, wherein T indicates ginseng
The time of clock CLK a cycles is examined,
When stop signal Stop arrives, reference clock counter stops counting and obtains commencing signal Start and stop signal
Reference clock cycle number N between Stop, meanwhile, stop signal Stop is admitted to delay chain, and obtain stop signal Stop with
Time interval Y, 0≤Y≤T of reference clock CLK,
It is characterized in that, the bearing calibration includes being corrected to reference clock cycle number N, this approach includes the following steps：
If intermediate judgment value Z meets 0<Z<T,
Step 1：If the rising edge of commencing signal Start is located at the left side of reference clock CLK rising edges and X<Z, then N=N-1,
Then step 2 is executed；
If the rising edge of commencing signal Start is located at the right side of reference clock CLK rising edges and X>Z, then N=N+1, then executes
Step 2；
If the rising edge of commencing signal Start is located at the right side of reference clock CLK rising edges and X<Z, commencing signal Start's is upper
It rises along the left side and X for being located at reference clock CLK rising edges>Z, or X=Z, then N=N, then executes step 2；Step 2：If stopping
The rising edge of stop signal Stop is located at the left side of reference clock CLK rising edges and Y<Z, then N=N+1, completes the correction of N；
If the rising edge of stop signal Stop is located at the right side of reference clock CLK rising edges and Y>Z, then N=N-1, completes the school of N
Just；
If the rising edge of stop signal Stop is located at the left side of reference clock CLK rising edges and Y>Z, the rising of stop signal Stop
Along the right side and Y for being located at reference clock CLK rising edges<Z, or Y=Z, then N=N, completes the correction of N.
2. the bearing calibration of hierarchy type TDC using delay chain structure according to claim 1 a kind of, which is characterized in that
The bearing calibration further includes the correction of the time interval between commencing signal Start and end signal Stop, and this method is：
N after step 2 is corrected substitutes into following formula：
Δ=NT-X+Y
Time interval Δ between commencing signal Start after being corrected and end signal Stop.
3. the bearing calibration of hierarchy type TDC using delay chain structure according to claim 1 or 2 a kind of, feature exist
In,
4. the bearing calibration of hierarchy type TDC using delay chain structure according to claim 2 a kind of, which is characterized in that
Time interval Δ between commencing signal Start and end signal Stop is：
Between time interval, Start failing edges between Start rising edges and Stop rising edges and the time between Stop failing edges
Between the time between time interval or Start rising edges and Stop failing edges between, Start failing edges and Stop rising edges
Every.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109116717A (en) * | 2018-09-28 | 2019-01-01 | 东北大学 | A kind of time interval measurement method based on multiple repairing weld |
| CN109444856A (en) * | 2018-08-31 | 2019-03-08 | 西安电子科技大学 | A kind of number of cycles measuring circuit applied to high resolution time digital quantizer |
| CN110045592A (en) * | 2019-05-17 | 2019-07-23 | 湖北京邦科技有限公司 | Time-correcting method, device, system and computer storage medium |
| CN114047683A (en) * | 2021-11-15 | 2022-02-15 | 星汉时空科技(长沙)有限公司 | Time interval measuring method and device based on orthogonal sampling interpolation |
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| CN109444856A (en) * | 2018-08-31 | 2019-03-08 | 西安电子科技大学 | A kind of number of cycles measuring circuit applied to high resolution time digital quantizer |
| CN109444856B (en) * | 2018-08-31 | 2020-07-31 | 西安电子科技大学 | Integer period measuring circuit applied to high-resolution time-to-digital converter |
| CN109116717A (en) * | 2018-09-28 | 2019-01-01 | 东北大学 | A kind of time interval measurement method based on multiple repairing weld |
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| CN114047683A (en) * | 2021-11-15 | 2022-02-15 | 星汉时空科技(长沙)有限公司 | Time interval measuring method and device based on orthogonal sampling interpolation |
| CN114047683B (en) * | 2021-11-15 | 2022-05-24 | 星汉时空科技(长沙)有限公司 | Time interval measuring method and device based on orthogonal sampling interpolation |
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Effective date of registration: 20230531 Address after: 264299 No. 2, Wenhua West Road, Weihai City, Shandong Province Patentee after: Weihai Harvey Asset Management Co.,Ltd. Patentee after: Wang Chenxu Address before: 264209 No. 2, Wenhua West Road, Shandong, Weihai Patentee before: HARBIN INSTITUTE OF TECHNOLOGY (WEIHAI) |
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Effective date of registration: 20230725 Address after: 264201 Room 201, No. 298-1, Huanhai Road, Sunjiatuan Street, Huancui District, Weihai City, Shandong Province Patentee after: Shandong Tianju Huineng Microelectronics Co.,Ltd. Address before: 264299 No. 2, Wenhua West Road, Weihai City, Shandong Province Patentee before: Weihai Harvey Asset Management Co.,Ltd. Patentee before: Wang Chenxu |