CN108428739A - 一种沟槽绝缘栅双极晶体管 - Google Patents

一种沟槽绝缘栅双极晶体管 Download PDF

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CN108428739A
CN108428739A CN201710082211.8A CN201710082211A CN108428739A CN 108428739 A CN108428739 A CN 108428739A CN 201710082211 A CN201710082211 A CN 201710082211A CN 108428739 A CN108428739 A CN 108428739A
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朱江
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

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Abstract

本发明提供一种沟槽绝缘栅双极晶体管；本发明将栅极与漂移层之间设置半导体结，去除沟槽栅绝缘层的峰值电场，提供栅与背电极保护装置，去除雪崩发生风险，形成极端情况下导电通路；本发明在沟槽底部设置反型区，抑制沟槽栅绝缘层的峰值电场，提高器件可靠性。

Description

一种沟槽绝缘栅双极晶体管
技术领域
本发明涉及到一种沟槽绝缘栅双极晶体管。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,简称IGBT)是一种集金属氧化物半导体场效应管(MOSFET)的栅电极电压控制特性和双极晶体管(BJT)的低导通电阻特性于一身的半导体功率器件，要求高可靠性、电压控制、输入阻抗大、驱动功率小、导通电阻小、开关损耗低及工作频率高等电特性，其应用非常广泛，包括飞机、舰船、交通、电网等支柱产业，被称为电力电子行业里的“CPU”。
发明内容
本发明提供一种沟槽绝缘栅双极晶体管及其制备方法。
一种沟槽绝缘栅双极晶体管，背P型发射区，为P型半导体材料；N型基区，为N型半导体材料，位于背P型发射区之上，N型基区内底部可以设置高浓度掺杂缓冲层；多个沟槽，位于N型基区表面，向下贯穿背P型发射区，沟槽侧壁设置绝缘层，沟槽内下部设置N型半导体材料，沟槽内N型半导体材料上部设置P型半导体材料，沟槽内上部设置栅极多晶硅，栅极多晶硅与沟槽内P型半导体材料相连，栅极多晶硅可以为N型多晶硅，也可以为P型多晶硅；P型基区和N+型区，位于沟槽之间N型基区内上部。N型基区与沟槽内P型半导体材料在反向偏压下可以形成电荷补偿。P型基区设置向下延伸电荷补偿P型半导体材料，电荷补偿P型半导体材料不与沟槽接触。槽内下部设置N型半导体材料内底部设置P型半导体材料。背P型发射区可以为P型多晶硅半导体材料，P型多晶硅可以在N型基区底部形成轻掺杂反型层。
一种沟槽绝缘栅双极晶体管，背P型发射区，为P型半导体材料；N型基区，为N型半导体材料，位于背P型发射区之上，N型基区内底部可以设置高浓度掺杂缓冲层；多个沟槽，位于N型基区表面，沟槽内侧壁设置绝缘层，沟槽内下部设置P型半导体材料，沟槽内上部设置栅极多晶硅，栅极多晶硅可以为N型多晶硅，也可以为P型多晶硅，栅极多晶硅与沟槽内P型半导体材料之间设置绝缘层隔离；P型基区和N+型区，位于沟槽之间N型基区内上部。P型基区设置向下延伸电荷补偿P型半导体材料，电荷补偿P型半导体材料不与沟槽接触；沟槽内下部设置P型半导体材料可以为P型多晶硅。背P型发射区可以为P型多晶硅，P型多晶硅可以在N型基区底部形成轻掺杂反型层。
上述沟槽绝缘栅双极晶体管，将栅极与漂移层之间设置半导体结或者在沟槽底部设置反型区，去除沟槽栅绝缘层的峰值电场或形成极端情况下导电通路，提高器件可靠性。
附图说明
图1为本发明的第一种绝缘栅双极晶体管剖面示意图；
图2为本发明的第二种绝缘栅双极晶体管剖面示意图；
图3为本发明的第三种绝缘栅双极晶体管剖面示意图；
图4为本发明的第四种绝缘栅双极晶体管剖面示意图；
图5为本发明的第五种绝缘栅双极晶体管剖面示意图；
图6为本发明的第六种绝缘栅双极晶体管剖面示意图；
其中，1、背P型发射区；2、背N型半导体材料；3、P型半导体材料；4、N型半导体材料；5、N型基区；6、P型基区；7、N+型区；8、绝缘层；9、栅极多晶硅。
具体实施方式
图1为本发明的一种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型多晶硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；背P型发射区与N型基区之间设置反型层P型半导体材料3，为背P型发射区扩散形成；沟槽位于N型基区表面，向下贯穿背P型发射区；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部设置背N型半导体材料2，为N型高浓度掺杂硅半导体材料；沟槽内栅极多晶硅与背N型半导体材料之间设置P型半导体材料3，为P型硅半导体材料。本实例制造方法包括为进行背部减薄，减薄至上表面沟槽。
图2为本发明的第二种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；沟槽位于N型基区表面，向下贯穿背P型发射区；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部从下向上设置P型半导体材料3和N型半导体材料4，P型半导体材料为高浓度掺杂P型硅半导体材料，N型半导体材料4为N型硅半导体材料；沟槽内栅极多晶硅下部设置P型半导体材料3，为P型硅半导体材料。
图3为本发明的第三种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型多晶硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；背P型发射区与N型基区之间设置反型层P型半导体材料3，为背P型发射区扩散形成；沟槽位于N型基区表面，向下贯穿背P型发射区；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部从下向上设置P型半导体材料3和N型半导体材料4，P型半导体材料为高浓度掺杂P型硅半导体材料，N型半导体材料4为N型硅半导体材料；沟槽内栅极多晶硅下部设置P型半导体材料3，为P型硅半导体材料。
图4为本发明的第四种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；沟槽位于N型基区表面，沟槽底部位于N型基区中；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部设置P型半导体材料3为P型多晶硅，包括为重掺杂或轻掺杂P型多晶硅，沟槽内下部设置P型半导体材料3还可以为P型硅半导体材料；沟槽内设置绝缘层对沟槽内栅极多晶硅和P型半导体材料3隔离。
图5为本发明的第五种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型多晶硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；背P型发射区与N型基区之间设置反型层P型半导体材料3，为背P型发射区扩散形成；沟槽位于N型基区表面，沟槽底部位于N型基区中；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部设置P型半导体材料3为P型多晶硅，包括为重掺杂或轻掺杂P型多晶硅，沟槽内下部设置P型半导体材料3还可以为P型硅半导体材料；沟槽内设置绝缘层对沟槽内栅极多晶硅和P型半导体材料3隔离。
图6为本发明的第六种绝缘栅双极晶体管的剖面图，背P型发射区1，为高浓度掺杂P型多晶硅材料；N型基区5，为N型半导体硅材料，N型基区内底部设置高浓度掺杂缓冲层；背P型发射区与N型基区之间设置反型层P型半导体材料3，为背P型发射区扩散形成；沟槽位于N型基区表面，沟槽底部位于N型基区5中；沟槽内壁设置绝缘层8，为二氧化硅；沟槽之间N型基区内上部设置P型基区6和N+型区7，为硅半导体材料；P型基区设置向下延伸电荷补偿P型半导体硅材料；沟槽内上部设置栅极多晶硅9，为N型多晶硅；沟槽内下部设置P型半导体材料3为P型多晶硅，包括为重掺杂或轻掺杂P型多晶硅，沟槽内下部设置P型半导体材料3还可以为P型硅半导体材料；沟槽内设置绝缘层对沟槽内栅极多晶硅和P型半导体材料3隔离。
通过上述实例阐述了本发明，同时也可以采用其它实例实现本发明，本发明不局限于上述具体实例，因此本发明由所附权利要求范围限定。

Claims (3)

1.一种沟槽绝缘栅双极晶体管，其特征在于：包括：
背P型发射区，为P型半导体材料；
N型基区，为N型半导体材料，位于背P型发射区之上；
多个沟槽，位于N型基区表面，向下贯穿背P型发射区，沟槽侧壁设置绝缘层，沟槽内下部设置N型半导体材料，沟槽内N型半导体材料上部设置P型半导体材料，沟槽内上部设置栅极多晶硅，栅极多晶硅与沟槽内P型半导体材料相连；
P型基区和N+型区，位于沟槽之间N型基区内上部。
2.如权利要求1所述的半导体装置，其特征在于：所述的槽内下部设置N型半导体材料内底部设置P型半导体材料。
3.一种沟槽绝缘栅双极晶体管，其特征在于：包括：
背P型发射区，为P型半导体材料；
N型基区，为N型半导体材料，位于背P型发射区之上；
多个沟槽，位于N型基区表面，沟槽内侧壁设置绝缘层，沟槽内下部设置P型半导体材料，沟槽内上部设置栅极多晶硅，栅极多晶硅与沟槽内P型半导体材料之间设置绝缘层隔离，沟槽内P型半导体材料与N型基区相连；
P型基区和N+型区，位于沟槽之间N型基区内上部。
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