CN108428465A - Static RAM（SRAM） - Google Patents
Static RAM（SRAM） Download PDFInfo
- Publication number
- CN108428465A CN108428465A CN201810270384.7A CN201810270384A CN108428465A CN 108428465 A CN108428465 A CN 108428465A CN 201810270384 A CN201810270384 A CN 201810270384A CN 108428465 A CN108428465 A CN 108428465A
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- Prior art keywords
- pmos
- nmos
- reading unit
- cell
- sram
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
Include the reading unit that the r/w cell being made of 6 transmission MOS and 2 transmission MOS are formed the invention discloses a kind of static RAM (SRAM), states reading unit and be made of concatenated first PMOS P1 and the 2nd PMOS P2.First end of the first PMOS P1 first ends for reading unit as the reading unit, second end of the second end of first PMOS P1 as the reading unit, the third end of first PMOS P1 connects the first end of the 2nd PMOS P2, the second end of 2nd PMOS P2 connects r/w cell as the third end of the reading unit, and the third end of the 2nd PMOS P2 connects ground as the 4th end of the reading unit.Signal read error caused by the invention can avoid leakage current is excessive due to RPBL (bit line for reading unit) judges.
Description
Technical field
The present invention relates to integrated circuit fields, are deposited more particularly to a kind of static random-access being made of 8 transfer tubes
Reservoir (SRAM).
Background technology
Static RAM (Static Random-Access Memory, SRAM) is random access memory
One kind.SRAM is more more expensive than dynamic random access memory (DRAM) but more quick, very low-power consumption (is especially
In idle state).Therefore either power consumption requirements are low or the two haves both at the same time for bandwidth requirement height for SRAM first choices.
As shown in Figure 1, a kind of static random access memory (SRAM) being made of 8 transfer tubes, r/w cell is by 4
NMOS and 2 PMOS composition, reads unit and is made of 2 NMOS.The r/w cell of the SRAM include the first~the 4th NMOS N1~
N4, the first PMOS and the 2nd PMOS P1, P2；
First NMOS N1 first ends connect the 4th NMOS N4 as the r/w cell first end, the first NMOS N1 second ends
Second end, the first NMOS N1 thirds end connect the first PMOS P1 thirds end, the 2nd PMOS P2 second ends, the 2nd NMOS N2 the
One end and the 3rd NMOS N3 second ends；
First PMOS P1 first ends connect the 2nd PMOS P2 first ends and are connected, the first PMOS P1 second ends connection second
NMOS N2 second ends, the 2nd PMOS P2 thirds end, the 3rd NMOS N3 first ends and the 4th NMOS N4 thirds end；
4th NMOS N4 first ends are as the r/w cell second end；
3rd NMOS N3 first ends connect as the r/w cell third end and read unit；
The 2nd N2 thirds ends NMOS are connected with the 3rd NMOS N3 thirds end as the 4th end of r/w cell connection ground.
That the SRAM reads unit includes the 5th NMOS N5 and the 6th NMOS N6, and the 5th NMOS N5 first ends are as the reading
The first end of unit, the second end of the second end of the 5th NMOS N5 as the reading unit, the third end connection of the 5th NMOS N5
The first end of 6th NMOS N6, the second end of the 6th NMOS N6 connect r/w cell as the third end of the reading unit, and the 6th
The third end of NMOS N6 connects ground as the 4th end of the reading unit.
The static RAM (SRAM) is read unit and is made of NMOS components.As shown in Fig. 2, reading unit
Bit line leakage group become Iboff (substrate leakage current bulk leakage)+Isoff (source leakage currents sourceleakage)+
Igoff (gate leakage current gate leakage).As shown in figure 3, when in unit reading patterned signal is read, RPBL (reads unit
Bit line)=1V, Selection bit (WL=on) signal be 0, others (N-1) non-selection bit (WL=
Off it is 1* (Iboff+Isoff)+(N-1) * (Iboff+Isoff+ that) signal, which is all the electric current of 1, RPBL (bit line for reading unit),
Igoff),Fig 3.RPBL (bit line for reading unit) leakage current is excessive, easy tos produce the situation of signal read error judgement.
Invention content
The technical problem to be solved in the present invention is to provide one kind to be avoided that since RPBL (bit line for reading unit) electric leakage is flowed through
The big static RAM (SRAM) for causing signal read error to judge.
In order to solve the above technical problems, static RAM (SRAM) provided by the invention, including transmitted by 6
The reading unit of the r/w cell of MOS compositions and 2 transmission MOS compositions, the reading unit is by concatenated first PMOS P1 and second
PMOS P2 compositions.
Wherein, first end of the first PMOS P1 first ends for reading unit as the reading unit, the first PMOS P1's
Second end of the second end as the reading unit, the first end of the 2nd PMOS P2 of third end connection of the first PMOS P1, second
The second end of PMOS P2 connects r/w cell as the third end of the reading unit, and the third end of the 2nd PMOS P2 is as the reading unit
The 4th end connection ground.
Wherein, the source electrode of the first PMOS P1 and the 2nd PMOS P2 is as its first end, the first PMOS P1 and the 2nd PMOS
The grid of P2 is as its second end, and the drain electrode of the first PMOS P1 and the 2nd PMOS P2 are as its third end.
Wherein, it is PMOS that it is the transmission of NMOS, the 5th and the 6th MOS that the first of the r/w cell~4th, which transmits MOS,.
Wherein, the described first~the 4th transmission NMOS is respectively designated as the first~the 4th NMOS N1~N4, the 5th and the 6th
Transmission MOS is respectively designated as the 3rd PMOS and the 4th PMOS P3, P4；
First NMOS N1 first ends connect the 4th NMOS N4 as the r/w cell first end, the first NMOS N1 second ends
Second end, the first NMOS N1 thirds end connect the 3rd PMOS P3 thirds end, the 4th PMOS P4 second ends, the 2nd NMOS N2 the
One end and the 3rd NMOS N3 second ends；
3rd PMOS P3 first ends connect the 4th PMOS P4 first ends and are connected, the 3rd PMOS P3 second ends connection second
NMOS N2 second ends, the 4th PMOS P4 thirds end, the 3rd NMOS N3 first ends and the 4th NMOS N4 thirds end；
4th NMOS N4 first ends are as the r/w cell second end；
3rd NMOS N3 first ends connect as the r/w cell third end and read unit；
The 2nd N2 thirds ends NMOS are connected with the 3rd NMOS N3 thirds end as the 4th end of r/w cell connection ground.
Wherein, the drain electrode of the first~the 4th NMOS N1~N4 is as its first end, the first~the 4th NMOS N1~N4's
Grid is as its second end, and the source electrode of the first~the 4th NMOS N1~N4 is as its third end.
Wherein, the source electrode of the 3rd PMOS and the 4th PMOS P3, P4 is as its first end, the 3rd PMOS and the 4th PMOSP3,
The grid of P4 is as its second end, and the drain electrode of the 3rd PMOS and the 4th PMOS P3, P4 are as its third end.
In order to improve the above problem, the electric leakage for reading unit extreme operating condition is as reduced, 8 transfer tube static random-access are deposited
Reservoir (SRAM) reading unit is changed to 2 MOS components and is formed.With reference to shown in figure 4-6, it is Isoff that PMOS, which reads cell bit line electric leakage,
The present invention's operates in reading unit extreme operating condition, and RPBL=1V, Selection bit (WL=on) signal is 1, others
(N-1) electric leakage that non-selection bit (WL=off) signal is all 0, Pfet RPBL is 1* (Isoff+Igoff)+(N-
1)*(Isoff).The present invention can reduce the electric leakage source of RPBL endpoints, read unit extreme operating condition electric leakage source, 1* (Iboff+
Isoff)+(N-1) * (Iboff+Isoff+Igoff) improvement is 1* (Isoff+Igoff)+(N-1) * (Isoff), reduces electric leakage
The probability of false judgment when source can improve reading signal.
Description of the drawings
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：
Fig. 1 is a kind of structural schematic diagram of existing 8 transfer tube static RAM (SRAM).
Fig. 2 is the principle schematic of Fig. 1.
Fig. 3 is the use reference view of Fig. 1.
Fig. 4 is the structural schematic diagram of static RAM of the present invention (SRAM).
Fig. 5 is the principle schematic of Fig. 4.
Fig. 6 is the use reference view of Fig. 4.
Reference sign
N1~N6 is NMOS
P1~P4 is PMOS
RPBL is to read cell bit line
RPWL is to read cell word lines
RPPG：READ PORT PASS PGTE
RPPD：READ PORT PULL DOWN
na：NODE A (SRAM inner terminal A)
nb：NODE B (SRAM inner terminal B)
Nw:N well (N wells)
Pw:P well (P wells)
BL is r/w cell bit line
BLB is r/w cell bit line B
WL is r/w cell wordline
Vdd is supply voltage
Vss is ground connection
Specific implementation mode
As shown in Figure 1, static RAM SRAM provided by the invention, includes being write by what 6 transmission MOS were formed
The reading unit of unit and 2 transmission MOS compositions；
The reading unit is made of concatenated first PMOS P1 and the 2nd PMOS P2, the first PMOS for reading unit
P1 source electrodes read the bit line of unit as the first end RPBL of the reading unit, the grid of the first PMOS P1 as the reading unit the
Two end RPWL read cell word lines, the source electrode of the 2nd PMOS P2 of drain electrode connection of the first PMOS P1, and the grid of the 2nd PMOSP2 is made
R/w cell is connected for the third end of the reading unit, the drain electrode of the 2nd PMOS P2 connects ground as the 4th end of the reading unit.
The r/w cell includes the first~the 4th NMOS N1~N4, the 5th PMOS and the 6th PMOS P3, P4.
First NMOS N1 drain electrodes are used as the r/w cell first end r/w cell bit line, the first NMOS N1 grids connection the 4th
NMOS N4 grids, the first the 3rd PMOS P3 drain electrodes of NMOS N1 drain electrode connections, the 4th PMOS P4 grids, the 2nd NMOS N2 leakages
Pole and the 3rd NMOS N3 grids；
3rd PMOS P3 source electrodes connect the 4th PMOS P4 source electrodes and are connected, and the 3rd PMOS P3 grids connect the 2nd NMOSN2
Grid, the 4th PMOS P4 drain electrodes, the 3rd NMOS N3 drain electrodes and the 4th NMOS N4 source electrodes；
4th NMOS N4 first ends are as r/w cell second end BLB r/w cell bit lines B；
3rd NMOS N3 drain electrodes read unit as r/w cell third end connection；
2nd NMOS N2 source electrodes and the 3rd NMOS N3 source electrodes are connected as the 4th end of r/w cell connection ground.
Above by specific implementation mode and embodiment, invention is explained in detail, but these are not composition pair
The limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of static RAM (SRAM) includes by 6 transmission MOS r/w cells formed and 2 transmission MOS groups
At reading unit, it is characterised in that：The reading unit is made of concatenated first PMOS (P1) and the 2nd PMOS (P2).
2. static RAM (SRAM) as described in claim 1, it is characterised in that：It is described to read the first of unit
First end of PMOS (P1) first ends as the reading unit, the second end of the second end of the first PMOS (P1) as the reading unit,
The third end of first PMOS (P1) connects the first end of the 2nd PMOS (P2), and the second end of the 2nd PMOS (P2) is as the reading unit
Third end connect r/w cell, the third end of the 2nd PMOS (P2) connects ground as the 4th end of the reading unit.
3. static RAM (SRAM) as claimed in claim 2, it is characterised in that：First PMOS (P1) and second
The source electrode of PMOS (P2) is as its first end, and the grid of the first PMOS (P1) and the 2nd PMOS (P2) is as its second end, and first
The drain electrode of PMOS (P1) and the 2nd PMOS (P2) are as its third end.
4. static RAM (SRAM) as claimed in claim 2, it is characterised in that：The first of the r/w cell~
4th transmission MOS is that the transmission of NMOS, the 5th and the 6th MOS is PMOS.
5. static RAM (SRAM) as claimed in claim 4, it is characterised in that：Described first~the 4th transmission
NMOS, which is respectively designated as the first~the 4th NMOS (N1~N4), the 5th and the 6th, to be transmitted MOS and is respectively designated as the 3rd PMOS and the
Four PMOS (P3, P4)；
For first NMOS (N1) first ends as the r/w cell first end, the first NMOS (N1) second end connects the 4th NMOS (N4) the
Two ends, the first NMOS (N1) thirds end connect the 3rd PMOS (P3) thirds end, the 4th PMOS (P4) second end, the 2nd NMOS (N2)
First end and the 3rd NMOS (N3) second end；
3rd PMOS (P3) first end connects the 4th PMOS (P4) first end and is connected, the 3rd PMOS (P3) second end connection second
NMOS (N2) second end, the 4th PMOS (P4) thirds end, the 3rd NMOS (N3) first ends and the 4th NMOS (N4) thirds end；
4th NMOS (N4) first ends are as the r/w cell second end；
3rd NMOS (N3) first ends connect as the r/w cell third end and read unit；
2nd (N2) the third ends NMOS are connected with the 3rd NMOS (N3) thirds end as the 4th end of r/w cell connection ground.
6. static RAM (SRAM) as claimed in claim 5, it is characterised in that：First~the 4th NMOS (N1
~N4) drain electrode as its first end, the grid of the first~the 4th NMOS (N1~N4) is as its second end, the first~the 4th
The source electrode of NMOS (N1~N4) is as its third end.
7. static RAM (SRAM) as claimed in claim 5, it is characterised in that：3rd PMOS and the 4th PMOS
The source electrode of (P3, P4) is as its first end, and the grid of the 3rd PMOS and the 4th PMOS (P3, P4) are as its second end, third
The drain electrode of PMOS and the 4th PMOS (P3, P4) are as its third end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810270384.7A CN108428465A (en) | 2018-03-29 | 2018-03-29 | Static RAM（SRAM） |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810270384.7A CN108428465A (en) | 2018-03-29 | 2018-03-29 | Static RAM（SRAM） |
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| Publication Number | Publication Date |
|---|---|
| CN108428465A true CN108428465A (en) | 2018-08-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810270384.7A Pending CN108428465A (en) | 2018-03-29 | 2018-03-29 | Static RAM（SRAM） |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920460A (en) * | 2019-02-22 | 2019-06-21 | 中国科学院微电子研究所 | SRAM memory cell circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
| CN104464794A (en) * | 2014-11-13 | 2015-03-25 | 无锡星融恒通科技有限公司 | Non-volatile SRAM (static random access memory) storage unit circuit |
| CN106575521A (en) * | 2014-08-29 | 2017-04-19 | 高通股份有限公司 | Silicon germanium read port for a static random access memory register file |
-
2018
- 2018-03-29 CN CN201810270384.7A patent/CN108428465A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
| CN106575521A (en) * | 2014-08-29 | 2017-04-19 | 高通股份有限公司 | Silicon germanium read port for a static random access memory register file |
| CN104464794A (en) * | 2014-11-13 | 2015-03-25 | 无锡星融恒通科技有限公司 | Non-volatile SRAM (static random access memory) storage unit circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920460A (en) * | 2019-02-22 | 2019-06-21 | 中国科学院微电子研究所 | SRAM memory cell circuit |
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Application publication date: 20180821 |
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