CN105489241A - Static random access memory - Google Patents
Static random access memory Download PDFInfo
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- CN105489241A CN105489241A CN201410539431.5A CN201410539431A CN105489241A CN 105489241 A CN105489241 A CN 105489241A CN 201410539431 A CN201410539431 A CN 201410539431A CN 105489241 A CN105489241 A CN 105489241A
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Abstract
The invention discloses a static random access memory. The static random access memory comprises a first bit line, a first transistor, N storage units, N second transistors, N first word lines, a second bit line, N fourth transistors and N second word lines, wherein the first transistor is connected between the first bit line and a power supply or the ground through the source and the drain; each of the N storage units is used for storing a level state, the level state comprises a high level and a low level, and N is greater than or equal to 1; the N second transistors are in one-to-one correspondence with the N storage units, and each of the N second transistors is connected between the corresponding storage unit and the gate of the first transistor through the source and the drain; the N first word lines are in one-to-one correspondence with the N second transistors; the third transistor is connected between the second bit line and the power supply or the ground through the source and the drain; the N fourth transistors are in one-to-one correspondence with the N storage units; and the N second word lines are in one-to-one correspondence with the N fourth transistors. According to the static random access memory, the problem of low stability of data reading operation of the static random access memory is solved.
Description
Technical field
The application relates to memory area, in particular to a kind of static RAM.
Background technology
Static RAM (SRAM) can realize read/write operation fast.Fig. 1 is the schematic diagram of a kind of 6T static RAM according to prior art, as shown in Figure 1, each memory module of this 6T static RAM comprises 6 transistors, is transistor PG-1, transistor PG-2, transistor PU-1, transistor PD-1, transistor PU-2 and transistor PD-2 respectively.Transistor PU-1, transistor PD-1, transistor PU-2, transistor PD-2, power vd D and ground VSS form storage unit jointly, for memory level state, i.e. high level state and low level state, this storage unit comprises two memory nodes, that memory node Q and memory node QN, memory node Q and memory node QN store a pair contrary level state respectively.Wordline WL is connected to the grid of transistor PG-1 and transistor PG-2, reads level state for controlling or writes level state to storage unit from storage unit.Transistor PG-1 is connected between the memory node Q of storage unit and bit line BL by source electrode and drain electrode, and transistor PG-2 is connected between the memory node QN of storage unit and bit line BLB by source electrode and drain electrode.
When wordline WL is high level, transistor PG-1 and transistor PG-2 conducting simultaneously, bit line BL can read the level state of memory node Q, and bit line BLB can read the level state of memory node QN, realizes reading data from storage unit.Same, such as to storage unit write high level " 1 ", first bit line BL is added high level, corresponding bit line BLB adds low level, when wordline WL is high level, and transistor PG-1 and transistor PG-2 conducting simultaneously, the level state of bit line BL, bit line BLB transfers to memory node Q and memory node QN respectively, make memory node Q be high level state " 1 ", corresponding memory node QN is low level state " 0 ", realizes to storage unit write data.
This 6T static RAM can only realize single port read/write, and read-write efficiency is lower, and the storage node voltage of this T static RAM can be subject to the impact of read operation, and static noise margin value is less, and storer stability is too low.
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art, as shown in Figure 2, this dual-port static random access memory is on the basis of the 6T static RAM shown in Fig. 1, add transistor PGA2 and transistor PGB2, and bit line BL2, BL1B and wordline WLB, wherein, transistor PGA2 is connected to bit line BL2 by source electrode or drain electrode, transistor PGB2 is connected to bit line BL1B by source electrode or drain electrode, and transistor PGA2 and transistor PGB2 grid are connected to wordline WLB.In figure, other elements are corresponding with element in Fig. 1 respectively, and bit line BL1 corresponds to bit line BL, bit line BL2B and corresponds to transistor PG-1, transistor PGB1 corresponding to transistor PG-2, wordline WLA corresponding to wordline WL corresponding to bit line BLB, transistor PGA1.
This dual-port static random access memory can realize simultaneously from two port read/write, namely can simultaneously from two port write data or from two port sense datas, its read-write efficiency is improved, but the read-write operation of two of this dual-port static random access memory ports can influence each other, its stability is also lower than traditional 6T static RAM.
In order to improve static noise margin and the stability of static RAM, 8T static RAM and 10T static RAM are manufactured, Fig. 3 is a kind of 8T static RAM schematic diagram according to prior art, and Fig. 4 is a kind of 10T static RAM schematic diagram according to prior art.
As shown in Figure 3, 8T static RAM by adding transistor RPD and transistor RPG on the basis of the 6T static RAM shown in Fig. 1, bit line RBL is connected to memory node QN via transistor RPD and transistor RPG, the grid of transistor RPG is connected to wordline RWL, this wordline RWL is used for controlling sense data from static RAM, transistor PG-1 and transistor PG-2 is connected to wordline WWL, bit line WWL is used for controlling to write data in static RAM, these other parts of 8T static RAM are with the 6T static RAM shown in Fig. 1.Due to the existence of transistor RPD and transistor RPG, make read port voltage can not have influence on the voltage of memory node QN, thus the stability of static RAM is improved, static noise margin value becomes large, but this 8T static RAM can only the read operation of fill order's port, and reading efficiency is lower.
As shown in Figure 4,10T static RAM is improved on 8T static RAM basis, two transistors are added in the position of transistor RPD and transistor RPG symmetry, and these two transistors are connected to wordline RWL and bit line RBL, bit line RBLB corresponds to the bit line RBL in Fig. 3.Other parts of this 10T static RAM are with the 8T static RAM shown in Fig. 3.This 10T static RAM can realize differential type and read, and improve the access speed of storer, and have higher stability, but each storage unit of this 10T static RAM comprises 10 transistors, and area is comparatively large, is unfavorable for Integrated manufacture.
To sum up, static memory (SRAM) can realize read/write operation fast, but reading static noise margin (RSNM) becomes worse and worse, and stability is more and more lower.Dual-port (2RW, 2 reading-writing port) static memory to read static noise margin poorer than traditional 6T static memory, although this dual-port (2RW) static memory has access speed faster.In order to realize highly reading static noise margin, invented 8T static memory and 10T static memory, but its access speed and cellar area are difficult to meet the demands.
For the problem that static RAM read data operation stability in prior art is low, at present effective solution is not yet proposed.
Summary of the invention
The embodiment of the present application provides a kind of static RAM, to solve the low problem of static RAM read data operation stability.
According to an aspect of the embodiment of the present application, provide a kind of static RAM, comprising: the first bit line; The first transistor, is connected between the first bit line and power supply or ground by source electrode and drain electrode; N number of storage unit, each in this N number of storage unit is for memory level state, and level state comprises high level and low level, and N is more than or equal to 1; N number of transistor seconds, with N number of storage unit one_to_one corresponding, each in N number of transistor seconds is connected between corresponding storage unit and the grid of the first transistor by source electrode and drain electrode; N number of first wordline, with N number of transistor seconds one_to_one corresponding, each in N number of first wordline is connected to the grid of corresponding transistor seconds, reads level state for controlling from the storage unit of correspondence; Second bit line; Third transistor, is connected between the second bit line and power supply or ground by source electrode and drain electrode; N number of 4th transistor, with N number of storage unit one_to_one corresponding, wherein, each in N number of 4th transistor is connected between corresponding storage unit and the grid of third transistor by source electrode and drain electrode; And N number of second wordline, with N number of 4th transistor one_to_one corresponding, each in N number of second wordline is connected to the grid of the 4th corresponding transistor, reads level state for controlling from the storage unit of correspondence.
Further, each storage unit in N number of storage unit comprises: the first memory node, for storing the level state with the level state homophase of each storage unit; Second memory node, for storing the level state anti-phase with the level state of each storage unit; Wherein, each in N number of transistor seconds is connected between the first memory node in corresponding storage unit and the grid of the first transistor by source electrode and drain electrode, or each in N number of transistor seconds is connected between the second memory node in corresponding storage unit and the grid of the first transistor by source electrode and drain electrode.
Further, each storage unit in N number of storage unit comprises: the first phase inverter, is connected between the first memory node and the second memory node; Second phase inverter, is oppositely connected between the first memory node and the second memory node relative to the first phase inverter.
Further, each storage unit in N number of storage unit comprises: a PMOS, is connected between power supply and the first memory node by source electrode and drain electrode, and the grid of a PMOS is connected to the second memory node; One NMOS, is connected between the first memory node and ground by source electrode and drain electrode, and the grid of a NMOS is connected to the second memory node; 2nd PMOS, is connected between power supply and the second memory node by source electrode and drain electrode, and the grid of the 2nd PMOS is connected to the first memory node; 2nd NMOS, is connected between the second memory node and ground by source electrode and drain electrode, and the grid of the 2nd NMOS is connected to the first memory node.
Further, this static RAM also comprises: the 3rd bit line; N number of 5th transistor, with N number of storage unit one_to_one corresponding, each in N number of 4th transistor is connected between corresponding storage unit and the 3rd bit line by source electrode and drain electrode; 4th bit line; N number of 6th transistor, with N number of storage unit one_to_one corresponding, each in N number of 6th transistor is connected between corresponding storage unit and the 4th bit line by source electrode and drain electrode; N number of 3rd wordline, with N number of 5th transistor and N number of 6th transistor one_to_one corresponding, each in N number of 3rd wordline is connected to the 5th corresponding transistor and the grid of the 6th transistor, for controlling the storage unit write level state reading level state from the storage unit of correspondence and/or control to correspondence.
Further, this static RAM also comprises: processor, connect the first bit line and N number of first wordline, for exporting control signal to arbitrary first wordline in N number of first wordline, and the level state of the storage unit corresponding with arbitrary first wordline is read from the first bit line, control signal is for controlling the conducting between the source electrode of transistor seconds corresponding to arbitrary first wordline and drain electrode.
Further, the first transistor and transistor seconds are NMOS.
In the static RAM that the application provides, keep the level state of storage unit constant when realizing reading static memory data by the first wordline control the first transistor and transistor seconds, reach the object improving static RAM read data operation stability, and then solve the low technical matters of static RAM read data operation stability.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present application, and form a application's part, the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 is the schematic diagram of a kind of 6T static RAM according to prior art;
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art;
Fig. 3 is a kind of 8T static RAM schematic diagram according to prior art;
Fig. 4 is a kind of 10T static RAM schematic diagram according to prior art;
Fig. 5 is the schematic diagram of the static RAM according to the embodiment of the present application; And
Fig. 6 is the schematic diagram of the memory module according to the embodiment of the present application.
Embodiment
Hereinafter also describe the application in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
The application's scheme is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the embodiment of the application's part, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all should belong to the scope of the application's protection.
It should be noted that, term " first ", " second " etc. in the instructions of the application and claims and above-mentioned accompanying drawing are for distinguishing similar object, and need not be used for describing specific order or precedence.Should be appreciated that the data used like this can be exchanged in the appropriate case, so as the embodiment of the application described herein can with except here diagram or describe those except order implement.In addition, term " comprises " and " having " and their any distortion, intention is to cover not exclusive comprising, such as, contain those steps or unit that the process of series of steps or unit, method, system, product or equipment is not necessarily limited to clearly list, but can comprise clearly do not list or for intrinsic other step of these processes, method, product or equipment or unit.
According to the embodiment of the present application, provide a kind of static RAM, Fig. 5 is the static RAM schematic diagram according to the embodiment of the present application.
As shown in Figure 5, this static RAM comprises: the first bit line 20, the first transistor 10, N number of storage unit, N number of transistor seconds, N number of first wordline, the second bit line 40, third transistor 30, N number of 4th transistor and N number of second wordline.
The first transistor 10, is connected between the first bit line 20 and power supply or ground by source electrode and drain electrode;
N number of storage unit, each in N number of storage unit is for memory level state, and level state comprises high level and low level, and N is more than or equal to 1;
N number of transistor seconds, with N number of storage unit one_to_one corresponding, each in N number of transistor seconds is connected between corresponding storage unit and the grid of the first transistor 10 by source electrode and drain electrode;
N number of first wordline, with N number of transistor seconds one_to_one corresponding, each in N number of first wordline is connected to the grid of corresponding transistor seconds, reads level state for controlling from the storage unit of correspondence.
Third transistor 30, is connected between the second bit line and power supply or ground by source electrode and drain electrode;
N number of 4th transistor, with N number of storage unit one_to_one corresponding, wherein, each in N number of 4th transistor is connected between corresponding storage unit and the grid of third transistor by source electrode and drain electrode.
N number of second wordline, with N number of 4th transistor one_to_one corresponding, each in N number of second wordline is connected to the grid of the 4th corresponding transistor, reads level state for controlling from the storage unit of correspondence.
As shown in Figure 5, this static random access memory comprises N memory module, and each memory module 50 in N number of memory module comprises storage unit 501, transistor seconds 502, first wordline the 507, four transistor 504 and the second wordline 508.Followingly the present embodiment to be described for example according to the memory module of in N number of storage unit 50.
The source ground of the first transistor 10, this the first transistor 10 grid is connected to the source electrode of transistor seconds 502 via internal wiring ILB, the drain electrode of this first transistor 10 is connected to the first bit line 20, first bit line 20 is as output line, be connected with external circuits (not shown), by the data that store in the first bit line 20 output storage or outer input data is write to storer.The drain electrode of transistor seconds 502 is connected to storage unit 501 first end, grid is connected to the first wordline 507, this transistor seconds 502 is as the read operation transmission channel of storer, when the first wordline 507 high level, this transistor seconds 502 conducting, the data that storage unit 501 stores just transfer to the first bit line 20 by transistor seconds 502, realize the read operation of memory data.The source electrode of third transistor 30 is connected to ground, and the drain electrode of third transistor 30 is connected to the second bit line 40, and the grid of third transistor 30 is connected to the source electrode of the 4th transistor 504 via internal wiring ILA.The drain electrode that the grid of the 4th transistor 504 is connected to the second wordline the 508, four transistor 504 is connected to storage unit 501 second end.
In the data procedures reading this static RAM, when the first wordline 507 high level, transistor seconds 502 conducting, the level state of storage unit 501 can be read from the first bit line 20, owing to being off state between the first transistor 10 grid and source electrode, the grid of the first transistor 10 does not have electric current to flow through, and the read operation therefore performed by transistor seconds 502 and the first transistor 10 can keep the level state of storage unit 501 constant.Same, when the second wordline 508 is high level, 4th transistor 504 conducting, the level state of cell stores can be read by the second bit line 40, and the obstructed electric current of the grid of third transistor 30, therefore the operation of this reading storer also can not have influence on the magnitude of voltage of the second end of the storage unit 501 of static RAM.This static memory is by the first bit line 20, the first transistor 10 and transistor seconds 502 are as the first read port, by third transistor 30, 4th transistor 504 and the second bit line 40 are as the second read port, data are read from static memory, thus realize two read ports and perform read data operation simultaneously, improve the efficiency from memory read data, and the magnitude of voltage at storage unit two ends can both be kept in reading the data constant, improve the stability reading data from static RAM, solve the problem that static RAM read data operational stability is low, in addition, this static RAM structure is simple, area is less, be convenient to Integrated manufacture.
Alternatively, each storage unit 501 in above-mentioned N number of storage unit comprises: the first memory node 5013 and the second memory node 5014.
First memory node 5013, for storing the level state with the level state homophase of each storage unit 501 above-mentioned.
Second memory node 5014, for storing the level state anti-phase with the level state of each storage unit 501 above-mentioned; Wherein, each in above-mentioned N number of transistor seconds 502 is connected between the first memory node 5013 in corresponding storage unit 501 and the grid of the first transistor 10 by source electrode and drain electrode.
As can be seen from Figure 5, transistor seconds 502 is connected to the second memory node 5014 by drain electrode and realizes the connection with storage unit.Storage unit 501 stores the level state identical with this storage unit 501 by the first memory node 5013, second memory node 5014 is for storing the level state anti-phase with this storage unit 501, such as, when the level state that storage unit 501 stores is " 1 ", the level state that then the first memory node 5013 stores is " 1 ", and the level state that the second memory node 5014 stores is " 0 ".
Preferably, conveniently realize the first memory node 5013 of storage unit 501 and the level state of the second memory node 5014 is level state contrary each other, each storage unit 501 in above-mentioned N number of storage unit comprises: the first phase inverter 5011 and the second phase inverter 5012.
First phase inverter 5011, is connected between the first memory node 5013 and the second memory node 5014.
Second phase inverter 5012, is oppositely connected between the first memory node 5013 and the second memory node 5014 relative to the first phase inverter 5011.
The second end that the first end of the first phase inverter 5011 is connected to the first memory node 5013, first phase inverter 5011 is connected to the second memory node 5014.And the second end that the first end of the second phase inverter 5012 is connected to the second memory node 5014, the second phase inverter 5012 is connected to the first memory node 5013, realizes the first phase inverter 5011 and be connected with the second the anti-phase of phase inverter 5012.Phase inverter is used for anti-phase for the level state of input, and such as, level state " 1 " obtains level state " 0 " via phase inverter.Two contrary level states can be obtained easily by phase inverter, realize the anti-phase of the level state of the first memory node 5013 and the second memory node 5014.
The concrete structure of the memory module in Fig. 5 as shown in Figure 6, as shown in Figure 6, this memory module comprises storage unit 501, preferably, in order to reduce the power consumption of static RAM, each storage unit 501 in above-mentioned N number of storage unit comprises: the first PMOS transistor PU-1, the first nmos pass transistor PD-1, the second PMOS transistor PU-2 and the second nmos pass transistor PD-2.
First PMOS transistor PU-1, is connected between power vd D and the first memory node Q by source electrode and drain electrode, and the grid of the first PMOS transistor PU-1 is connected to the second memory node QN.
First nmos pass transistor PD-1, be connected between the first memory node Q and ground VSS by source electrode and drain electrode, the grid of the first nmos pass transistor PD-1 is connected to described second memory node QN.
Second PMOS transistor PU-2, is connected between power vd D and described second memory node QN by source electrode and drain electrode, and the grid of described second PMOS transistor PU-2 is connected to described first memory node Q;
Second nmos pass transistor PD-2, be connected between described second memory node QN and ground VSS by source electrode and drain electrode, the grid of described second nmos pass transistor PD-2 is connected to described first memory node Q.
As shown in Figure 6, storage unit 501 comprises: the first PMOS transistor PU-1, the first nmos pass transistor PD-1, the second PMOS transistor PU-2, the second nmos pass transistor PD-2, power vd D and ground VSS.Wherein, the grid of the first PMOS transistor PU-1 and the first nmos pass transistor PD-1 is connected to the second memory node QN jointly, the drain electrode of the first PMOS transistor PU-1 is connected to power vd D, the source electrode of the first PMOS transistor PU-1 is connected to the first memory node Q, the drain electrode of the first nmos pass transistor PD-1 is connected to the first memory node Q, and the source electrode of the first nmos pass transistor PD-1 is connected to ground VSS.Same, the grid of the second PMOS transistor PU-2 and the second nmos pass transistor PD-2 is connected to the first memory node Q, the drain electrode of the second PMOS transistor PU-2 is connected to power vd D, the source electrode of the second PMOS transistor PU-2 and the drain electrode of the second nmos pass transistor PD-2 are connected to the second memory node QN, and the source electrode of the second nmos pass transistor PD-2 is connected to ground VSS.
Be interconnected to constitute a CMOS phase inverter by the first PMOS transistor PU-1, the first nmos pass transistor PD-1, power vd D and ground VSS, make the anti-phase level state obtaining the second memory node QN of the level state of the first memory node Q.Same, the second PMOS transistor PU-2, the second nmos pass transistor PD-2, power vd D and ground VSS are interconnected and also form a CMOS phase inverter, make the anti-phase level state obtaining the first memory node Q of the level state of the second memory node QN.CMOS phase inverter quiescent dissipation is low, and antijamming capability is strong, and storage unit adopts CMOS phase inverter can reduce power consumption and the antijamming capability of whole static RAM.
Preferably, in order to improve the efficiency of data writing operation in static RAM further, this static RAM also comprises: the 3rd bit line 509, N number of 5th transistor and, the 4th bit line 510 and N number of 3rd wordline.
N number of 5th transistor, with N number of storage unit one_to_one corresponding, each in described N number of 5th transistor is connected between corresponding storage unit and the 3rd bit line 509 by source electrode and drain electrode;
N number of 6th transistor, with N number of storage unit one_to_one corresponding, each in N number of 6th transistor is connected between corresponding storage unit and the 4th bit line 510 by source electrode and drain electrode;
N number of 3rd wordline, with N number of 5th transistor and N number of 6th transistor one_to_one corresponding, each in N number of 3rd wordline is connected to the 5th corresponding transistor and the grid of the 6th transistor, for controlling the storage unit write level state reading level state from the storage unit of correspondence and/or control to correspondence.
As shown in Figure 5, the grid of the 5th transistor 505 is connected to the drain electrode that the 3rd wordline the 511, five transistor 505 is connected to the 3rd bit line the 509, five transistor 505 by source electrode and is connected to the first memory node 5013.3rd wordline 511 writes data for controlling to storage unit 501.When the 3rd wordline 511 is high level, the 5th transistor 505 conducting, becomes a transmission path, now can write level state by the 3rd bit line 509 in storage unit 501.As a write port, in static RAM, write data by this write port by increase the 5th transistor 505 and the 3rd bit line 509 in above-mentioned static RAM, reach the efficiency improving and write data in static RAM.
The grid of the 5th transistor 505 is connected to the 3rd wordline the 511, five transistor 505 is connected to storage unit 501 the first memory node 5013 by the drain electrode that source electrode is connected to the 3rd bit line the 509, five transistor 505.The grid of the 6th transistor 506 is also connected to the 3rd wordline the 511, six transistor 506 is connected to storage unit 501 the second end by the drain electrode that source electrode is connected to the 4th bit line the 510, six transistor 506.The conducting that 3rd wordline 511 controls the 5th transistor 505 and the 6th transistor 506 simultaneously and cut-off control data that whether reading cells 501 stores or write data to storage unit 501.In the data read operation process of storer, such as, " 1 " that stores in reading cells 501, the level of the first end of storage unit 501 is " 0 ", the level of the second end of storage unit 501 is " 1 ", first charging is carried out to the 3rd bit line 509 and the 4th bit line 510 and reach " 1, 3rd wordline 511 is high level, 5th transistor 505 and the conducting simultaneously of the 6th transistor 506, at this moment in the 5th transistor 505 and the 6th transistor 506, electric current is had to flow through, now the level of the 3rd bit line 509 is dragged down, 3rd bit line 509 and the 4th bit line 510 produce pressure reduction, when voltage difference reach predetermined value then sense amplifier (not shown) open, amplify voltage difference, realize the reading of data.Obtain in process writing data in storer, the Data import that will write is on the 3rd bit line 509 and the 4th bit line 510, such as to write data " 1 " in storage unit 501, the 3rd bit line 509 is then made to load data " 0 ", 4th bit line 510 loads data " 1 ", when the 3rd wordline 511 is high level, 5th transistor 505 and the conducting simultaneously of the 6th transistor 506, " 0 " that now the 3rd bit line 509 loads transfers to the first end of storage unit 501, the data " 1 " that second bit line 307 loads transfer to the second end of storage unit 501, realize writing data to storage unit 501.
3rd wordline 511 controls the 5th transistor 505 and the 6th transistor 506, realize reading level state and/or the storage unit write level state to correspondence from storage unit, the basis of above-mentioned static RAM adds the 5th transistor 505, the 6th transistor 506, the 3rd bit line 509 and the 4th bit line 510 as a memory read/write port, realize sense data or write data in static RAM from static RAM, improve the read/write speed of static RAM.
Alternatively, this static RAM also comprises: processor, connect the first bit line 20 and N number of first wordline, for exporting control signal to arbitrary first wordline in N number of first wordline 5, and the level state of the storage unit corresponding with arbitrary first wordline is read from the first bit line 20, control signal is for controlling the conducting between the source electrode of transistor seconds corresponding to arbitrary first wordline and drain electrode.
Preferably, the first transistor 10 and transistor seconds 502 are NMOS.
The power consumption of CMOS transistor lower than the power consumption of TTL transistor, and has stronger anti-interference.CMOS transistor comprises nmos pass transistor and PMOS transistor, wherein, nmos pass transistor conducting needs the voltage difference making grid and source electrode to be greater than certain value ability conducting, be applicable to the situation of source ground, and PMOS transistor conducting needs the voltage difference making grid and source electrode to be less than certain value ability conducting, be applicable to source electrode and connect power supply.In addition, nmos pass transistor conducting resistance is less than the conducting resistance of PMOS transistor, thus the conduction loss of nmos pass transistor is accordingly lower than the conduction loss of PMOS transistor, therefore adopts nmos pass transistor can reduce the loss of static RAM.
This application provides a kind of preferred embodiment to make an explanation to the application further, but it should be noted that the preferred embodiment is just in order to better describe the application, does not form and limits improperly the application.
As can be seen from the above description, the application achieves following technique effect:
1) by the grid of the first transistor to be connected to the source electrode of transistor seconds via internal wiring ILB, the voltage of the second memory node of storage unit can be kept when making to read data from static RAM to remain unchanged, by the grid of third transistor to be connected to the source electrode of the 4th transistor via internal wiring ILA, the voltage of the first memory node of storage unit can be kept when making to read data from static RAM to remain unchanged, improve the stability reading data from static RAM, solve and read the low problem of data stability from static RAM.And this static RAM number of transistors is less, area is less, is convenient to Integrated manufacture.
2) this static RAM can perform 2 ports read data and 1 port write data simultaneously, or performs 3 ports read data simultaneously, and the read data efficiency of this static RAM is greatly improved.
3) transistor of this static RAM adopts MOS transistor composition, and power consumption is lower, reduces the power consumption of static RAM.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the application.
Claims (7)
1. a static RAM, is characterized in that, comprising:
First bit line;
The first transistor, is connected between described first bit line and power supply or ground by source electrode and drain electrode;
N number of storage unit, each in described N number of storage unit is for memory level state, and described level state comprises high level and low level, and N is more than or equal to 1;
N number of transistor seconds, with described N number of storage unit one_to_one corresponding, each in described N number of transistor seconds is connected between corresponding storage unit and the grid of described the first transistor by source electrode and drain electrode;
N number of first wordline, with described N number of transistor seconds one_to_one corresponding, each in described N number of first wordline is connected to the grid of corresponding transistor seconds, reads level state for controlling from the storage unit of correspondence;
Second bit line;
Third transistor, is connected between described second bit line and power supply or ground by source electrode and drain electrode;
N number of 4th transistor, with described N number of storage unit one_to_one corresponding, wherein, each in described N number of 4th transistor is connected between corresponding storage unit and the grid of described third transistor by source electrode and drain electrode; And
N number of second wordline, with described N number of 4th transistor one_to_one corresponding, each in described N number of second wordline is connected to the grid of the 4th corresponding transistor, reads level state for controlling from the storage unit of correspondence.
2. static RAM according to claim 1, is characterized in that, each storage unit in described N number of storage unit comprises:
First memory node, for storing the level state with the level state homophase of each storage unit described;
Second memory node, for storing the level state anti-phase with the level state of each storage unit described; Wherein,
Each in described N number of transistor seconds is connected between the first memory node in corresponding storage unit and the grid of described the first transistor by source electrode and drain electrode, or each in described N number of transistor seconds is connected between the second memory node in corresponding storage unit and the grid of described the first transistor by source electrode and drain electrode.
3. static RAM according to claim 2, is characterized in that, each storage unit in described N number of storage unit comprises:
First phase inverter, is connected between described first memory node and described second memory node;
Second phase inverter, is oppositely connected between described first memory node and described second memory node relative to described first phase inverter.
4. static RAM according to claim 2, is characterized in that, each storage unit in described N number of storage unit comprises:
One PMOS, is connected between power supply and described first memory node by source electrode and drain electrode, and the grid of a described PMOS is connected to described second memory node;
One NMOS, is connected between described first memory node and ground by source electrode and drain electrode, and the grid of a described NMOS is connected to described second memory node;
2nd PMOS, is connected between power supply and described second memory node by source electrode and drain electrode, and the grid of described 2nd PMOS is connected to described first memory node;
2nd NMOS, is connected between described second memory node and ground by source electrode and drain electrode, and the grid of described 2nd NMOS is connected to described first memory node.
5. static RAM according to claim 1, is characterized in that, also comprises:
3rd bit line;
N number of 5th transistor, with described N number of storage unit one_to_one corresponding, each in described N number of 4th transistor is connected between corresponding storage unit and described 3rd bit line by source electrode and drain electrode;
4th bit line;
N number of 6th transistor, with described N number of storage unit one_to_one corresponding, each in described N number of 6th transistor is connected between corresponding storage unit and described 4th bit line by source electrode and drain electrode;
N number of 3rd wordline, with described N number of 5th transistor and N number of 6th transistor one_to_one corresponding, each in described N number of 3rd wordline is connected to the 5th corresponding transistor and the grid of the 6th transistor, for controlling the storage unit write level state reading level state from the storage unit of correspondence and/or control to correspondence.
6. static RAM according to any one of claim 1 to 5, is characterized in that, also comprises:
Processor, connect described first bit line and described N number of first wordline, for exporting control signal to arbitrary first wordline in described N number of first wordline, and the level state of the storage unit corresponding with described arbitrary first wordline is read from described first bit line, described control signal is for controlling the conducting between the source electrode of transistor seconds corresponding to described arbitrary first wordline and drain electrode.
7. static RAM according to any one of claim 1 to 5, is characterized in that, described the first transistor and described transistor seconds are NMOS.
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| CN109196587A (en) * | 2016-05-16 | 2019-01-11 | 索尼公司 | Semiconductor circuit, driving method and electronic equipment |
| CN113096702A (en) * | 2020-01-09 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Memory circuit and reading method and recovery method thereof |
| CN116230053A (en) * | 2023-03-01 | 2023-06-06 | 芯立嘉集成电路(杭州)有限公司 | Four-transistor static random access memory and access method |
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| CN105489241B (en) | 2018-07-03 |
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