CN108414988A - A kind of digital delay method and device based on FPGA - Google Patents
A kind of digital delay method and device based on FPGA Download PDFInfo
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- CN108414988A CN108414988A CN201810193493.3A CN201810193493A CN108414988A CN 108414988 A CN108414988 A CN 108414988A CN 201810193493 A CN201810193493 A CN 201810193493A CN 108414988 A CN108414988 A CN 108414988A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/2806—Employing storage or delay devices which preserve the pulse form of the echo signal, e.g. for comparing and combining echoes received during different periods
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Abstract
The present invention discloses a kind of digital delay method and device based on FPGA, and method includes storing the valid data of each pulse in phased-array radar intermediate-freuqncy signal；And it is directed to each pulse, when the reception duration of pulse reaches the corresponding maximum delay value of the pulse, export the valid data of the pulse.Due to only storing the valid data in radar intermediate frequency signal, to reduce memory space, and it can be directed to the flexible configuration that maximum delay value is realized in each pulse, adapt to the delay variation of each pulse.
Description
Technical field
The present invention relates to delay line technique fields, and FPGA (Field- are based on more specifically to one kind
Programmable Gate Array, i.e. field programmable gate array) digital delay method and device.
Background technology
Phased-array radar (PAR, Phased Array Radar) i.e. phase controlling Electronically Scanned Array radar, using a large amount of
The small size antenna unit of unit control is arranged in antenna array, and each antenna element is controlled by independent switch.
In order to improve the anti-interference ability and resolution ratio of phased-array radar, recognition capability and solution multi-target imaging are asked
Topic, it is desirable that phased-array radar must have instant bandwidth as big as possible.And in order to solve because of caused by aperture effect to letter
The restricted problem of number instant bandwidth usually uses delay line to carry out compensation of delay.Traditional optical time delay technology is realizing big
The problems such as weight of fibre delay line is heavy, volume is big, precision is low, loss is big can be caused when range delay, have been unable to meet radar
The requirement of system.In recent years, with the development of digital technology, digital delay line obtains increasingly wider in fields such as radar, communications
General application solves the problems of optical time delay technology, but traditional digital delay techniques will realize super large distance
It is too big that delay occupies digital storage space.
Invention content
In view of this, the present invention proposes a kind of digital delay method and device based on FPGA, it is intended to realize that reduction storage is empty
Between purpose.
To achieve the goals above, it is proposed that scheme it is as follows：
A kind of digital delay method based on FPGA, including：
Receive the phased-array radar intermediate-freuqncy signal of down coversion output；
Store the valid data of each pulse in the phased-array radar intermediate-freuqncy signal successively according to receiving time sequence；
Obtain the corresponding maximum delay value of each pulse；
Calculate the reception duration of each pulse, when reception of the pulse is a length of to initially receive having for the pulse
Data are imitated to the time so far；
For each pulse, judge whether the reception duration of the pulse reaches the corresponding maximum delay of the pulse
Value, if so, exporting the valid data of the pulse, the reception duration of each pulse reaches the corresponding maximum of the pulse
The receiving time sequence consensus of the sequence of delay value and each pulse.
Preferably, the reception duration for calculating each pulse, specifically includes：
After reset, opens counter and count；
In the reception start time of the valid data of each pulse, obtains the count value of the counter and be stored in
In first RAM；
For each pulse, connecing for the valid data of the pulse is subtracted using the current count value of the counter
The count value for receiving counter described in start time, obtains the reception duration of the pulse.
Preferably, for each pulse, it is corresponding to judge whether the reception duration of the pulse reaches the pulse
Maximum delay value specifically includes if so, exporting the valid data of the pulse：
For each pulse writing for the pulse is obtained in the reception start time of the valid data of the pulse
Initial address is simultaneously stored in the 2nd RAM, the reading initial address as the pulse；
The moment is finished receiving in the valid data of each pulse, obtains the count value of the counter；
For each pulse, the counting for finishing receiving counter described in the moment of the valid data of the pulse is utilized
Value subtracts the count value for receiving counter described in start time of the valid data of the pulse, obtains the pwm value of the pulse
And it is stored in the 3rd RAM；
It is raw when the reception duration of the pulse reaches the corresponding maximum delay value of the pulse for each pulse
At the reading origin identification of the pulse；
The pulse is obtained out of described 2nd RAM according to the reading origin identification of the pulse for each pulse
Reading initial address, and obtain out of described 3rd RAM the pwm value of the pulse, according to the reading initial address of the pulse and
The pwm value of the pulse obtains the reading end address of the pulse, and data are read since the reading initial address of the pulse,
When reading the reading end address of the pulse, the reading end of identification of the pulse is generated, the significant figure of the pulse is terminated
According to reading.
Preferably, when reading the reading end address of the pulse, further include：
Generate the enable signal of the delay judgement of next pulse；
After obtaining the enable signal, the delay judgement of next pulse is opened, until having for each pulse
Until imitating data end of output.
Preferably, the valid data of each pulse are sequentially stored in QDRII+SRAM；
The QDRII+SRAM points are N number of partition holding, and the N is positive integer；
The valid data of each pulse are sequentially stored in each partition holding according to partition holding number, each
The partition holding stores the valid data of a pulse, and the corresponding maximum delay value of each pulse is no more than described
QDRII+SRAM stores the corresponding duration of valid data of N number of pulse.
A kind of digital delay device based on FPGA, including：
Data receipt unit, the phased-array radar intermediate-freuqncy signal for receiving down coversion output；
Valid data storage unit, for being stored successively in the phased-array radar intermediate-freuqncy signal according to receiving time sequence
The valid data of each pulse；
First acquisition unit, for obtaining the corresponding maximum delay value of each pulse；
Counting unit, the reception duration for calculating each pulse, when reception of the pulse is a length of to be started to receive
To the valid data of the pulse to the time so far；
Output unit, for for each pulse, judging whether the reception duration of the pulse reaches the pulse
Corresponding maximum delay value, if so, exporting the valid data of the pulse, the reception duration of each pulse reaches described
The receiving time sequence consensus of the sequence and each pulse of the corresponding maximum delay value of pulse.
Preferably, the counting unit, specifically includes：
It counts and opens subelement, after resetting, open counter and count；
It counts and obtains subelement, for the reception start time of the valid data in each pulse, obtain the meter
The count value of number device is simultaneously stored in the first RAM；
Duration calculation subelement is received, for for each pulse, the current count value using the counter to subtract
The count value for receiving counter described in start time for removing the valid data of the pulse, obtains the reception duration of the pulse.
Preferably, the output unit, specifically includes：
It reads address and obtains subelement, for for each pulse, starting in the reception of the valid data of the pulse
Moment obtains writing initial address and being stored in the 2nd RAM for the pulse, the reading initial address as the pulse；
It counts and obtains subelement, finish receiving the moment for the valid data in each pulse, obtain the meter
The count value of number device；
Pulsewidth computation subunit is finished receiving using the valid data of the pulse for for each pulse
The count value of counter described in moment subtracts the count value for receiving counter described in start time of the valid data of the pulse,
It obtains the pwm value of the pulse and is stored in the 3rd RAM；
It reads to enable subelement, for being directed to each pulse, when the reception duration of the pulse reaches the pulse pair
The maximum delay value answered generates the reading origin identification of the pulse；
Digital independent subelement, for for each pulse, according to the reading origin identification of the pulse, from described the
The reading initial address of the pulse is obtained in two RAM, and obtains the pwm value of the pulse out of described 3rd RAM, according to institute
The pwm value for stating the reading initial address and the pulse of pulse obtains the reading end address of the pulse, from the reading of the pulse
Initial address starts reading data and generates the reading end of identification of the pulse when reading the reading end address of the pulse,
Terminate the reading of the valid data of the pulse.
Preferably, described device further includes：
Delay judgement enable signal unit, it is next described for when reading the reading end address of the pulse, generating
The enable signal of the delay judgement of pulse；
Delay judgement opening unit, for after obtaining the enable signal, opening the delay judgement of next pulse,
Until the valid data end of output of each pulse.
Preferably, the valid data storage unit is QDRII+SRAM；
The QDRII+SRAM points are N number of partition holding, and the N is positive integer；
The valid data of each pulse are sequentially stored in each partition holding according to partition holding number, each
The partition holding stores the valid data of a pulse, and the corresponding maximum delay value of each pulse is no more than described
QDRII+SRAM stores the corresponding duration of valid data of N number of pulse.
Compared with prior art, technical scheme of the present invention has the following advantages：
A kind of digital delay method based on FPGA that above-mentioned technical proposal provides stores in phased-array radar intermediate-freuqncy signal
The valid data of each pulse；And it is directed to each pulse, reach the corresponding maximum delay value of the pulse in the reception duration of pulse
When, export the valid data of the pulse.It is empty to reduce storage due to only storing the valid data in radar intermediate frequency signal
Between, and it can be directed to the flexible configuration that maximum delay value is realized in each pulse, adapt to the delay variation of each pulse.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of flow chart of the digital delay method based on FPGA provided in an embodiment of the present invention；
Fig. 2 is the pulse schematic diagram of phased-array radar intermediate-freuqncy signal；
Fig. 3 is the detail flowchart of digital delay method；
Fig. 4 is that QDRII+SRAM reads interface sequence figure；
Fig. 5 is a kind of structural schematic diagram of QDRII+SRAM modules provided in an embodiment of the present invention；
Fig. 6 is the specific implementation logical construction schematic diagram of digital delay provided in an embodiment of the present invention；
Fig. 7 is the sequential relationship schematic diagram of digital delay provided in an embodiment of the present invention；
Fig. 8 is the schematic diagram of data valid signal；
Fig. 9 is the schematic diagram of data writing process；
Figure 10 is a kind of logical construction schematic diagram of the digital delay device based on FPGA provided in an embodiment of the present invention.
Specific implementation mode
Core of the invention thought is can to reduce pulse memory space by valid data in only storage pulse
To realize the delay of bigger, and then big instant bandwidth is realized, improves radar system anti-interference ability, resolution ratio, identification
Ability and multi-target imaging ability, it is small, light-weight, anti-electromagnetic interference capability is strong and integrated level is high.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The digital delay method based on FPGA that the present embodiment provides a kind of, referring to Fig. 1, including step：
S11：Receive the phased-array radar intermediate-freuqncy signal of down coversion output；
Digital delay method shown in Fig. 1 can be based on DRFM (Digital Radio-Frequency Memory, digital RF
Memory) technology realization.DRFM is a kind of radiofrequency signal storage system, for realizing radiofrequency signal storage and forwarding capability.It should
In step S11, the phased-array radar intermediate-freuqncy signal of down coversion output is received by the data receipt unit of DRFM.
S12：Store the valid data of each pulse in phased-array radar intermediate-freuqncy signal successively according to receiving time sequence；
Shown in Figure 2, the corresponding high level region of pulse is the significant figure of pulse in phased-array radar intermediate-freuqncy signal
According to.It will be in the valid data storage to the memory outside FPGA in phased-array radar intermediate-freuqncy signal.FPGA is in the present embodiment
FPGA inside DRFM, memory are the memory inside DRFM.
S13：Obtain the corresponding maximum delay value of each pulse；
In order to adapt to the delay variation of each pulse, each pulse can be directed to, corresponding maximum delay value is set, realized
The flexible configuration of each pulse delay.After the valid data for receiving phased-array radar intermediate-freuqncy signal, each pulse pair is obtained
The maximum delay value answered.
S14：Calculate the reception duration of each pulse；
One pulse corresponds to a reception duration.A length of valid data for initially receiving the pulse arrive when the reception of pulse
Time so far；
S15：For each pulse, judge whether the reception duration of pulse reaches the corresponding maximum delay value of the pulse, if
It is then to export the valid data of the pulse.
When the reception duration of each pulse reaches sequence and the reception of each pulse of the corresponding maximum delay value of the pulse
Between sequence consensus.The reception duration of some pulse reaches the corresponding maximum delay value of the pulse, then exports the significant figure of the pulse
According to conversely, then calculating the reception duration of the pulse again and judging again.The valid data for exporting pulse are exactly having pulse
Effect data are read out from the memory outside FPGA, that is, realize the big delay of each pulse.In practical applications, it can read
The valid data of pulse are imported into FPGA internal RAMs after pulse valid data, realize relative delay；Then again significant figure
It is read according to from RAM, delay fine tuning is carried out by shift register after 4 times of interpolation filterings of progress, finally 4 times of extractions again, carry out
After the modulation of width phase information, exported afterwards through DUC (Digital Up Conversion, Digital Up Convert), shown in Fig. 3.
Digital delay method provided in this embodiment based on FPGA stores each pulse of phased-array radar intermediate-freuqncy signal
Valid data；And it is directed to each pulse, when the reception duration of pulse reaches the corresponding maximum delay value of the pulse, output should
The valid data of pulse.Due to only storing the valid data in radar intermediate frequency signal, to reduce memory space, and can
To realize the flexible configuration of maximum delay value for each pulse, the delay variation of each pulse has been adapted to.
In a kind of specific implementation mode of the embodiment of the present invention, by each of phased-array radar intermediate-freuqncy signal received
The valid data of pulse are stored to QDRII+SRAM successively according to receiving time sequence.QDRII+SRAM points are N number of storage point
Area, N are positive integer；The valid data of each pulse are sequentially stored in each partition holding, Mei Gecun according to partition holding number
The valid data of one pulse of partitioned storage are stored up, the corresponding maximum delay value of each pulse stores N number of no more than QDRII+SRAM
The corresponding duration of valid data of pulse.
Fig. 4 discloses QDRII+SRAM and reads interface sequence figure, and use_clk indicates user clock.It is shown in Figure 4,
The reading delay of QDRII+SRAM outside FPGA is larger, compares FPGA internal RAMs, has more the delay of 72 clock cycle, Ke Yishi
Existing larger delay.
The QDRII+SRAM modules that the present embodiment uses, can specifically include：The concatenated QDRII+SRAM of multi-disc.Using more
The mode of piece QDRII+SRAM serial accesses is to improve access depth.Two panels QDRII+SRAM as shown in Figure 5 is used in series, every
Size is 36MB, two panels 72MB, and 40000km delays may be implemented, and super large delay is realized by the above method.Pass through 4 times later
Interpolation filtering is finely tuned using delay, and then the process of 4 times of extractions realizes that 4 times of delay precisions improve again.Every QDRII+SRAM
A corresponding maximum delay value, shown in Figure 5, two panels QDRII+SRAM corresponds to maximum delay value D1, D2 respectively.QDR-COM-
WRD is the integration module for writing control module QDR_CTRL_WR and time delay module QDR_CTRL_RD.
The step of calculating the reception duration of each pulse, can specifically include step：
S21：After reset, opens counter and count；
S22：In the reception start time of the valid data of each pulse, obtains the count value of counter and be stored in first
In RAM；
S23：For each pulse, when subtracting the receptions of the valid data of pulse using the current count value of counter and starting
The count value for carving counter, obtains the reception duration of pulse.
For each pulse, judge whether the reception duration of pulse reaches the corresponding maximum delay value of the pulse, if so,
The step of exporting the valid data of the pulse, can specifically include：
S31：For each pulse, in the reception start time of the valid data of pulse, obtain the pulse writes starting point
Location is simultaneously stored in the 2nd RAM, the reading initial address as the pulse；
S32：The moment is finished receiving in the valid data of each pulse, obtains the count value of counter；
S33：For each pulse, this is subtracted using the count value for finishing receiving moment counter of the valid data of pulse
The count value of the reception start time counter of the valid data of pulse, obtains the pwm value of the pulse and is stored in the 3rd RAM
It is interior；
S34：For each pulse, when the reception duration of pulse reaches the corresponding maximum delay value of the pulse, the arteries and veins is generated
The reading origin identification of punching；
S35：The reading starting point of the pulse is obtained out of the 2nd RAM according to the reading origin identification of pulse for each pulse
Location, and the pwm value for obtaining out of the 3rd RAM the pulse obtains the pulse according to the reading initial address and pwm value of the pulse
Reading end address, data are read since the reading initial address of the pulse, it is raw when reading the reading end address of the pulse
At the reading end of identification of the pulse, terminate the reading of the valid data of the pulse.
Consider pulse data export in sequence, can after the valid data end of output of current PRF, then into
The delay judgement of the valid data of the next pulse of row, and then vast resources caused by avoiding the calculating of a large amount of delay judgements occupies,
Concrete implementation method can be：
During reading the valid data of current PRF, when reading end address, not only generates and read to terminate
Mark, to terminate the reading of the valid data of current PRF, also generates the enable signal of the delay judgement of next pulse, when obtaining
After the enable signal of the delay judgement of next pulse, the delay judgement of next pulse is opened, until the phased-array radar received
Until the valid data end of output of all pulses in intermediate-freuqncy signal.
The delay judgement process of next pulse includes step：
S41：The count value of the reception start time counter of the valid data of the pulse is obtained out of the first RAM；
S42：It is subtracted from the reception of the valid data of the first RAM pulses obtained and is opened using the current count value of counter
The count value of beginning moment counter, obtains the reception duration of the pulse；
S43：Judge whether the reception duration of the pulse reaches the corresponding maximum delay value of the pulse, if so, executing step
Rapid S44, if it is not, thening follow the steps S42；
S44：Generate the reading origin identification of the pulse.
Fig. 6 is a kind of specific implementation mode of the present invention, and sequential relationship is as shown in Figure 7.Shown in Fig. 6 and Fig. 7, realize
The process postponed greatly includes the following steps：
A11：Data are written；
QDRII+SRAM's writes control module QDR_CTRL_WR under data valid signal vin effects, and generation is write enabled
Wr_en, write address wr_addr, write data wr_dat, and control QDRII+SRAM carries out write operation.Write address wr_addr, that is, phased
The valid data of the pulse of battle array radar intermediate frequency signal are stored in the address in QDRII+SRAM；Write data wr_dat i.e. phased array thunder
Up to the valid data of the pulse of intermediate-freuqncy signal.It refers to that will write data wr_dat according to writing ground that control QDRII+SRAM, which carries out write operation,
Location wr_addr is deposited into QDRII+SRAM.Din indicates phased-array radar intermediate-freuqncy signal.
Referring to Fig. 8, data valid signal vin includes rising edge vin_pos, keeps stage vin_con and failing edge vin_
Neg three phases.
A12：Data export；
Time delay module QDR_CTRL_RD mainly utilizes 3 dual port RAMs, i.e. RAM1, RAM2 and RAM3, realizes delay work(
Energy.RAM1, that is, above-mentioned first RAM, RAM2, that is, above-mentioned 2nd RAM, RAM3, that is, above-mentioned 3rd RAM.
The current meter of counter is written under the rising edge vin_pos drivings of the data valid signal of current PRF in RAM1
Numerical value, i.e. the count value pw_start_time of the reception start time counter of the valid data of current PRF.Real-time judge meter
The count value time_cnt of number device subtracts the count value pw_ of the reception start time counter of the valid data of current PRF
Whether start_time is equal to the maximum delay value D of current PRF.If the count value time_cnt of counter subtracts current PRF
Valid data reception start time counter count value pw_start_time be equal to current PRF maximum delay value D,
Then generate and export the reading origin identification rd_rdy for the valid data for starting to read the current PRF in QDRII+SRAM.
Having write for current PRF is written under the rising edge vin_pos drivings of the data valid signal of current PRF in RAM2
Beginning address start_address, initial address when read operation as current PRF, i.e., read the arteries and veins from QDRII+SRAM
The reading initial address of the valid data of punching.
The pulsewidth of current PRF is written under the failing edge vin_neg drivings of the data valid signal of current PRF in RAM3
Value pw_end_cnt.The count value of counter is obtained under the failing edge vin_neg drivings of the data valid signal of current PRF,
The counting value added of counter this period between the rising edge vin_pos and failing edge vin_neg of current PRF is to work as
The pwm value pw_end_cnt of prepulse.Data are read since the reading initial address start_address of current PRF, work as reading
To current PRF pwm value pw_end_cnt at the end of, obtain read end address.Wherein, the meaning of pw_cnt is in Fig. 7
Pwm value.
After the valid data delay output of previous pulse, the enable signal ram_rd_ of the delay judgement of next pulse is obtained
The reading address ram_rd_addr of en, 3 RAM of control obtain current PRF by the above processing of RAM1, RAM2 and RAM3
Read origin identification rd_rdy, the reading initial address start_address of current PRF and the pwm value pw_end_ of current PRF
Cnt, and then export to obtain the reading origin identification rd_en of QDRII+SRAM by block of state Status and read address rd_addr,
To realize the delay operation to data, data valid signal rd_dat_v and data rd_dat is exported after being postponed.
Step A11 carries out the process of data write-in, is equivalent to QDRII+SRAM subregions, each pulse is one group, every group
Amount of storage is determined by pulsewidth, stores the valid data of N number of pulse, after the rising edge for receiving a pulse, by having for the pulse
Corresponding region in data write-in QDRII+SRAM is imitated, until the failing edge of pulse.As shown in figure 9, QDRII+SRAM points are N number of
Partition holding, N are positive integer.The valid data of each pulse are sequentially written in corresponding partition holding according to partition holding number,
Each partition holding stores the valid data of a pulse, and the valid data of the N+1 pulse are written first in QDRII+SRAM
Group subregion, recycles, in cycles successively.
Step A12 carries out the process of data output.The reading starting of current PRF is obtained by RAM1, RAM2 and RAM3 processing
Rd_rdy is identified, the reading initial address start_address of current PRF reads the pwm value pw_end_cnt of current PRF, reads
End of identification rd_end.It is, when module enable signal triggers, to wait starting of continuing that QDRII+SRAM, which reads state of a control transfer process,
Rd_rdy is identified, when triggering, starts to read data from QDRII+SRAM, until reading end of identification rd_end triggerings, current PRF
The delay operation of valid data is completed, this process is then recycled.
For each method embodiment above-mentioned, for simple description, therefore it is all expressed as a series of combination of actions, but
Be those skilled in the art should understand that, the present invention is not limited by the described action sequence because according to the present invention, certain
A little steps can be performed in other orders or simultaneously.
Following is apparatus of the present invention embodiment, can be used for executing the method for the present invention embodiment.For apparatus of the present invention reality
Undisclosed details in example is applied, the method for the present invention embodiment is please referred to.
A kind of digital delay side's device based on FPGA is present embodiments provided, referring to Figure 10, which includes：Data connect
Receive unit 11, valid data storage unit 12, first acquisition unit 13, counting unit 14 and output unit 15.
Data receipt unit 11, the phased-array radar intermediate-freuqncy signal for receiving down coversion output；
Valid data storage unit 12, it is every in phased-array radar intermediate-freuqncy signal for being stored successively according to receiving time sequence
The valid data of a pulse；
First acquisition unit 13, for obtaining the corresponding maximum delay value of each pulse；
Counting unit 14, the reception duration for calculating each pulse, when reception of pulse is a length of initially receive it is described
The valid data of pulse are to the time so far；
It is corresponding most to judge whether the reception duration of pulse reaches the pulse for being directed to each pulse for output unit 15
Big delay value, if so, exporting the valid data of the pulse, the reception duration of each pulse reaches the corresponding maximum delay of pulse
The receiving time sequence consensus of the sequence of value and each pulse.
Digital delay device provided in this embodiment based on FPGA, valid data storage unit 12 are suitable according to receiving time
Sequence stores the valid data of each pulse in phased-array radar intermediate-freuqncy signal successively；Output unit 14 is directed to each pulse, judges
Whether the reception duration of pulse reaches the corresponding maximum delay value of the pulse, if so, exporting the valid data of the pulse.Due to
The valid data in radar intermediate frequency signal are only stored, to reduce memory space, and each pulse can be directed to and realized
The flexible configuration of maximum delay value has adapted to the delay variation of each pulse.
Counting unit 14, specifically includes：It counts and opens subelement, counting obtains subelement and it is single to receive duration calculation
Member.
It counts and opens subelement, after resetting, open counter and count；
It counts and obtains subelement, for the reception start time of the valid data in each pulse, obtain the meter of counter
Numerical value is simultaneously stored in the first RAM；
Duration calculation subelement is received, for being directed to each pulse, pulse is subtracted using the current count value of counter
The count value of the reception start time counter of valid data, obtains the reception duration of the pulse.
Output unit 15, specifically includes：Address is read to obtain subelement, count acquisition subelement, pulsewidth computation subunit, read
Enabled subelement and data reading subunit.
It reads address and obtains subelement, for being directed to each pulse, in the reception start time of the valid data of pulse, obtain
The pulse is write initial address and is stored in the 2nd RAM, the reading initial address as the pulse；
It counts and obtains subelement, finish receiving the moment for the valid data in each pulse, obtain the meter of counter
Numerical value；
Pulsewidth computation subunit is counted for being directed to each pulse using the finishing receiving for valid data of pulse constantly
The count value of device subtracts the count value of the reception start time counter of the valid data of the pulse, obtains the pwm value of the pulse
And it is stored in the 3rd RAM；
It reads to enable subelement, for being directed to each pulse, prolong when the reception duration of pulse reaches the corresponding maximum of the pulse
Duration generates the reading origin identification of the pulse；
Digital independent subelement, for being obtained out of the 2nd RAM according to the reading origin identification of pulse for each pulse
The reading initial address of the pulse, and the pwm value of the pulse is obtained out of the 3rd RAM, according to the reading initial address and arteries and veins of the pulse
Width values obtain the reading end address of the pulse, data are read since the reading initial address of the pulse, when reading the pulse
When reading end address, the reading end of identification of the pulse is generated, the reading of the valid data of the pulse is terminated.
Preferably, the digital delay device based on FPGA further includes：Delay judgement enable signal unit and delay judgement are opened
Open unit.
Delay judgement enable signal unit, for when reading end address, generating the delay of next pulse
The enable signal of judgement；
Delay judgement opening unit, the delay judgement for after obtaining enable signal, opening next pulse, until each
Until the valid data end of output of pulse.
Preferably, valid data storage unit 12 is specially QDRII+SRAM；
QDRII+SRAM points are N number of partition holding, and N is positive integer；
The valid data of each pulse are sequentially stored in each partition holding, each partition holding according to partition holding number
The valid data of a pulse are stored, the corresponding maximum delay value of each pulse stores N number of pulse no more than QDRII+SRAM
The corresponding duration of valid data.
The apparatus embodiments described above are merely exemplary, wherein the unit illustrated as separating component can
It is physically separated with being or may not be.Some or all of module therein can be selected according to the actual needs
It achieves the purpose of the solution of this embodiment.Those of ordinary skill in the art are without creative efforts, you can with reason
It solves and implements.
Herein, the terms "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, from
And make include a series of elements process, method, article or equipment not only including those elements, but also include not bright
The other element really listed, or further include for elements inherent to such a process, method, article, or device.Do not having
In the case of more limitations, the element that is limited by sentence "including a ...", it is not excluded that including the element process,
There is also other identical elements in method, article or equipment.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
To the above description of disclosed embodiment of this invention, so that professional and technical personnel in the field is realized or use this
Invention.Various modifications to these embodiments will be apparent to those skilled in the art, institute herein
The General Principle of definition can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore,
The present invention is not intended to be limited to the embodiments shown herein, and is to fit to special with principles disclosed herein and novelty
The consistent widest range of point.
Claims (10)
1. a kind of digital delay method based on FPGA, which is characterized in that including：
Receive the phased-array radar intermediate-freuqncy signal of down coversion output；
Store the valid data of each pulse in the phased-array radar intermediate-freuqncy signal successively according to receiving time sequence；
Obtain the corresponding maximum delay value of each pulse；
Calculate the reception duration of each pulse, when reception of the pulse a length of significant figure for initially receiving the pulse
According to the time so far；
For each pulse, judge whether the reception duration of the pulse reaches the corresponding maximum delay value of the pulse,
If so, exporting the valid data of the pulse, the reception duration of each pulse reaches the corresponding maximum of the pulse and prolongs
The receiving time sequence consensus of the sequence of duration and each pulse.
2. according to the method described in claim 1, it is characterized in that, the reception duration of each pulse of calculating, specifically includes：
After reset, opens counter and count；
In the reception start time of the valid data of each pulse, obtains the count value of the counter and be stored in first
In RAM；
For each pulse, the reception that the valid data of the pulse are subtracted using the current count value of the counter is opened
The count value of counter, obtains the reception duration of the pulse described in moment beginning.
3. according to the method described in claim 2, it is characterized in that, for each pulse, the reception of the pulse is judged
Whether duration reaches the corresponding maximum delay value of the pulse specifically includes if so, exporting the valid data of the pulse：
For each pulse, in the reception start time of the valid data of the pulse, obtain the pulse writes starting
Address is simultaneously stored in the 2nd RAM, the reading initial address as the pulse；
The moment is finished receiving in the valid data of each pulse, obtains the count value of the counter；
For each pulse, the count value for finishing receiving counter described in the moment using the valid data of the pulse subtracts
The count value for receiving counter described in start time for removing the valid data of the pulse, obtains the pwm value of the pulse and deposits
Storage is in the 3rd RAM；
For each pulse, when the reception duration of the pulse reaches the corresponding maximum delay value of the pulse, generation institute
State the reading origin identification of pulse；
The reading of the pulse is obtained out of described 2nd RAM according to the reading origin identification of the pulse for each pulse
Initial address, and obtain out of described 3rd RAM the pwm value of the pulse, according to the reading initial address of the pulse and described
The pwm value of pulse obtains the reading end address of the pulse, and data are read since the reading initial address of the pulse, work as reading
When getting the reading end address of the pulse, the reading end of identification of the pulse is generated, the valid data of the pulse are terminated
It reads.
4. according to the method described in claim 3, it is characterized in that, when reading the reading end address of the pulse, also wrap
It includes：
Generate the enable signal of the delay judgement of next pulse；
After obtaining the enable signal, the delay judgement of next pulse is opened, until the significant figure of each pulse
Until end of output.
5. according to the method described in Claims 1 to 4 any one, which is characterized in that the valid data of each pulse according to
It is secondary to be stored in QDRII+SRAM；
The QDRII+SRAM points are N number of partition holding, and the N is positive integer；
The valid data of each pulse are sequentially stored in each partition holding according to partition holding number, each described
Partition holding stores the valid data of a pulse, and the corresponding maximum delay value of each pulse is no more than described
QDRII+SRAM stores the corresponding duration of valid data of N number of pulse.
6. a kind of digital delay device based on FPGA, which is characterized in that including：
Data receipt unit, the phased-array radar intermediate-freuqncy signal for receiving down coversion output；
Valid data storage unit, it is each in the phased-array radar intermediate-freuqncy signal for being stored successively according to receiving time sequence
The valid data of pulse；
First acquisition unit, for obtaining the corresponding maximum delay value of each pulse；
Counting unit, the reception duration for calculating each pulse, when reception of the pulse is a length of to initially receive institute
The valid data of pulse are stated to the time so far；
Output unit, for for each pulse, judging whether the reception duration of the pulse reaches the pulse and correspond to
Maximum delay value, if so, export the valid data of the pulse, the reception duration of each pulse reaches the pulse
The receiving time sequence consensus of the sequence of corresponding maximum delay value and each pulse.
7. device according to claim 6, which is characterized in that the counting unit specifically includes：
It counts and opens subelement, after resetting, open counter and count；
It counts and obtains subelement, for the reception start time of the valid data in each pulse, obtain the counter
Count value and be stored in the first RAM；
Duration calculation subelement is received, for for each pulse, institute to be subtracted using the current count value of the counter
The count value for receiving counter described in start time for stating the valid data of pulse, obtains the reception duration of the pulse.
8. device according to claim 7, which is characterized in that the output unit specifically includes：
It reads address and obtains subelement, for for each pulse, in the reception start time of the valid data of the pulse,
Obtain writing initial address and being stored in the 2nd RAM for the pulse, the reading initial address as the pulse；
It counts and obtains subelement, finish receiving the moment for the valid data in each pulse, obtain the counter
Count value；
Pulsewidth computation subunit finishes receiving the moment for for each pulse using the valid data of the pulse
The count value of the counter subtracts the count value for receiving counter described in start time of the valid data of the pulse, obtains
The pwm value of the pulse is simultaneously stored in the 3rd RAM；
It reads to enable subelement, for for each pulse, when to reach the pulse corresponding for the reception duration of the pulse
Maximum delay value generates the reading origin identification of the pulse；
Digital independent subelement, for being directed to each pulse, according to the reading origin identification of the pulse, from described second
The reading initial address of the pulse is obtained in RAM, and obtains the pwm value of the pulse out of described 3rd RAM, according to described
The pwm value of the reading initial address and the pulse of pulse obtains the reading end address of the pulse, from the reading of the pulse
Beginning address starts reading data and generates the reading end of identification of the pulse when reading the reading end address of the pulse, ties
The reading of the valid data of Shu Suoshu pulses.
9. device according to claim 8, which is characterized in that described device further includes：
Delay judgement enable signal unit, for when reading the reading end address of the pulse, generating next pulse
Delay judgement enable signal；
Delay judgement opening unit, for after obtaining the enable signal, opening the delay judgement of next pulse, until
Until the valid data end of output of each pulse.
10. according to the device described in claim 6~9 any one, which is characterized in that the valid data storage unit is
QDRII+SRAM；
The QDRII+SRAM points are N number of partition holding, and the N is positive integer；
The valid data of each pulse are sequentially stored in each partition holding according to partition holding number, each described
Partition holding stores the valid data of a pulse, and the corresponding maximum delay value of each pulse is no more than described
QDRII+SRAM stores the corresponding duration of valid data of N number of pulse.
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| CN113204011A (en) * | 2021-03-29 | 2021-08-03 | 上海星秒光电科技有限公司 | Pulse time output method and device, signal processing equipment and storage medium |
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