CN102510273B - Finite impulse response (FIR) filter - Google Patents
Finite impulse response (FIR) filter Download PDFInfo
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Abstract
The invention discloses a finite impulse response (FIR) filter, which consists of a filtering coefficient buffer, a to-be-filtered data buffer, a multiplier, an accumulator, an accumulating register and a comparator, wherein the filtering coefficient buffer is used for buffering coefficients which are used in the filter; the to-be-filtered data buffer is used for buffering data to be filtered; the multiplier is used for computing a product of a single filter coefficient multiplied by BS data to be filtered; the accumulator is used for computing a sum of the output of the multiplier and the output of the accumulating register; the accumulating register is used for storing a result of the accumulator; and the output of the comparator is used for indicating whether the current output of the accumulator is filtering output. By adoption of the FIR filter, high efficiency of parallel computation can be realized.
Description
Technical field
The present invention relates to electron trade digital signal processing technique field, relate in particular to a kind of finite impulse response (FIR) (Finite Impulse Response is called for short FIR) filter based on multiply accumulating device.
Background technology
FIR filter extensive application in digital communication system, industry is also devoted to improve its filtering performance always.This filter can be used for carrying out multiple work, such as matched filtering, the isolation of noise, channel etc. are changed etc.
Generally, FIR algorithm filter can be expressed as:
Wherein, H vector is filter factor, and its number is K, and containing element is H (0)～H (K-1); X vector is data to be filtered, and its number is N
xindividual, comprise data element to be filtered and be: X (0)～X (N
x-1), the part that the X vector index using in algorithm is less than 0, all replaces with zero; Y-direction amount is filtering output, and its number is N
xindividual, containing element is Y (0)～Y (N
x-1).In prior art, there are various structures and implementation method to be suggested, to accelerate and to simplify FIR algorithm filter.
Chinese patent CN 1525642A discloses a kind of reconfigurable finite impulse response filter, and this filter construction has higher efficiency for fixation application occasion, and it is constructed as shown in Figure 1.With reference to Fig. 1, the course of work of this filter is as follows: according to the fixing filter factor number K in application scenario, then according to K digital processing element of this K filter coefficient design, K filter factor is pre-stored in digital processing element, when data to be filtered left side when input from Fig. 1, can complete the multiplying of K data to be filtered and K filter factor at every turn, and then laterally add up, obtain 1 filtering result, from the right output of the filter of FIR shown in Fig. 1.
Realizing in process of the present invention, applicant recognizes that prior art FIR filter exists following technological deficiency:
1) when filter factor K number is larger, prior art FIR filter is generally that each filter factor is multiplied each other with data to be filtered, obtain sub-result, this process is to have walked abreast, but while afterwards each sub-results added being obtained to filtering result, this cumulative required time directly depends on filter factor number, when filter factor number is larger, the critical path of filtering result output is very long, has a strong impact on its operating efficiency;
2) digital processing element number is limited to filter factor number, must determine in application scenario after the number of filter factor, and number that could stationary digital processing unit, lacks application flexibility.After filter system is fixing, this filter system is only applicable to a kind of application scenario, and the required filter factor number of this occasion is fixed;
3) in one-dimensional filtering application, data to be filtered exist principle of locality, load the data that repeat and make the service efficiency of data to be filtered very low, the reference to storage repeating in addition has larger time overhead on the one hand, can increase on the other hand the power consumption of system.
Summary of the invention
(1) technical problem that will solve
For solving above-mentioned one or more problems, the invention provides a kind of finite pulse response FIR filter, to improve the operating efficiency of FIR filter.
(2) technical scheme
According to an aspect of the present invention, provide a kind of finite pulse response FIR filter.This FIR filter comprises: filter factor provides module, for K the filter factor that prestore; At n execution cycle, receive and read after enable signal, 1 filter factor H (i) is provided; Data to be filtered provide module, for the N that prestores
xindividual data to be filtered; At n execution cycle, receive and read after enable signal, 1 data group to be filtered is provided, this data group to be filtered comprises BS data to be filtered: X (nBS-i), X (nBS-i+1) ..., X[(n+1) and BS-i-1], when the vector index of data to be filtered is less than 0, these data to be filtered are with 0 replacement; Multiplier, comprises a parallel BS multiplication unit; Each multiplication unit all provides module to provide module to be connected with data to be filtered with filter factor, for realizing the product calculation of 1 data to be filtered of filter factor H (i) and data group to be filtered; Accumulator, its control end is connected with comparator, comprises parallel BS cumulative unit; Each cumulative unit and corresponding multiplication unit are connected with deposit unit in accumulator register, for realizing the accumulating operation of the current result of product of multiplication unit and the intermediate data of deposit unit; Accumulator also for: when receiving the output useful signal of comparator, the group filtering result output using BS accumulation result as n; Otherwise, using BS accumulation result as intermediate data, export respectively deposit unit corresponding in accumulator register to; Accumulator register, comprises BS deposit unit; The input of each deposit unit is connected with input with the output of corresponding cumulative unit respectively with output, for depositing the intermediate data of accumulating operation; Comparator, for carrying out the comparison operation of computing sequence number and filter factor number K, when computing sequence number=K-1, to accumulator, send output useful signal, carry out subsequently n+1 execution cycle, computing sequence number is in n execution cycle, the product calculation having completed or the number of times of accumulating operation.
(3) beneficial effect
From technique scheme, FIR filter of the present invention has following beneficial effect:
1) high efficiency of parallel computation, the present invention adopts BS parallel multiplication unit, can carry out BS multiplying simultaneously, BS multiplication result walked abreast and carry out BS add operation with corresponding register intermediate value simultaneously, thereby greatly improved operation efficiency, save operation time, and all control signals have been all digital signals, avoid the computing inaccuracy that adopts the analogue units such as delay cell to bring, improved operational precision;
2) reconfigurability, in the filter factor number situation of the present invention in spatial cache size range, all obtain efficient filter effect, even when the number of filter factor changes, as long as it is within the scope of spatial cache, just need not again change corresponding hardware, thereby realize goodish reconstruct;
3) data high usage to be filtered, the present invention passes through in whole algorithm level analysis, use data buffer to be filtered and filter factor buffer structure, take full advantage of data locality principle to be filtered, do not repeat to load the phenomenon of data to be filtered, and every access primary memory, can draw BS result, reduce memory accesses, thereby reach the effect of " once reading; repeatedly calculate ", and then reduce the power consumption of whole design.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art FIR filter;
Fig. 2 is the structural representation of embodiment of the present invention FIR filter;
Fig. 3 is the schematic diagram of filter factor buffer in embodiment of the present invention FIR filter;
Fig. 4 is the schematic diagram of data buffer to be filtered in embodiment of the present invention FIR filter;
Fig. 5 a be embodiment of the present invention FIR filter data buffer memory space to be filtered when BS=4 be under 4BS coding and initialization after schematic diagram;
Fig. 5 b is the schematic diagram of data buffer to be filtered after displacement as shown in Fig. 4 a;
Fig. 6 is the schematic diagram of the effective offset address generation of embodiment of the present invention FIR filter figure;
Fig. 7 a be embodiment of the present invention FIR filter data buffer memory space to be filtered when BS=4 be under 5BS coding and initialization after schematic diagram;
Fig. 7 b is the schematic diagram of data buffer to be filtered after displacement as shown in Figure 6 a;
Fig. 8 a is the schematic diagram that in embodiment of the present invention FIR filter, filter factor is stored in memory;
Fig. 8 b is the schematic diagram that in embodiment of the present invention FIR filter, filter factor is stored in filter factor buffer;
Fig. 9 a is the schematic diagram that in embodiment of the present invention FIR filter, data to be filtered are stored in memory;
Fig. 9 b is the schematic diagram that in embodiment of the present invention FIR filter, data to be filtered are stored in data buffer to be filtered;
Figure 10 a is the schematic diagram that embodiment of the present invention FIR filter carries out the 1st multiply accumulating computing;
Figure 10 b is the schematic diagram that embodiment of the present invention FIR filter carries out the 2nd multiply accumulating computing;
Figure 10 c is the schematic diagram that embodiment of the present invention FIR filter carries out the 18th multiply accumulating computing;
The schematic diagram that Figure 11 A is the data storage after embodiment of the present invention data buffer initialization to be filtered when K '=BS+3;
Figure 11 B is the schematic diagram of the data storage after data buffer displacement to be filtered described in Figure 11 A;
The schematic diagram that Figure 12 A is the data storage after embodiment of the present invention data buffer initialization to be filtered when K '=3BS+2;
Figure 12 B is the schematic diagram of the data storage after data buffer displacement to be filtered described in Figure 12 A.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.Although the demonstration of the parameter that comprises particular value can be provided herein, should be appreciated that, parameter is without definitely equaling corresponding value, but can in acceptable error margin or design constraint, be similar to described value.
Applicant finds, the algorithm of FIR filter in formula 1 can be expanded into following result:
For FIR algorithm filter as implied above, launch result, filter factor is used has following rule:
(1) with regard to the row at each dotted line frame place, each multiplier carries out computing by BS data to be filtered in a filter factor and dotted line frame, and the BS of this process multiplication can be concurrent operation;
(2) result after parallel adds up again, and cumulative process is right-to-left as implied above, can draw common BS the result of Y (0)～Y (BS-1) after cumulative K time.Wherein, often draw BS result, use respectively filter factor H (K-1), H (K-2), H (K-3) ..., H (1), H (0).
Therefore, filter factor buffer is had to 2 requirements: 1, read at every turn and return to a filter factor; 2, be separated by and read for K time, the value of returning is the same.According to above-mentioned result, the number of filter factor is K, and the number of operational data is BS.
For FIR algorithm filter as implied above, launch result, data to be filtered are used has following rule:
(1), for the adjacent dotted line frame in left and right, it uses data to be filtered only to have a difference.
(2), in neighbouring BS filtering result computing, there are BS data to be filtered not re-use, with stylish use BS data to be filtered.For example, while calculating Y (BS)～Y (2BS-1), data X to be filtered (K+1)～X (BS-K) does not re-use, data X to be filtered (BS-K+1)～X (BS-1) continues to use, and has newly increased the use of data X to be filtered (BS)～X (2BS-1) simultaneously.
(3) data X vector to be filtered, the minus part of its index value, by zero replacement.Be X (1), X (2) in above formula ..., X (K+1) is zero.
According to above-mentioned rule, can design a kind of novel data buffer to be filtered, this data buffer to be filtered at least meets following 4 requirements: 1, read buffer at every turn and can return to BS data to be filtered; 2, reading of adjacent twice buffer, the BS returning a data to be filtered the inside, only has a value different; 3, often complete K computing, produced after BS filtering result, this buffer has an overall renewal, and this renewal, by the BS bringing into use most rejection of data to be filtered, newly loads BS the data to be filtered in memory; 4, buffer provides corresponding zero padding region, and effectively zero number is K-1.
Technical in above-mentioned filter factor and data rule to be filtered, applicant proposes a kind of FIR filter, to improve the service efficiency of filter factor and data to be filtered, reduces the read-write number of times to memory, improves arithmetic speed.
In one exemplary embodiment of the present invention, a kind of FIR filter has been proposed.Fig. 2 is the structural representation of embodiment of the present invention FIR filter.As shown in Figure 2, the present embodiment FIR filter comprises: filter factor buffer 20, data buffer to be filtered 30, multiplier 40, accumulator register 50, accumulator 60 and comparator 70.The peripheral components of this FIR filter also comprises memory 10.
Accumulator 60, its control end is connected with comparator, comprises parallel BS cumulative unit; Each cumulative unit and corresponding multiplication unit are connected with deposit unit in accumulator register, for the current result of product of cumulative described multiplication unit and the intermediate data of deposit unit.When receiving the output useful signal of comparator, this accumulator is organized the output of filtering result using BS accumulation result as n; Otherwise, using this BS accumulation result as intermediate data, export respectively deposit unit corresponding in accumulator register to.
It should be noted that, n gets 0,1,2,3 successively ..., ceil (N
x/ BS)-1, ceil is the symbol to contiguous larger integer value, ceil (N
x/ BS)-1 group of filtering result be as N
xthe filtering result of individual data to be filtered.
In addition, the principle that in the present embodiment, data to be filtered and filter factor are chosen is, not homogeneous read the filter factor difference that enable signal correspondence provides, and not homogeneous read the data group difference to be filtered that enable signal is corresponding.In general, can select one by one filter factor and data group to be filtered, as long as guarantee that K computing do not repeat mutually.Certainly, for the algorithm as FIR filter, launch result, have two kinds of usual computational methods, a kind of method is to calculate successively from right-to-left, and another kind of method is to calculate successively from left to right.Preferably, for the algorithm of FIR filter, launch result, from right-to-left, calculate successively, i get successively K-1, K-2 ..., 1,0 (will describe in detail hereinafter).
In order can more to have known, understand the present embodiment, existing generation and output to its timing control signal describes.As shown in Figure 2, the output useful signal of comparator is used to refer to current BS the filtering result that completed on the one hand, the output that is current accumulator 60 is effective, is used to refer on the other hand current effectively (will describe in detail hereinafter) of shift signal that outputs to data buffer 30 to be filtered.In addition, by multiplier 40, outputed to the enable signal of reading of filter factor buffer 20, be used to refer to current multiplier 40 and need to read filter factor buffer 20; By multiplier 40, outputed to the enable signal of reading of data buffer 30 to be filtered, be used to refer to current multiplier 40 and need to read data buffer 30 to be filtered.Certainly, this reads enable signal also can be issued to filter factor buffer and data buffer to be filtered by comparator or accumulator, be one of them of comparator, multiplier and accumulator, also, for when the computing sequence number < K-1, to described filter factor, provide module and described data to be filtered to provide module to send and read enable signal.
From the present embodiment, can find out, be different from FIR filter of the prior art, the present invention adopts BS parallel multiplication unit, can carry out BS multiplying simultaneously, BS multiplication result be carried out to BS add operation with corresponding register intermediate value is parallel simultaneously, thereby greatly improved operation efficiency, save operation time, and all control signals are all digital signals, avoided the computing inaccuracy that adopts the analog components such as delay cell to bring, improved operational precision.
Adopt parallel multiplication unit and supporting adder and register in the present embodiment, can carry out BS concurrent operation simultaneously, this concurrent operation is a part of computing that produces BS filtering result, adopt the parallel of this form, make the quantity of arithmetic unit be independent of filter factor number, when filter factor increases, the parallel multiplication unit in reuse plan and supporting adder and register, have the flexibility of height.
The present embodiment FIR filter adopts filter factor buffer and data buffer to be filtered.In fact, also can adopt and can realize data to be filtered other memory devices of function are provided, as register etc.In order to reduce as far as possible reading memory, improve arithmetic speed and efficiency, for filter factor, the mode that the present invention adopts memory and buffer to mutually combine, filter factor is deposited in order in buffer from memory, take filter factor number K as the cycle, export a filter factor at every turn.Concrete technical scheme is as follows:
In the present embodiment, filter factor buffer 20, for reading filter factor from memory 10, is placed in buffer entity, and 1 filter factor H (i) is read in each filter computing in order.Fig. 3 is the schematic diagram of filter factor buffer in embodiment of the present invention FIR filter.As shown in Figure 3, this filter factor buffer 20 comprises that a buffer entity 201, one read logical block 202, initialization logic unit 203 and a logic with shift unit 204.Wherein:
Buffer entity 201, buffer memory is for the filter factor of computing, and its size is relevant with the size (BS) of arithmetic element, and buffer memory cell number is 2BS+1 herein, and is addressed to from top to bottom 0～2BS.
Read logical block 202 for the read operation to filter factor buffer, take filter factor number (K) as the cycle, return in order a filter factor.
Initialization logic unit 203 is for the initialization to buffer entity.From memory access, buffer entity 201 is carried out to assignment.
From the structure of above-mentioned filter factor buffer 20, can find out, there is not inevitable relation in arithmetic element number BS of the present invention and filter factor number K.In the situation that arithmetic element number BS is certain, if filter factor number K changes, do not need to change internal arithmetic unit number or size, as long as this filter factor number K is in the memory space ranges of filter factor buffer, just can meet the needs of computing completely, there is high degree of flexibility, thereby make the present invention there is good reconfigurability.Take the size of filter factor buffer as 2BS+1, can adapt to 2BS+1 the filtering operation within the scope of filter factor.For the ease of understanding, in explanation below, the largest filter coefficient number that can support take filter factor buffer is of a size of K ' as example.
In the present embodiment, filter factor buffer is to design for meeting the requirement to filter factor in filter implementation procedure, its function is for providing filter factor, its way of realization may be various, such as adopting 2BS+1 register, realize, and do not need added logic expense, but in each product calculation, which register multiplier need to be controlled from is got required coefficient.
Further, in order to improve raising the efficiency of data to be filtered, the parts that provide that the present invention also treats filtering data improve, in the present embodiment, data buffer 30 to be filtered, for reading data group to be filtered from memory 10, be placed in data buffer entity to be filtered, data group d to be filtered is read in each filter computing
k, wherein, d
kbe a vector [d
k[0], d
k[1] ..., d
k[BS-1]], d in FIR algorithm filter expansion
kthe part that vector index is less than 0, as X[-1], all with 0, replace.This buffer size is 4BS, the computing size that wherein BS is multiplier, the multiplying number that can simultaneously carry out.
Fig. 4 is the schematic diagram of data buffer to be filtered in embodiment of the present invention FIR filter.As shown in Figure 4, this data buffer to be filtered comprises data buffer entity 310 to be filtered, reads logical block 320, upgrades logical block 330.Wherein:
Buffer entity 310 buffer memorys are for the data to be filtered of computing.Its size is relevant with the size (BS) of arithmetic element demand, and size is 4BS size herein, and is addressed to 0～4BS-1.
Read logical block 330 for reading the data to be filtered of buffer.Its input signal is for reading enable signal, computing sequence number and filter factor number, and output signal comprises to buffer entity 10 sends effective offset address, obtains the data to be filtered of BS size, and by this data output to be filtered.
Wherein effectively offset address need to be according to computing sequence number, read enable signal and filter factor number produces.Corresponding relation is: when reading enable signal when effective, and effectively offset address=K '-K+ computing sequence number.Wherein computing sequence number be by arithmetic element (multiplication unit) according to the order of reading buffer memory, the number of reading of transmission, this computing sequence number, since 0, increases by 1 at every turn.For the present embodiment, the size of filter factor buffer entity is 2BS+1, this effective offset address=2BS+1-K+ computing sequence number.
Upgrade logical block 320 for upgrading the data content to be filtered of buffer entity, this structure comprises an initialization logic unit 321 and a logic with shift unit 322.Wherein:
Initialization logic unit is the operation in early stage to buffer entity 10 before arithmetic unit work.For the initialization to buffer entity, the partially-initialized that wherein address is 0～2BS-1 is 0, and address 2BS～4BS-1 part is from the value initialization of memory the inside.
Logic with shift unit 322 is for the integral shift to memory block entity data to be filtered, and, when input signal shift signal is effective, start working in logic with shift unit.
First suppose largest filter coefficient number K '=2BS+1 that one-dimensional filtering that data buffer to be filtered coordinates is supported, this data buffer physical size to be filtered is at least 4BS size, suppose arithmetic element size, i.e. simultaneously BS=4, actual filter factor number is K=6.
Known in conjunction with above-mentioned hypothesis, K '=9, treat data buffer physical size >=4BS=16 to be filtered, K=6.First take several buffer physical size, as 4BS=16 as example, the present invention will be further described below.
The incipient stage of using, the present embodiment need to first carry out initialization, now work in initialization logic unit 201, by the partially-initialized of several buffers address 0～7, be 0, by the partially-initialized of address 8～15, it is specific value, this value obtains from memory, can get BS=4 data to be filtered from memory at every turn, need to get altogether 2 times.Situation after buffer addressing and initialization as shown in Figure 5 a.
After initialization, the multiplier of arithmetic unit in adopting shown in Fig. 2 need to read this buffer, now reading logical block 330 starts working, according to the computing sequence number of input, read enable signal and maximum filter factor number and the actual filter factor number signal supported, produce effective offset address, thereby read the data to be filtered of tram.
In the present embodiment, because every generation BS=4 data to be filtered need to read buffer memory K=6 time, therefore computing sequence number be a string 0,1,2,3,4, the cyclic code of 5}.When producing during first group of BS=4 filtering result data, effective offset address=3,4,5,6,7,8}.This effective offset address produces figure as shown in Figure 6.So time front read for 6 times the data to be filtered that data buffer to be filtered returns be respectively 0,0,0,0}, 0,0,0,0}, 0,0,0,1}, 0,0,1,2}, 0,1,2,3}, 1,2,3,4}.
When after the multiplier computing in Fig. 2 K=6 time, can draw a front BS=4 end value, need afterwards to upgrade the value of buffer entity 310, from memory the inside value.The shift signal of now exporting to data buffer 30 to be filtered in Fig. 2 in FIR filter is effective, and buffer has an overall displacement, and the amplitude of displacement is BS=4.After displacement, buffer data to be filtered as shown in Figure 5 b.
Now drawn BS filtering output data, and buffer carries out the renewal of corresponding data to be filtered, coordinated arithmetic unit to carry out the computing of BS result data to be filtered below, read during this time buffer and renewal caching mechanism is constant.
Above-described embodiment is that buffer size is the situation of 4BS, and in fact this buffer is not limited only to 4BS size.Under the prerequisite of K '=2BS+ 1, take buffer entity 10 as 5BS sizes as example, introduce in detail the present invention below.
When buffer entity 310 sizes are 5BS, as shown in Figure 5 a, actual filter factor number (being less than or equal to 2BS) is K=6 in the distribution of same data to be filtered in memory, and buffer entity is addressed to 0～19.
When Fig. 7 a is the big or small 5BS of being of data buffer to be filtered, after initialization, the data to be filtered in buffer entity.Now compare size for the buffer of 4BS, after initialization many buffer memorys BS=4 data to be filtered.These do not affect the logical block 330 of reading of the present invention, it equally according to input computing sequence number, read enable signal and filter factor number signal, produce effective offset address, thereby read the data to be filtered of tram.
Same, first group of BS=4 filtering result data of every generation, effectively offset address distinguish=3,4,5,6,7,8}.This effective offset address produces figure as shown in Figure 6.So time front read for 6 times the data to be filtered that data buffer to be filtered returns be respectively 0,0,0,0}, 0,0,0,0}, 0,0,0,1}, 0,0,1,2}, 0,1,2,3}, 1,2,3,4}.
When after the multiplier computing in Fig. 2 K=6 time, can draw a front BS=4 end value, need afterwards to upgrade the value of data buffer entity 310 to be filtered, from memory the inside value.The shift signal of now exporting to data buffer 30 to be filtered in Fig. 2 is effective, and buffer has an overall displacement, and the amplitude of displacement is BS=4.After displacement, buffer data to be filtered are as shown in 7b.
Now drawn BS filtering output data, and buffer carries out the renewal of corresponding data to be filtered, coordinated arithmetic unit to carry out the computing of BS result data below, read during this time buffer and renewal caching mechanism is constant.
From the structure of above-mentioned data buffer 30 to be filtered, can find out, it fully takes into account Data duplication in algorithm and utilizes phenomenon, at memory, load after given number data, carry out abundant computing, according to algorithm requirement, after all computings that use this part data to be filtered all complete, just do the renewal of data buffer to be filtered, this part data to be filtered can again not be loaded in whole algorithm implementation procedure afterwards, improved like this data user rate to be filtered, reduced the number of times of reference to storage, solved when processor does one-dimensional filtering algorithm the powerful demand for number ability of processor, and then reduced the power consumption of whole design.
In the present embodiment, can simplify the function of data buffer to be filtered, the thing that data buffer to be filtered will be done is transferred arithmetic element (multiplication unit or cumulative unit) to and is done, such as the logic of reading that can reduced data buffer, the effective address of this part is produced to transfer to and read logical block and do.But initialization logic and more new logic are absolutely necessary.In a word, due to the demand of filter of the present invention to data, so designed this buffer.Can to the requirement of data, regard filter as requirement profile, and this data buffer to be filtered is a kind of most possible realization.Other realize all or part of sequential logic of this standard, can regard data buffer to be filtered of the present invention as.
In addition, the present embodiment pending data buffer is for the application scenario of different filter factor numbers, can, according to the zero padding of algorithm requirements intelligence, greatly facilitate programmer to carry out algorithm realization, and not need to consider to carry out for different coefficient length the zero padding operation of suitable number.
Certainly, also can adopt other data providing formula to be filtered, as data buffer to be filtered being divided into BS sub-buffer, BS corresponding each filter factor in n execution cycle data to be filtered are all stored to one of them of BS sub-buffer.In each multiplying, from sub-buffer, read whole data to be filtered to multiplier.Certainly, the internal memory that this data providing formula to be filtered expends is larger, and reading efficiency is lower.
By a concrete scene, be below that example is described below in detail the present invention: in the present embodiment, the computing size BS=16 of multiplier, each this multiplier can carry out 16 pairs of data and multiplies each other, corresponding, the size of filter factor buffer is 2*BS+1=33 data width to be filtered, the size of data buffer to be filtered is 4*BS=64 data width to be filtered, and multiplier has 16 parallel multiplication units, and accumulator has 16 parallel cumulative unit.The width of accumulator register is BS=16 data width.Not limiting data type herein, can be 64bit, 32bit, 16bit and 8bit data type.
In fact, in other algorithm of field of digital signals, such as convolution and related operation, its operating characteristic is realized with FIR filter, be data and multiplication, then add up and show that a result, filter provided by the invention and coefficient buffer thereof, data buffer can apply in this algorithm realization equally.
Suppose the filter factor number K=18 of filter, suppose that it distributes as shown in 8a in memory.Before computing starts, need to carry out the initialization of filter factor buffer 20 and data buffer to be filtered 30.After initialization, interior 18 the required filter factors of filtering of having stored of filter factor buffer 20, as shown in Figure 8 b.
Complete after the initialization of buffer, multiplier starts corresponding data to be filtered to carry out computing, in order to make full use of the data to be filtered in data buffer to be filtered, multiplier often obtains once effectively result, carry out altogether K=18 computing, during each computing, call filter factor buffer 20 and data buffer to be filtered 30 once.
Treat calling of filtering data buffer 30 at every turn and can return to BS=16 data to be filtered, multiplier 40 is treated calling for K=18 time of filtering data buffer 30 can return to d
0, d
1, d
2, d
17, their are the data to be filtered in K=18 square frame of the first half right-to-left in corresponding FIR algorithm filter expansion respectively.So d
0～d
17width be the width of BS=16 data to be filtered, equal form sign with one-dimension array in describing in the back, i.e. d
0[0]～d
0[15] represent d
0, d
17[0]～d
17[15] represent d
17.The implementation structure of data buffer to be filtered has guaranteed that its data to be filtered that provide are the data to be filtered that filtering algorithm needs.
Particularly, suppose data to be filtered in the distribution of memory and data buffer to be filtered 30 respectively as shown in 8a and 8b.D
0[0]～d
0[15]=0,0,0 ..., 0}, d
1[0]～d
1[15]=0,0,0 ..., 0} ..., d
17[0]～d
17[15]=1,2,3 ..., 16}.
Figure 10 a to Figure 10 c has described above-mentioned through K=18 computing, draws the process of BS result, is in fact also a cumulative hardware of K right-to-left of FIR filter deployment algorithm is realized and being described.
Wherein Figure 10 a has described the process of the 1st multiply accumulating, and now the value in accumulator register 50 is 0, after accumulation calculating, and filter factor k
17and d
0the end value of each element product put into accumulator register, completed k
17d
0[0], k
17d
0[1], k
17d
0[2] ..., k
17d
0[15] computing.
Figure 10 b is the process of the 2nd multiply accumulating, and the result that now multiplier 40 is exported is k
16and d
1the product of each element, accumulator is added this result and accumulation result last time (value in current accumulator register 50), obtains result k
17d
0[0]+k
16d
1[0], k
17d
0[1]+k
16d
1[1], k
17d
0[2]+k
16d
1[2] ..., k
17d
0[15]+k
16d
1and put into accumulator register 50 [15]; Residue k
15～k
1similar with the calculating process of data d2～d16 to be filtered.
Figure 10 c is the process of the 18th multiply accumulating, is now still the result of multiplier 40 and accumulator register 50 are added.Through above-mentioned 18 computings, can draw BS=16 result, be equivalent to do the cumulative of following equation sequence:
k
17d
0[0]+k
16d
1[0]+…+k
2d
15[0]+k
1d
16[0]+k
0d
17[0]、
k
17d
0[1]+k
16d
1[1]+…+k
2d
15[1]+k
1d
16[1]+k
0d
17[1]、
k
17d
0[2]+k
16d
1[2]+…+k
2d
15[2]+k
1d
16[2]+k
0d
17[2]、
……、
k
17d
0[15]+k
16d
1[15]+…+k
2d
15[15]+k
1d
16[15]+k
0d
17[15]，
Above-mentioned sequence is the expression formula of filtering result Y (0)～Y (15).
If input data to be filtered, all do not carry out filtering operation, need to upgrade data buffer 30 to be filtered, after the complete BS of every calculating data to be filtered, send to shift signal of data buffer to be filtered, data buffer to be filtered is in integral shift, from memory the inside value again.Repeat afterwards the collaborative calculating process of multiplier 40 and accumulator 60, until the whole calculating of data to be filtered is complete.
Special instruction, if data amount check N to be filtered
xcan not be divided exactly by BS, whole calculating process remains unchanged, but in BS the result that computing draws the last time, only has N
mindividual effective filtering result data, N
mfor N
xdivided by the remainder of BS gained.While for the last time data being write back to memory, only by this N
mindividual effective result writes back.
In above-mentioned each embodiment, K '=2BS+ 1, the maximum number filter factor size that K ' can support for the filter that this filtered data providing apparatus is applied to, therefore, the size that in data supplying device to be filtered, buffer is implemented is K '-1+2BS=4BS.Those skilled in the art should be appreciated that K ' is not only limited to 2BS+1, describe respectively below as an example of K '=BS+3 and K '=3BS+2 example.As follows:
When K '=BS+3, embodiment is as follows: now buffer sizes is at least 3BS+2.Still suppose arithmetic element size simultaneously, i.e. BS=4, actual filter factor number is K=6, now K '=7, buffer size is at least 14.
The incipient stage of using, the present embodiment need to first carry out initialization, now work in initialization logic unit 201, by the partially-initialized of several buffers address 0～5, be 0, by the partially-initialized of address 6～13, it is specific value, this value obtains from memory, can get BS=4 data to be filtered from memory at every turn, need to get altogether 2 times.Situation after buffer addressing and initialization as shown in Figure 11 A.
After initialization, the multiplier of arithmetic unit in adopting shown in Fig. 2 need to read this buffer, now reading logical block 330 starts working, according to the computing sequence number of input, read enable signal and maximum filter factor number and the actual filter factor number signal supported, produce effective offset address, thereby read the data to be filtered of tram.
In the present embodiment, because every generation BS=4 data to be filtered need to read buffer memory K=6 time, therefore computing sequence number be a string 0,1,2,3,4, the cyclic code of 5}.When producing during first group of BS=4 filtering result data, effective offset address=1,2,3,4,5,6}.This effective offset address produces as shown in Figure 6.So time front read for 6 times the data to be filtered that data buffer to be filtered returns be respectively 0,0,0,0}, 0,0,0,0}, 0,0,0,1}, 0,0,1,2}, 0,1,2,3}, 1,2,3,4}.
When after the multiplier computing in Fig. 2 K=6 time, can draw a front BS=4 end value, need afterwards to upgrade the value of buffer entity 310, from memory the inside value.The shift signal of now exporting to data buffer 30 to be filtered in Fig. 2 in FIR filter is effective, and buffer has an overall displacement, and the amplitude of displacement is BS=4.After displacement, buffer data to be filtered as shown in Figure 11 B.
Now drawn BS filtering output data, and buffer carries out the renewal of corresponding data to be filtered, coordinated arithmetic unit to carry out the computing of BS result data to be filtered below, read during this time buffer and renewal caching mechanism is constant.
When K '=3BS+ 2, embodiment is as follows: now buffer sizes is at least 5BS+1.Still suppose arithmetic element size simultaneously, i.e. BS=4, actual filter factor number is K=6, now K '=14, buffer size is at least 21.
The incipient stage of using, the present embodiment need to first carry out initialization, now work in initialization logic unit 201, by the partially-initialized of several buffers address 0～12, be 0, by the partially-initialized of address 13～20, it is specific value, this value obtains from memory, can get BS=4 data to be filtered from memory at every turn, need to get altogether 2 times.Situation after buffer addressing and initialization is as shown in Figure 12 A.
After initialization, the multiplier of arithmetic unit in adopting shown in Fig. 2 need to read this buffer, now reading logical block 330 starts working, according to the computing sequence number of input, read enable signal and maximum filter factor number and the actual filter factor number signal supported, produce effective offset address, thereby read the data to be filtered of tram.
In the present embodiment, because every generation BS=4 data to be filtered need to read buffer memory K=6 time, therefore computing sequence number be a string 0,1,2,3,4, the cyclic code of 5}.When producing during first group of BS=4 filtering result data, effective offset address=8,9,10,11,12,13}.This effective offset address produces as shown in Figure 6.So time front read for 6 times the data to be filtered that data buffer to be filtered returns be respectively 0,0,0,0}, 0,0,0,0}, 0,0,0,1}, 0,0,1,2}, 0,1,2,3}, 1,2,3,4}.
When after the multiplier computing in Fig. 2 K=6 time, can draw a front BS=4 end value, need afterwards to upgrade the value of buffer entity 310, from memory the inside value.The shift signal of now exporting to data buffer 30 to be filtered in Fig. 2 in FIR filter is effective, and buffer has an overall displacement, and the amplitude of displacement is BS=4.After displacement, buffer data to be filtered as shown in Figure 12 B.
Now drawn BS filtering output data, and buffer carries out the renewal of corresponding data to be filtered, coordinated arithmetic unit to carry out the computing of BS result data to be filtered below, read during this time buffer and renewal caching mechanism is constant.
Special instruction, if data amount check N to be filtered
xcan not be divided exactly by BS, whole calculating process remains unchanged, but in BS the result that computing draws the last time, only has N
mindividual effective filtering result data, N
mfor N
xdivided by the remainder of BS gained.While for the last time data being write back to memory, only by this N
mindividual effective result writes back.
The realization of above-mentioned filter can be applied in the design of filter of FPGA, also can be by this filter rows for being defined as a processor instruction, in the inner realization of ASIC.
From above-described embodiment, FIR filter of the present invention has following beneficial effect:
1) high efficiency of parallel computation, the present invention adopts BS parallel multiplication unit, can carry out BS multiplying simultaneously, BS multiplication result walked abreast and carry out BS add operation with corresponding register intermediate value simultaneously, thereby greatly improved operation efficiency, save operation time, and all control signals have been all digital signals, avoid the computing inaccuracy that adopts the analogue units such as delay cell to bring, improved operational precision;
2) reconfigurability, the present invention is based on the FIR filter of multiply accumulating device, within the scope of 2BS filter factor, all obtain efficient filter effect, even when the number of filter factor changes, as long as it,, within the scope of spatial cache, just need not again be changed corresponding hardware, thereby realize goodish reconstruct;
3) data high usage to be filtered, the present invention passes through in whole algorithm level analysis, use data buffer 30 to be filtered and coefficient buffer 20 structures, take full advantage of data locality principle to be filtered, do not repeat to load the phenomenon of data to be filtered, and every access primary memory, can draw BS result, reduce memory accesses, thereby reach the effect of " once reading; repeatedly calculate ", and then reduce the power consumption of whole design.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a finite pulse response FIR filter, is characterized in that, comprising:
Filter factor provides module, for K the filter factor that prestore; At n execution cycle, receive and read after enable signal, 1 filter factor H (i) is provided;
Data to be filtered provide module, for the N that prestores
xindividual data to be filtered; At n execution cycle, receive and read after enable signal, 1 data group to be filtered is provided, this data group to be filtered comprises BS data to be filtered: X (nBS-i), X (nBS-i+1) ..., X[(n+1) and BS-i-1], when the vector index of data to be filtered is less than 0, these data to be filtered are with 0 replacement, and wherein, described n gets 0,1,2,3 successively,, ceil (N
x/ BS)-1, ceil is the symbol to contiguous larger integer value; Described i get successively K-1, K-2 ..., 1,0;
Multiplier, comprises a parallel BS multiplication unit; Each multiplication unit all provides module to provide module to be connected with described data to be filtered with described filter factor, for realizing the product calculation of 1 data to be filtered corresponding to described data group to be filtered and described filter factor H (i);
Accumulator, its control end is connected with comparator, comprises parallel BS cumulative unit; Each cumulative unit and corresponding multiplication unit are connected with deposit unit in accumulator register, for realizing the accumulating operation of the current result of product of described multiplication unit and the intermediate data of described deposit unit; Described accumulator also for: when receiving the output useful signal of described comparator, the group filtering result output using BS accumulation result as n; Otherwise, using a described BS accumulation result as intermediate data, export respectively deposit unit corresponding in accumulator register to;
Described accumulator register, comprises BS deposit unit; The input of each deposit unit is connected with input with the output of corresponding cumulative unit respectively with output, for depositing the intermediate data of described accumulating operation;
Described comparator, for carrying out the comparison operation of computing sequence number and filter factor number K, when computing sequence number=K-1, to described accumulator, send output useful signal, carry out subsequently n+1 execution cycle, described computing sequence number is in n execution cycle, the product calculation having completed or the number of times of accumulating operation.
2. FIR filter according to claim 1, is characterized in that, in each execution cycle, described computing sequence number is since 0, and each computing increases by 1,
One of them of described multiplier and accumulator, also for providing described computing sequence number to described comparator; And/or
One of them of described comparator, multiplier and accumulator, also for when the computing sequence number <K-1, provides module and described data to be filtered to provide module to send to described filter factor and reads enable signal.
3. FIR filter according to claim 2, is characterized in that, described filter factor provides module to comprise:
Second memory, for storing a described K filter factor;
The second buffer entity, comprises the individual memory cell of K ', K ' >=K;
The second initialization logic unit, be connected with the second buffer entity with described second memory, be used for a described K filter factor, H[K-1], H[K-2] ..., H[1] and H[0] from described second memory from A-P buffer into successively described the second buffer entity K memory cell;
Second reads logical block, for receiving, reads after enable signal, take K as the cycle, by the filter factor reading successively from the order of A-P in described the second buffer entity stores unit, and this filter factor is sent to described multiplier.
4. FIR filter according to claim 3, is characterized in that, described K'=2BS+1.
5. FIR filter according to claim 3, is characterized in that,
Described comparator, also for when computing sequence number=K-1, provides module to send shift signal to described data to be filtered;
Described data to be filtered provide module to comprise:
First memory, for storing successively N
xindividual data to be filtered;
The first buffer entity, comprises at least K '-1+2BS memory cell, and this K '-1+2BS memory cell is for buffer memory data to be filtered;
The first initialization logic unit, at the 0th execution cycle, carries out initialization to described the first buffer entity, and the memory cell that is 0～K '-2 by address is initialized as 0; By data X to be filtered (0), X (1), X (2) ..., X (2BS-1) buffers into from described first memory the memory cell that the address of described the first buffer entity is K '-1～K '-2+2BS successively;
First reads logical block, its control end is connected with described comparator, described in being used for receiving, read after enable signal, take effective offset address as starting point, according to the data to be filtered that read successively BS memory cell in described the first buffer entity from the order of A-P, and this BS data to be filtered are sent to described multiplier;
The first logic with shift unit, its control end is connected with described comparator, for receiving after the shift signal of described comparator, by BS the position of data reach to be filtered in the memory cell that in described the first buffer entity, address is BS to K '-2+2BS; From described first memory, read successively BS data to be filtered and buffer into successively the memory cell that in described the first buffer entity, address is K '-1+BS～K '-2+2BS.
6. FIR filter according to claim 5, is characterized in that, described data to be filtered provide the first buffer entity in module to comprise 4BS or 5BS memory cell.
7. FIR filter according to claim 5, is characterized in that, during described K '=2BS+1, and described effective offset address=K '-K+ computing sequence number.
8. FIR filter according to claim 7, is characterized in that, it is same memory that described filter factor provides first memory in module and described data to be filtered that second memory in module is provided; This memory is also for storing described n group filtering result.
9. according to the FIR filter described in any one in claim 1 to 8, it is characterized in that,
The relation of described filtering result, filter factor and data to be filtered is as follows:
Y(0)＝H(0)X(0)+H(1)X(-1)+H(2)X(-2)+…+H(K-1)X(-K+1)
Y(1)＝H(0)X(1)+H(1)X(0)+H(2)X(-1)+…+H(K-1)X(-K+2)
Y(2)＝H(0)X(2)+H(1)X(1)+H(2)X(0)+…+H(K-1)X(-K+3)
……
Y(BS-1)＝H(0)X(BS-1)+H(1)X(BS-2)+H(2)X(BS-3)+…+H(K-1)X(BS-K)
Y(BS)＝H(0)X(BS)+H(1)X(BS-1)+H(2)X(BS-2)+…+H(K-1)X(BS-K+1)
Y(BS+1)＝H(0)X(BS+1)+H(1)X(BS)+H(2)X(BS-1)+…+H(K-1)X(BS-K+2)
Y(BS+2)＝H(0)X(BS+2)+H(1)X(BS+1)+H(2)X(BS)+…+H(K-1)X(BS-K+3)
……
Y(2BS-1)＝H(0)X(2BS-1)+H(1)X(2BS-2)+H(2)X(2BS-3)+…+H(K-1)X(2BS-K)
……
Y(N
x-1)＝H(0)X(N
x-1)+H(1)X(N
x-2)+H(2)X(N
x-2)+…+H(k-1)X(
N x -K)
Wherein, described H (0), H (1), H (2) ..., H (K-1) is K coefficient to be filtered;
Described X (K+1), X (K+2), X (K+3), X (BS-K) ..., X (0), X (1), X (2) ..., X (BS-1), X (BS), X (BS+1), X (BS+2) ..., X (2BS-1), X (N
x-1) be N
xindividual data to be filtered;
Described Y (0), Y (1), Y (2) ..., Y (BS-1) is the 0th group of filtering result; Y (BS), Y (BS+1), Y (BS+2) ..., Y2BS-1) be the 1st group of filtering result; Y (N
x-1) be last the filtering result in last 1 group of filtering result.
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| CN103227622B (en) * | 2013-04-19 | 2016-07-06 | 中国科学院自动化研究所 | A kind of parallel filtering method and corresponding device |
| WO2014169480A1 (en) * | 2013-04-19 | 2014-10-23 | 中国科学院自动化研究所 | Parallel filtering method and corresponding apparatus |
| CN103760411A (en) * | 2013-11-06 | 2014-04-30 | 国网安徽省电力公司淮南供电公司 | Direct-current bus voltage wave-recording device |
| CN103761075B (en) * | 2014-02-10 | 2017-01-25 | 东南大学 | Coarse granularity dynamic reconfigurable data integration and control unit structure |
| CN113258902B (en) * | 2021-04-29 | 2022-02-22 | 睿思芯科(深圳)技术有限公司 | Processor, filtering method and related equipment |
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