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Two-channel seamless digit delay implementation method based on field programmable gate array (FPGA)

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CN103066997A
CN103066997A CN 201210497093 CN201210497093A CN103066997A CN 103066997 A CN103066997 A CN 103066997A CN 201210497093 CN201210497093 CN 201210497093 CN 201210497093 A CN201210497093 A CN 201210497093A CN 103066997 A CN103066997 A CN 103066997A
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data
delay
storage
channel
time
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CN 201210497093
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CN103066997B (en )
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崔明雷
钱璐
邹林
于雪莲
周云
汪学刚
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电子科技大学
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Abstract

The invention provides a two-channel seamless digit delay implementation method based on a field programmable gate array (FPGA). The defects that an existing delay line delays time for replacing and switching and occupies system processing time, and system work efficiency is lowered are overcome. The work characteristics of first input first output (FIFO) are fully considered, two FIFO data storage areas which are identical in structure are adopted, and channels corresponding to different data storage areas are arranged and selected according to the different delay time requirements to output data. When one channel is rearranged, another channel outputs the data continuously. When the channels are rearranged and written full, the states of the two channels are switched by a system, the data of a data storage area which is arranged up to the minute are read, so that the time delay between input data and output data of the corresponding channel of the data storage area meets the current requirements, and an idle state for waiting the data to be output which occurs in the system and is caused by switching of the data storage area is avoided. Therefore, seamless switching of different delay outputs is achieved, and an authentic echo environment can be better simulated.

Description

—种基于FPGA的双通道无缝数字延迟实现方法 - based on the kind of dual-channel seamless digital delay FPGA Implementation

技术领域 FIELD

[0001] 本发明属于信号处理技术,具体涉及数字延迟技术。 [0001] The present invention pertains to signal processing techniques, particularly directed to digital delay technology.

背景技术 Background technique

[0002] 延迟是信号处理的一个基本操作,随着数字技术的发展,数字延迟线在雷达、通信等领域得到越来越广泛的应用。 [0002] The delay is a basic operation of the signal processing, with the development of digital technology, digital delay line to be more widely used in the field of radar and communications. 采用FPGA芯片,通过硬件编程实现数字延迟线是当前的一个设计趋势。 Using FPGA chip, digital delay line is the current through a programmed hardware design trends. 采用FPGA芯片实现数字延迟,其延迟的时长是通过预设队列FIFO(先入先出队列)中数据存储区的长度来实现的。 FPGA chip using a digital delay, the delay of which duration is achieved through a preset queue FIFO (first in first out queue) length of the data storage area. 如图1所示,当需要延时N个时钟周期,则设置数据存储区的长度为N。 1, when it is desired delayed by N clock cycles, then the length of the data storage area provided is N. 这样,本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的实施方法,应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。 Thus, those of ordinary skill in the art will appreciate that embodiments described herein are to aid the reader in understanding the method of the present embodiment of the invention, it should be understood that the scope of the present invention is not limited to such embodiments and specifically stated . 本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。 Those of ordinary skill in the art can make various modifications and other various concrete compositions of the present invention without departing from the spirit of techniques according to teachings of the present disclosure, it is still within the scope of the present invention such variations and combinations. 数据存储区中写指针指向存储单元与读指针指向存储单元间隔了长度N。 The data storage area and the write pointer to the read pointer of the memory cell storage unit interval length N. 每一个时钟周期,FPGA芯片向写指针指向存储单元写入数据;当数据存储区被写满后,每一个时钟周期FPGA芯片由读指针指向存储单元读取数据。 Each clock cycle, the FPGA chip pointing to the memory cell to write data to the write pointer; when the data store is filled, FPGA chip per clock cycle by the read pointer points to the memory cell to read data. 即从数据写入数据存储区到数据从数据存储区被读出就间隔了N个时钟周期,从而实现输入数据与输出数据之间延时N个时钟周期。 I.e. write data from the storage area to the data from the data storage area is read out to an interval of N clock cycles, to achieve delayed by N clock cycles between input data and output data.

[0003] 在雷达信号模拟中,根据目标的运动规律,回波信号时延会有增大或减小的变化,需对信号进行不同时长的延时处理。 [0003] In the simulation of radar signals in accordance with the movement of the target echo signals delay variation be increased or decreased, the need for signal processing are not simultaneously long delay. 在输出延时时长需修改时,应将FIFO中数据存储区清空,按照新的时长重新设置数据存储区大小后,等待数据装满再输出新的时延的数据。 Need to modify the duration, should the data storage area when the output delay FIFO empty, the length of time according to the new data storage area resized after waiting for a new re-output the data fill delay data. 数据存储区切换所需的系统处理时间(将清空FIFO并按照新的时长重新装载数据需要耗费的系统处理时间)导致系统出现等待数据输出的空闲状态。 System processing time required for switching the data storage area (FIFO empty and the length of time according to the new data reloading system takes processing time) cause the system to an idle state waiting for data output. 由于真实的回波环境并不存在这样的空闲状态,因此灵活地改变FPGA实现不同数字时延大小的切换,避免出现空闲状态以实现“无缝”变得越来越重要。 As the true echo environment is not the existence of such an idle state, and therefore the flexibility to change FPGA implementation of digital delay switch to a different size, to avoid idle state in order to achieve "seamless" is becoming increasingly important.

发明内容 SUMMARY

[0004] 本发明所要解决的技术问题是,提供一种基于FPGA的无缝数字延迟线实现方法。 [0004] The present invention solves the technical problem is to provide a seamless FPGA-based digital delay line implementation.

[0005] 本发明为解决上述技术问题所采用的技术方案是,一种基于FPGA的双通道无缝数字延迟实现方法,包括以下步骤: [0005] Technical Solution The present invention to solve the above technical problem is based on FPGA seamless digital two-channel delay implemented method, comprising the steps of:

[0006] 初始设置两片FIFO数据存储区的大小;选择两片数据存储区中的一片为输出状态,另一片为仅写入状态;需进行延时的数据不间断依序同时送入两片数据存储区; [0006] Initial size two FIFO data set storage region; selecting one of two output state data storage area, a write only state other sheet; continuous data need to be delayed while sequentially into two a data storage area;

[0007] 当数据存储区被写满后,开始读取并输出处于输出状态的数据存储区的读指针指向存储单元的数据,另一片处于仅写入状态数据存储区写满后数据溢出; [0007] When the data storage area is filled, and starts reading the output data storage area in the read pointer pointing to the output state data storage units, another piece is written only after the data storage area filled state data overflow;

[0008] 当输出数据相对于输入数据的延迟需要进行调整时,在继续对输出状态的数据存储区进行读取的同时,对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度为目标延时长度;待重新设置后的处于仅写入状态的数据存储区重新写满后,根据时序切换两片数据存储区的状态。 [0008] When the output data with respect to the input data of the delay needs to be adjusted, while continuing the state of the output data storage area is read only in the write state of the data storage area for emptying and re-sets the data storage the length of the delay length as a target region; after the setting is only to be re-written to re-state data storage area is full, timing data store two state switch. [0009] 本发明为了克服现有延迟线延迟时间更改切换占用系统处理时间,降低系统工作效率的不足,充分考虑到FIFO的工作特点,采用两个相同结构的FIFO数据存储区,按不同延迟时间要求来设置并选择不同数据存储区对应的通道来输出数据,当一个通道在进行重新设置时,另一个通道还在不间断输出数据,当通道重新设置并写满时,系统切换两个通道的状态,读取最新设置的数据存储区的数据,使得从该数据存储区对应通道的输入数据与输出数据之间的延时满足当前要求并避免了数据存储区切换导致系统出现等待数据输出的空闲状态。 [0009] The present invention is to overcome the conventional delay line occupancy changes switching system processing time and reduce the efficiency of the system is insufficient, fully taking into account the working characteristics of the FIFO, the FIFO data storage area using two identical structures, different time delays required to set and select a different data storage area corresponding to the output data channel, when a channel during reset, another channel is still continuously output data, and reset when the channel is full, two-channel system switching a state data storage area, reads the latest set such that the delay between the corresponding channel from the data store input data and output data to meet current requirements and avoid idle datastore cause switching occurring in the system waits for the data output status.

[0010] 更进一步的,为了使得本发明的延时的实时性最强,输出数据相对于输入数据的延迟需要进行调整的时机为:根据目标运动规律与数据存储区切换所需的系统处理时间,在目标延时变化之前,预先对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度,使得状态切换完成后该数据存储区开始输出数据时,输出数据相对于输入数据满足当前时刻对应的变化后目标延时。 [0010] Further still, in order to make the most real-time, the output data is delayed with respect to the present invention, the data input of the delay time need to be adjusted as follows: the processing time required for the switching system in accordance with the movement of the target and the data storage area , before the target delay variation, in advance in the write state only data storage area for emptying and re-set the length of the data storage area of ​​the data storage area such that when the start switch status after the completion of data output, the data output relative to the input data corresponding to the change in time to meet the current target delay. 即,在目标延时变化之前,根据数据存储区切换所需的系统处理时间提前开始进行数据存储区切换处理,待数据存储区切换完成后,输出数据的延时满足变化后的目标延时要求。 That is, before the target delay variation, the switching system processing time required to store the data in advance to start handover processing data storage area, after the handover completion of the data storage area, delay output data of the target after the change to meet the latency requirements .

[0011] 本发明的有益效果是,通过两个结构相同的FIFO数据存储区的交替设置与交替输出实现不同延迟输出的无缝切换,可以更好地模拟出真实的回波环境。 [0011] Advantageous effects of the present invention is to seamlessly switch alternately outputs different delay provided alternately outputs the same as the structure of the two FIFO data storage region by, may be better simulate the real echo environment.

附图说明 BRIEF DESCRIPTION

[0012] 图1为现有FPGA芯片实现数字延迟的示意图; [0012] FIG. 1 is a conventional FPGA chip digital delay schematic;

[0013] 图2为实施例FPGA芯片实现数字延迟的示意图。 [0013] FIG. 2 is a digital delay schematic embodiment FPGA chip embodiment.

具体实施方式 detailed description

[0014] 如图2所示,实现数字延迟线需要用到:1、两个可预置数据存储区大小的FIFO,用于保存输入数据;用于将带延迟的数据分送到两个这数据存储区的分线器;多路模拟开关MUX,用于选择不同数据存储区对应通道的数据作为输出数据。 [0014] 2, the digital delay line need to use: 1, two pre-FIFO size data storage area for storing input data; Delayed for data which is distributed to two splitter data storage area; analog multiplexer MUX, for selecting a different data storage areas corresponding to channel data as output data. FIFO采用FPGA的IP核实现。 FIFO using IP core FPGA. FIFO数据区大小采用USEDW信号设置。 FIFO data block size setting signal USEDW employed. FIFO数据区清空采用CLR信号控制。 FIFO data area using clear CLR signal.

[0015] 基于FPGA的双通道无缝数字延迟实现方法,以模拟的回波环境中目标的运动越来越近,回波信号时延逐渐减小为例,步骤如下: [0015] Based on the delay FPGA seamless digital dual channel method, to simulate the motion of an object in echo getting closer environment, gradually decreases the echo signal delay an example, the following steps:

[0016] 步骤一、设置两片FIFO数据存储区的初始大小,FIF01设置长度为N,FIF02设置长度为N-1。 [0016] Step a, set the initial size of the two FIFO data storage area, FIF01 set length N, FIF02 set of length N-1. FIFO的存取方式:连续写入时,数据依序输入写指针指向的存储单元;读取时,从读指针指向的存储单元读取数据,设置数据存储区长度后,输出数据延迟时间与存储区长度对应。 FIFO access mode: Continuous writing, the write data is sequentially input pointer memory means; reading, data is read from the memory cell read pointer, after the length of the setting data storage area, and stores output data of the delay time the length of the corresponding region.

[0017] 步骤二、输入数据依序同时送入FIF01和FIF02,直至数据区被写满。 [0017] Step two, the input data sequentially into FIF01 and simultaneously FIF02, until the data area is filled.

[0018] 步骤三、数据写满后,由MUX根据当前的目标延迟值选择从FIF01或FIF02读指针指向的存储单元读取数据。 [0018] Step three, the data is filled, the MUX delay value from the selected memory cell or FIF02 FIF01 the read pointer to read data based on the current target.

[0019] 当选择某一片FIFO进行读取数据,则MUX将开通该FIFO的输出通道,即该FIFO处于数据输出的状态;另一片FIFO数据不能输出,处于仅写入状态,数据写满后溢出。 [0019] When a select a read data FIFO, the FIFO will open the MUX output channel, i.e., the state data output from the FIFO; not another piece of data output FIFO, only in the write state, the data is filled with the overflow . 选择由FIF01读数时,输出数据相对于输入数据延迟N个时钟周期;选择由FIF02读数时,输出数据相对于输入数据延迟N-1个时钟周期。 When reading from the selected FIF01, output data delayed by N clock periods relative to the input data; FIF02 select a reading, the output data of the N-1 clock delay period relative to the input data. [0020] 步骤四、如当前选择FIF02进行数据输出。 [0020] Step 4 FIF02 currently selected as the output data. 在对FIF02读数的同时,根据目标运动规律,下一次时延调整所需延迟由N-1个时钟周期调整为N-2个时钟周期,此时可通过控制信号CLR将FIFOl清空,设置USEDW,使得FIFOl数据存储区长度为N-2,待FIFOl重新写满后,根据时序切换为由FIFOl输出,输出数据相对于输入数据延迟N-2个时钟周期。 In FIF02 while reading, the movement of the target, the next time delay is adjusted by adjusting the desired delay of N-1 N-2 clock cycles to clock cycles, this time by controlling the FIFOl clear signal CLR provided USEDW, such FIFOl datastore length N-2, until FIFOl filled again, the switching timing by FIFOl output, the output data is delayed N-2 clock cycles with respect to the input data.

[0021] 步骤五、当输出数据相对于输入数据的延迟需由N-2调整为N-3个时钟周期时,可在对FIFOl读数的同时,通过控制信号CLR将FIF02清空,设置USEDW,使得FIF02数据存储区长度为^3,待FIF02重新写满后,根据时序切换为由FIF02输出,输出数据相对于输入数据延迟N-3个时钟周期。 [0021] Step (5) When the output data with respect to the delayed input data required by the N-2 was adjusted to N-3 clock cycles, it can be simultaneously FIFOl reading, by the control signal CLR to FIF02 empty, set USEDW, such that FIF02 datastore length ^ 3, to be re-filled FIF02, FIF02 by a timing switch output, the output data delay N-3 clock cycles with respect to the input data.

[0022] 通过交替设置、切换FIFOl与FIF02,可实现信号时延由N_3个时钟周期到I个时钟周期的变化。 [0022] By alternately setting the switching FIFOl FIF02, by the signal delay variations N_3 I clock cycles to clock cycles can be achieved.

[0023] 达到需调整的时延后,停止切换FIFO工作状态。 [0023] When the need to adjust the delay reached, stops the switching operation state FIFO.

[0024] 经过上述步骤处理,即可得到符合延时要求的输出信号,由于两个不同延迟时间的延迟输出分别由两片FIFO实现,并通过切换开关进行选择,可实现无缝延迟,避免系统出现等待数据输出的空闲状态。 [0024] Through the above process steps, to obtain an output signal meet latency requirements, due to the delayed output two different delay times, respectively, the FIFO is implemented by two, and are selected by switching the switch, the delay may be seamless to avoid system idle state waiting for data output occurs.

[0025] 可选的,在步骤一中,对数据存储区的初始大小进行设置时,两片FIFO的长度也可以设置为相同或不同长度。 [0025] Optionally, in step one, during the initial size of the data storage area is set, the length of the two FIFO may be set to the same or different lengths. 如设置为不同长度,两片FIFO的长度之差可以是延迟调整的步长,实施例中设置的延迟调整步长为I个时钟周期,当然也不仅限于此,可以根据实际需求将2或3甚至更长的时钟周期作为延迟调整步长。 If set to different lengths, the length difference of two FIFO delay may be adjusted in steps, the delay adjustment step is provided in Example I clock cycles, of course, not limited thereto, according to the actual demand 2 or 3 even longer period as the clock delay adjustment steps.

[0026] 可选的,在步骤三中,实施例MUX对初始化之后的两片FIFO进行第一读取选择是在FIFO写满之后。 [0026] Alternatively, in step three, after a first embodiment of the read select MUX is filled in the FIFO of the FIFO after two initialization. 同样的,也可以在两片FIFO初始设置时默认某一片FIFO为初始读取的对象,默认其为输出状态,当该FIFO写满后对该FIFO读指针指向存储单元进行读取并由MUX开通该FIFO的输出通道。 The same may be the default when two objects in a FIFO initial setting an initial reading of the FIFO, which is the default output state, when the FIFO is full the FIFO is read by the read MUX pointer points to the opening of the storage unit the output channel FIFO.

[0027] 用于选择不同数据存储区对应通道的数据作为输出数据的模块不限于现多路模拟开关MUX还可以是其它相同选择功能的模块。 [0027] for selecting a different data storage region corresponding to the channel as a data module output data is not limited to existing analog multiplexer MUX to select the same may be another function module. 甚至,这个选择模块可以同时接收来自两个FIFO对应通道的数据,再根据目标延时选择输出一个通道(输出状态)的数据,丢弃另一个通道(仅写入状态)的数据。 Indeed, the selection module can receive data simultaneously from two corresponding channel FIFO, and then outputs a channel selection data (output state) according to the target delay, discarding the other channel (the write state only) data.

[0028] 实施例 [0028] Example

[0029] 采用雷达信号模拟器作为平台,根据模拟目标与雷达的相对位置和目标的运动方式,从目标进入雷达波束主瓣到目标离开雷达波束主瓣,一共收到M个回波脉冲。 [0029] The radar signal simulator as a platform, according to the relative position and motion simulation target object and the radar, the radar beam main lobe away from the object enters the radar beam main lobe to the target, M total received echo pulses. 其第一个脉冲重复周期的回波信号与发射信号间的延迟为500时钟周期,第二个脉冲重复周期的回波信号与发射信号间的延迟为499时钟周期,以此类推,第M个回波信号与发射信号间的延迟为500-M+1个时钟周期,因此需设置的FIFO大小为50(T500-M+1。 The delay between the transmitted signal and the echo signal which is a first pulse repetition period of 500 clock cycles, the delay between the transmitted signal and the echo signals a second pulse repetition period of 499 clock cycles, and so on, of the M delay between the echo signals of the transmitted signal 500-M + 1 clock cycles, so the size of the FIFO to be set to 50 (T500-M + 1.

[0030] 步骤一、设置两片FIFO数据存储区的大小,FIF01设置长度为500,FIF02设置长度为499。 [0030] Step a, sets the size of two FIFO data storage area, FIF01 set length 500, FIF02 length is set 499.

[0031] 步骤二、数据依序同时送入FIF01和FIF02,直至数据区被写满。 [0031] Step two, the data sequentially and simultaneously into FIF01 FIF02, until the data area is filled.

[0032] 步骤三、数据写满后,根据模拟目标与雷达的相对位置和目标的运动方式,由选择开关选择首先从FIF01中读取数据,输出数据相对于输入数据延迟500个时钟周期;当目标延迟需要调整为499时,由选择开关选择从FIF02中读取数据,输出数据相对于输入数据延迟499个时钟周期。 [0032] Step three, the data is filled, in accordance with the relative position and motion of the target and radar simulation target, the data is first read from FIF01 by the selection switch, the output data of the phase delay of 500 clock cycles input data; when delay needs to be adjusted to the target 499, the read data selected by the selector switch from FIF02, the output data of the delay 499 clock periods relative to the input data. [0033] 步骤四、根据实施例假设条件,在对FIF02读数的同时,下一次所需时延应调整为498,则通过控制信号CLR将FIFOl清空,设置USEDW,使得FIFOl数据存储区减少2个长度单位,待FIFOl重新写满后,根据时序切换为由FIFOl输出,输出数据相对于输入数据延迟498个时钟周期。 [0033] Step four, according to embodiments assumptions, while reading of FIF02, next desired delay should be adjusted to 498, by controlling the FIFOl clear signal CLR provided USEDW, so that the data storage area reduction FIFOl 2 after the unit of length to be re-filled FIFOl The switching timing by FIFOl output, the output data of the delay 498 with respect to the input data clock cycles.

[0034] 步骤五、在对FIFOl读数的同时,下一次所需时延应调整为497,则通过控制信号CLR将FIF02清空,设置USEDW,使得FIF02数据存储区减少两个单元,待FIF02重新写满后,根据时序切换为由FIF02输出,输出数据相对于输入数据延迟497个时钟周期。 [0034] Step 5 of FIFOl while reading the next time should be adjusted to the desired delay 497, by controlling the FIF02 clear signal CLR provided USEDW, such that the data store FIF02 two reduction units, to be re-written FIF02 is full, switching timing by FIF02 output, the output data of the delay 497 with respect to the input data clock cycles.

[0035] 步骤六、交替进行步骤四和步骤五,可实现信号时延由498个时钟周期到50(T500-M+1个时钟周期的变化。 [0035] Step 6 and Step four alternating Step five, the signal delay can be achieved by a 50 to 498 clock cycles (variation T500-M + 1 clock cycles.

[0036] 本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的实施方法,应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。 [0036] Those of ordinary skill in the art will appreciate that embodiments described herein are to aid the reader in understanding the method of the present embodiment of the invention, it should be understood that the scope of the present invention is not limited to such embodiments and specifically stated example. 本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。 Those of ordinary skill in the art can make various modifications and other various concrete compositions of the present invention without departing from the spirit of techniques according to teachings of the present disclosure, it is still within the scope of the present invention such variations and combinations.

Claims (9)

1. 一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,包括以下步骤: 初始设置两片FIFO数据存储区的大小;选择两片数据存储区中的一片为输出状态,另一片为仅写入状态;需进行延时的数据不间断依序同时送入两片数据存储区; 当数据存储区被写满后,开始读取并输出处于输出状态的数据存储区的数据,另一片处于仅写入状态数据存储区写满后数据溢出; 当输出数据相对于输入数据的延迟需要进行调整时,在对输出状态的数据存储区进行读取的同时,对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度;待重新设置数据存储区的长度后,处于仅写入状态的数据存储区开始缓存数据,重新写满后,根据时序切换两片数据存储区的状态。 An FPGA-based dual-channel seamless digital delay implemented method comprising the steps of: setting the size of the initial two FIFO data storage region; selecting a data storage area in two of the output state, the other sheet a write state only; delay of data to be continuously performed while sequentially storing data into two regions; when the data store is filled, starts reading the data and outputs the data storage area in the output state, and the other after writing in a data storage area filled with only the status data overflow; when the output data is to be adjusted with respect to the delayed input data, while the data storage area of ​​the output state of the read, write only in the state of datastore for emptying and re-set the length of the data storage area; after resetting the length of the data storage area, at the beginning of the data cache store data is written only state, re-filled, two switching timing data storage state area.
2.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,输出数据相对于输入数据的延迟需要进行调整的时机为:根据目标运动规律与数据存储区切换所需的系统处理时间,在目标延时变化之前,预先对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度,使得状态切换完成后该数据存储区开始输出数据时,输出数据相对于输入数据满足当前时刻对应的变化后目标延时。 2. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that the output data with respect to the input of the delay time data need to be adjusted to: switch the data storage area according to the movement of the target when the processing time required by the system, before the target delay variation, in advance in the write state only data storage area for emptying and re-set the length of the data storage area, such that the output of the data storage area starts after the state switching completion data , the output data with respect to input data corresponding to the current time satisfies the target delay variation.
3.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对数据存储区的初始大小进行设置时,两片FIFO数据存储区的长度设置为相同长度。 The seamless 1 FPGA-based dual-channel digital delay as claimed in claim implemented method, wherein, when the initial size of the data storage area is set, the length of the two FIFO data set storage region to be the same length.
4.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对数据存储区的初始大小进行设置时,两片FIFO数据存储区的长度设置为不同长度,两片FIFO的长度之差为延迟调整的步长。 As claimed in claim 1 based on the dual-channel seamless digital delay FPGA implementation method, wherein, when the initial size of the data storage area is set, the length of the FIFO data storage area is set to two different lengths, difference in length of the two-step delay adjustment FIFO is long.
5.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对初始化设置之后的两片数据存储区进行第一次状态选择是在数据存储区第一次写满之后。 5. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that, for two data storage area after the initialization settings for the first time a state is selected in the first data storage area filled later.
6.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对初始化设置之后的两片数据存储区进行第一次状态选择是对数据存储区进行数据写入之前。 6. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that, for two data storage area after the initialization settings for the first time a state is selected for data writing Datastore into before.
7.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,所述两片FIFO数据存储区采用FPGA的IP核实现。 7. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that the two FIFO data storage area using the IP core FPGA.
8.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,采用USEDW信号对两片FIFO数据存储区大小进行设置。 8. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that the two signals using USEDW FIFO data storage area size setting.
9.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,采用CLR信号控制数据存储区清空。 9. The seamless 1 FPGA-based digital dual-channel delay implemented method as claimed in claim, characterized in that, using the data storage area control signal CLR cleared.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104731550A (en) * 2015-03-12 2015-06-24 电子科技大学 Double-clock bidirectional digital delay method based on single FIFO

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884099A (en) * 1996-05-31 1999-03-16 Sun Microsystems, Inc. Control circuit for a buffer memory to transfer data between systems operating at different speeds
CN101118529A (en) * 2007-08-10 2008-02-06 北京理工大学 Two-channel DSPEED-DAC_D1G board
CN101123586A (en) * 2007-09-21 2008-02-13 北京锐安科技有限公司 Method for using FPGA to process network data packets in optical network
CN101826888A (en) * 2010-03-15 2010-09-08 中国电子科技集团公司第十研究所 Processing method of automatically calibrating sum-and-difference passage spread spectrum code phase to coincidence
CN102163980A (en) * 2011-05-17 2011-08-24 中国电子科技集团公司第十研究所 Method for processing consistency of sum-difference channel signal transmission delays through automatic calibration

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884099A (en) * 1996-05-31 1999-03-16 Sun Microsystems, Inc. Control circuit for a buffer memory to transfer data between systems operating at different speeds
CN101118529A (en) * 2007-08-10 2008-02-06 北京理工大学 Two-channel DSPEED-DAC_D1G board
CN101123586A (en) * 2007-09-21 2008-02-13 北京锐安科技有限公司 Method for using FPGA to process network data packets in optical network
CN101826888A (en) * 2010-03-15 2010-09-08 中国电子科技集团公司第十研究所 Processing method of automatically calibrating sum-and-difference passage spread spectrum code phase to coincidence
CN102163980A (en) * 2011-05-17 2011-08-24 中国电子科技集团公司第十研究所 Method for processing consistency of sum-difference channel signal transmission delays through automatic calibration

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104731550A (en) * 2015-03-12 2015-06-24 电子科技大学 Double-clock bidirectional digital delay method based on single FIFO
CN104731550B (en) * 2015-03-12 2017-10-17 电子科技大学 A delay-based single bidirectional digital clock fifo double

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