CN108389833B - 显示基板及其制造方法和显示装置 - Google Patents

显示基板及其制造方法和显示装置 Download PDF

Info

Publication number
CN108389833B
CN108389833B CN201810251783.9A CN201810251783A CN108389833B CN 108389833 B CN108389833 B CN 108389833B CN 201810251783 A CN201810251783 A CN 201810251783A CN 108389833 B CN108389833 B CN 108389833B
Authority
CN
China
Prior art keywords
semiconductor pattern
data line
forming
manufacturing
display substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810251783.9A
Other languages
English (en)
Other versions
CN108389833A (zh
Inventor
庄子华
陈曦
廖加敏
吴振钿
李大海
林琳琳
汤高攀
洪贵春
王进
邱鑫茂
石常洪
吕耀朝
刘家荣
李宗祥
林鸿涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Fuzhou BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Fuzhou BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201810251783.9A priority Critical patent/CN108389833B/zh
Publication of CN108389833A publication Critical patent/CN108389833A/zh
Priority to US16/211,870 priority patent/US10943928B2/en
Application granted granted Critical
Publication of CN108389833B publication Critical patent/CN108389833B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Abstract

本发明公开了一种显示基板及其制造方法和显示装置。该方法包括：在衬底基板之上形成栅线、半导体图形和数据线，所述半导体图形和所述数据线之间对应设置；从所述数据线的靠近所述半导体图形的一侧，通过设定波长的光对所述半导体图形进行照射，以使所述半导体图形的带隙中产生悬挂键缺陷态。本发明中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。

Description

显示基板及其制造方法和显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种显示基板及其制造方法和显示装置。
背景技术
随着显示技术的发展，液晶显示装置的应用越来越广泛。液晶显示装置中数据线和公共电极线之间形成耦合电容。当数据线上的数据电压发生变化时，公共电极线上的公共电压会由于耦合作用而发生畸变 (Distortion)，偏离正常电位。
现有技术中，若液晶显示装置中的显示基板是采用4mask工艺制成时，数据线下方存在半导体图形，从而会造成耦合振荡。
发明内容
本发明提供一种显示基板及其制造方法和显示装置，用于减小耦合振荡的现象。
为实现上述目的，本发明提供了一种显示基板的制造方法，包括：
在衬底基板之上形成栅线、半导体图形和数据线，所述半导体图形和所述数据线之间对应设置；
从所述数据线的靠近所述半导体图形的一侧，通过设定波长的光对所述半导体图形进行照射，以使所述半导体图形的带隙中产生悬挂键缺陷态。
可选地，所述在衬底基板之上形成栅线、半导体图形和数据线包括：
在所述衬底基板之上形成栅线；
在所述栅线之上形成栅极绝缘层；
在所述栅绝缘层之上形成半导体图形和数据线。
可选地，所述在所述衬底基板之上形成栅线的同时还包括：形成公共电极、公共电极线和栅极，所述栅线和所述栅极同层设置，所述公共电极和所述公共电极线同层设置；
所述在所述栅绝缘层之上形成半导体图形和数据线的同时还包括：形成半导体图形、有源层图形、源极和漏极，所述半导体图形和所述有源层图形同层设置，所述源极、所述漏极和所述数据线同层设置，所述数据线和所述半导体图形相邻层设置。
可选地，所述从所述数据线的靠近所述半导体图形的一侧，通过设定波长的光对所述半导体图形进行照射之前还包括：
在所述衬底基板的上方形成钝化层，钝化层覆盖整个衬底基板；
在所述钝化层上形成过孔；
在所述钝化层之上形成像素电极，所述像素电极通过所述过孔与所述漏极连接。
可选地，所述从所述数据线的靠近所述半导体图形的一侧，通过紫外光对所述半导体图形进行照射之后还包括：
在所述衬底基板的上方形成钝化层，钝化层覆盖整个衬底基板；
在所述钝化层上形成过孔；
在所述钝化层之上形成像素电极，所述像素电极通过所述过孔与所述漏极连接。
可选地，所述设定波长的光为紫外光；
所述通过设定波长的光对所述半导体图形进行照射包括：
通过紫外光以设定照射量对所述半导体图形进行照射。
可选地，所述设定照射量为3000毫焦至10000毫焦。
可选地，所述设定照射量为5000毫焦至7000毫焦。
可选地，所述半导体图形的材料为氢化非晶硅。
为实现上述目的，本发明提供了一种显示基板，所述显示基板采用上述显示基板的制造方法而制成。
为实现上述目的，本发明提供了一种显示装置，包括上述显示基板。
可选地，所述显示装置包括液晶显示装置或者OLED显示装置。
本发明具有以下有益效果：
本发明提供的显示基板及其制造方法和显示装置的技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
附图说明
图1为本发明实施例一提供的一种显示基板的制造方法的流程图；
图2为本发明实施例二提供的一种显示基板的制造方法的流程图；
图3a为实施例二中形成栅线、公共电极线、公共电极和栅极的示意图；
图3b为图3a中A-A向剖视图；
图3c为实施例二中形成半导体层和源漏极层的示意图；
图3d为实施例二中B-B向剖视图；
图3e为实施例二中薄膜晶体管T的示意图；
图4为实施例二中进行紫外光照射的示意图；
图5为本发明实施例三提供的一种显示基板的制造方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的显示基板及其制造方法和显示装置进行详细描述。
图1为本发明实施例一提供的一种显示基板的制造方法的流程图，如图1所示，该方法包括：
步骤101、在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置。
步骤102、从数据线的靠近半导体图形的一侧，通过设定波长的光对半导体图形进行照射，以使半导体图形的带隙中产生悬挂键缺陷态。
优选地，设定波长的光为紫外光。
本实施例提供的显示基板的制造方法的技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
图2为本发明实施例二提供的一种显示基板的制造方法的流程图，如图2所示，该方法包括：
步骤201、在衬底基板之上形成栅线、公共电极线、公共电极和栅极。
图3a为实施例二中形成栅线、公共电极线、公共电极和栅极的示意图，图3b为图3a中A-A向剖视图，如图3a和图3b所示，在衬底基板1 之上形成栅线2、公共电极线3、公共电极4和栅极5。
具体地，步骤201包括：
步骤2011、在衬底基板1之上连续形成公共电极材料层和栅极材料层，栅极材料层位于公共电极材料层之上。
步骤2012、对栅极材料层和公共电极材料层进行一次构图工艺，形成栅线2、公共电极线3、公共电极4和栅极5。
其中，栅线2和栅极5的下方形成有剩余公共电极图形6。
步骤202、在栅线、公共电极线、公共电极和栅极之上形成栅极绝缘层。
步骤203、在栅绝缘层之上形成半导体图形、有源层图形、数据线、源极和漏极，数据线和半导体图形相邻层设置。
图3c为实施例二中形成半导体层和源漏极层的示意图，图3d为实施例二中B-B向剖视图，图3e为实施例二中薄膜晶体管T的示意图，如图3c、图3d和图3e所示，在栅绝缘层7之上形成半导体图形9、有源层图形10、数据线8、源极11和漏极12，数据线8位于半导体图形9之上。
具体地，步骤203包括：
步骤2031、在栅绝缘层7之上连续形成半导体材料层和源漏极材料层。
优选地，半导体材料层的材料为氢化非晶硅。
步骤2032、对半导体材料层和源漏极材料层进行一次构图工艺，形成半导体图形9、有源层图形10、数据线8、源极11和漏极12。
其中，半导体图形9和有源层图形10同层设置，半导体图形9和有源层图形10通过半导体材料层制成；数据线8、源极11和漏极12同层设置，源极11和漏极12通过源漏极材料层制成。如图3a和图3c所示，薄膜晶体管T包括栅极2、有源层图形10、源极11和漏极12，有源层图形 10位于栅极2的上方。
优选地，半导体图形9的材料为氢化非晶硅。
步骤204、在完成步骤203的衬底基板之上形成钝化层，钝化层覆盖整个衬底基板。
由于钝化层覆盖整个衬底基板，因此钝化层位于有源层图形10、数据线8、源极11和漏极12之上。
步骤205、对钝化层进行构图工艺，在钝化层上形成过孔，该过孔位于漏极的上方。
步骤206、在钝化层之上形成像素电极，像素电极通过过孔与漏极连接。
其中，部分像素电极位于过孔中以实现与漏极连接。
步骤207、从数据线的靠近半导体图形的一侧，通过紫外光对半导体图形进行照射，以使半导体图形的带隙中产生悬挂键缺陷态。
图4为实施例二中进行紫外光照射的示意图，如图4所示，从数据线8的靠近半导体图形9的一侧，通过紫外光对半导体图形9进行照射。具体地，通过紫外光从衬底基板1的远离数据线8的一侧进行照射。
优选地，通过紫外光以设定照射量对半导体图形9进行照射。
本实施例中，数据线8之下设置半导体图形9，半导体图形9的材料可以为氢化非晶硅。当紫外光照射到半导体图形9时，半导体图形9会发生光致衰退效应(Steabler Wronski效应，简称SW效应)，光照导致带隙中产生悬挂键缺陷态，非晶硅中悬挂键缺陷态可俘获载流子而降低载流子密度和寿命，进而导致形成电子极化偶极矩减小，从而使得半导体图形9的介电常数ε减小。由于公共电极线和数据线之间形成耦合电容，根据耦合电容公式C＝εS/d可知，当介电常数ε减小，耦合电容也减小。其中由于半导体图形9位于数据线8之下，也就是说，半导体图形9位于数据线8和公共电极线3之间，因此耦合电容公式中的介电常数ε为半导体图形9的介电常数。当紫外光照射半导体图形9时，介电常数ε减小，从而导致耦合电容减小。耦合电容减小，使得公共电压畸变的幅值(ΔV)和恢复时间(ΔT)均减小，从而减小了耦合振荡的现象。设定照射量为3000 毫焦至10000毫焦，优选地，设定照射量为5000毫焦至7000毫焦，从而能够更好的实现减小耦合振荡的现象。
本实施例中，当显示基板应用于液晶显示装置时，减小了耦合振荡，从而有效减少了液晶显示装置的线残像。
本实施例中，当显示基板应用于OLED显示装置时，减小了耦合振荡，从而有效减少了OLED显示装置的串扰现象。
如图3e所示，当通过紫外光从衬底基板1的远离数据线8的一侧进行照射时，由于栅极2的阻挡，有源层图形10避免了被紫外光进行照射。
本实施例是在显示基板制造过程中通过紫外光固化(UV cure)设备对有源层图形10进行照射的，也就是说，在对盒工艺之前就完成了紫外线照射处理过程，从而避免了液晶劣化的风险。紫外光照射工艺流程简单，无需新增设备，改进成本小。
本实施例提供的显示基板的制造方法的技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
图5为本发明实施例三提供的一种显示基板的制造方法的流程图，如图5所示，该方法包括：
步骤301、在衬底基板之上形成栅线、公共电极线、公共电极和栅极。
对步骤301的具体描述可参见上述实施例二中步骤201的描述，此处不再赘述。
步骤302、在栅线、公共电极线、公共电极和栅极之上形成栅极绝缘层。
步骤303、在栅绝缘层之上形成半导体图形、有源层图形、数据线、源极和漏极，数据线位于半导体图形之上。
对步骤303的具体描述可参见上述实施例二中步骤203的描述，此处不再赘述。
步骤304、从数据线的靠近半导体图形的一侧，通过紫外光对半导体图形进行照射，以使半导体图形的带隙中产生悬挂键缺陷态。
对步骤304的具体描述可参见上述实施例二中步骤207的描述，此处不再赘述。
步骤305、在完成步骤304的衬底基板之上形成钝化层，钝化层覆盖整个衬底基板。
由于钝化层覆盖整个衬底基板，因此钝化层位于有源层图形、数据线、源极和漏极之上。
步骤306、对钝化层进行构图工艺，在钝化层上形成过孔，该过孔位于漏极的上方。
步骤307、在钝化层之上形成像素电极，像素电极通过过孔与漏极连接。
其中，部分像素电极位于过孔中以实现与漏极连接。
本实施例提供的显示基板的制造方法的技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
本发明实施例三提供了一种显示基板，该显示基板采用上述实施例一或者实施例二提供的显示基板的制造方法而制成。
本实施例中，显示基板可包括阵列基板或者OLED显示基板。
本实施例提供的显示基板的技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
本发明实施例四提供了一种显示装置，该显示装置包括实施例三提供的显示基板。
本实施例中，显示装置包括液晶显示装置，则显示基板可以为阵列基板；或者，显示装置包括OLED显示装置，则显示基板可以为OLED显示基板。
本实施例提供的显示装置技术方案中，在衬底基板之上形成栅线、半导体图形和数据线，半导体图形和所述数据线之间对应设置，从数据线的靠近半导体图形的一侧通过设定波长的光对半导体图形进行照射以使半导体图形的带隙中产生悬挂键缺陷态，使得公共电压畸变的幅值和恢复时间均减小，从而减小了耦合振荡的现象。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

1.一种显示基板的制造方法，其特征在于，包括：
在衬底基板之上形成栅线、半导体图形和数据线，所述半导体图形和所述数据线之间对应设置；
从所述数据线的靠近所述半导体图形的一侧，通过设定波长的光对所述半导体图形进行照射，以使所述半导体图形的带隙中产生悬挂键缺陷态；
所述设定波长的光为紫外光；所述通过设定波长的光对所述半导体图形进行照射包括：通过紫外光以设定照射量对所述半导体图形进行照射。
2.根据权利要求1所述的显示基板的制造方法，其特征在于，所述在衬底基板之上形成栅线、半导体图形和数据线包括：
在所述衬底基板之上形成栅线；
在所述栅线之上形成栅极绝缘层；
在所述栅极绝缘层之上形成半导体图形和数据线。
3.根据权利要求2所述的显示基板的制造方法，其特征在于，所述在所述衬底基板之上形成栅线的同时还包括：形成公共电极、公共电极线和栅极，所述栅线和所述栅极同层设置，所述公共电极和所述公共电极线同层设置；
所述在所述栅极绝缘层之上形成半导体图形和数据线的同时还包括：形成半导体图形、有源层图形、源极和漏极，所述半导体图形和所述有源层图形同层设置，所述源极、所述漏极和所述数据线同层设置，所述数据线和所述半导体图形相邻层设置。
4.根据权利要求3所述的显示基板的制造方法，其特征在于，所述从所述数据线的靠近所述半导体图形的一侧，通过设定波长的光对所述半导体图形进行照射之前还包括：
在所述衬底基板的上方形成钝化层，钝化层覆盖整个衬底基板；
在所述钝化层上形成过孔；
在所述钝化层之上形成像素电极，所述像素电极通过所述过孔与所述漏极连接。
5.根据权利要求3所述的显示基板的制造方法，其特征在于，所述从所述数据线的靠近所述半导体图形的一侧，通过紫外光对所述半导体图形进行照射之后还包括：
在所述衬底基板的上方形成钝化层，钝化层覆盖整个衬底基板；
在所述钝化层上形成过孔；
在所述钝化层之上形成像素电极，所述像素电极通过所述过孔与所述漏极连接。
6.根据权利要求1所述的显示基板的制造方法，其特征在于，所述设定照射量为3000毫焦至10000毫焦。
7.根据权利要求6所述的显示基板的制造方法，其特征在于，所述设定照射量为5000毫焦至7000毫焦。
8.根据权利要求1至7任一所述的显示基板的制造方法，其特征在于，所述半导体图形的材料为氢化非晶硅。
9.一种显示基板，其特征在于，所述显示基板采用权利要求1至8任一所述的显示基板的制造方法而制成。
10.一种显示装置，其特征在于，包括权利要求9所述的显示基板。
11.根据权利要求10所述的显示装置，其特征在于，所述显示装置包括液晶显示装置或者OLED显示装置。
CN201810251783.9A 2018-03-26 2018-03-26 显示基板及其制造方法和显示装置 Active CN108389833B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810251783.9A CN108389833B (zh) 2018-03-26 2018-03-26 显示基板及其制造方法和显示装置
US16/211,870 US10943928B2 (en) 2018-03-26 2018-12-06 Display substrate, method for manufacturing the same and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810251783.9A CN108389833B (zh) 2018-03-26 2018-03-26 显示基板及其制造方法和显示装置

Publications (2)

Publication Number Publication Date
CN108389833A CN108389833A (zh) 2018-08-10
CN108389833B true CN108389833B (zh) 2021-01-29

Family

ID=63072219

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810251783.9A Active CN108389833B (zh) 2018-03-26 2018-03-26 显示基板及其制造方法和显示装置

Country Status (2)

Country Link
US (1) US10943928B2 (zh)
CN (1) CN108389833B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826534A (zh) * 2009-03-05 2010-09-08 株式会社半导体能源研究所 半导体装置及其制造方法
CN203367291U (zh) * 2013-07-29 2013-12-25 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN205507319U (zh) * 2016-04-13 2016-08-24 北京京东方显示技术有限公司 阵列基板、显示面板和显示装置
CN106158581A (zh) * 2015-03-26 2016-11-23 北大方正集团有限公司 一种对布线后晶圆进行合金化处理的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826534A (zh) * 2009-03-05 2010-09-08 株式会社半导体能源研究所 半导体装置及其制造方法
CN203367291U (zh) * 2013-07-29 2013-12-25 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN106158581A (zh) * 2015-03-26 2016-11-23 北大方正集团有限公司 一种对布线后晶圆进行合金化处理的方法
CN205507319U (zh) * 2016-04-13 2016-08-24 北京京东方显示技术有限公司 阵列基板、显示面板和显示装置

Also Published As

Publication number Publication date
US10943928B2 (en) 2021-03-09
US20190296049A1 (en) 2019-09-26
CN108389833A (zh) 2018-08-10

Similar Documents

Publication Publication Date Title
US8987068B2 (en) Method for manufacturing display device
CN110400811B (zh) 阵列基板和显示装置
KR101491981B1 (ko) 반도체 장치의 제작 방법
KR101263726B1 (ko) 폴리실리콘을 이용한 박막트랜지스터를 포함하는 어레이 기판 및 이의 제조방법
JPH09311342A (ja) 表示装置
KR20080018839A (ko) 반도체 장치의 제조 방법
US20050253195A1 (en) Semiconductor device and image display device
US7262433B2 (en) Semiconductor device
US7508037B2 (en) Polycrystalline silicon liquid crystal display device and fabrication method thereof
CN108389833B (zh) 显示基板及其制造方法和显示装置
KR20070048912A (ko) 액정표시장치 및 그 제조방법
JP2010073920A (ja) 半導体装置の製造方法
KR20080001110A (ko) 액정표시소자 및 그 제조방법
JP2006209130A (ja) 薄膜トランジスタ表示板、該表示板を有する液晶表示装置及びその製造方法
JP2005311037A (ja) 半導体装置およびその製造方法
US11222983B2 (en) Display substrate, manufacturing method thereof, and display device
JP5405770B2 (ja) 表示装置およびその製造方法
JP2008166597A (ja) 半導体装置の製造方法及び液晶表示装置の製造方法
US20210343878A1 (en) Thin-film transistor and method for manufacturing same
US10541258B2 (en) Patterning layers stacks for electronic devices
US11948947B2 (en) Display device
JP2011066280A (ja) 光マトリックスデバイスの製造方法
JP3949650B2 (ja) アクティブマトリクス型表示装置の作製方法
KR101021715B1 (ko) 스토리지 도핑공정을 개선한 액정표시소자의 제조방법
KR101384048B1 (ko) 유기 광 발생 장치 및 이의 제조 공정

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant