CN108389804A - The sintering method of GaN chips and GaN chips to be sintered - Google Patents
The sintering method of GaN chips and GaN chips to be sintered Download PDFInfo
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- CN108389804A CN108389804A CN201810166863.4A CN201810166863A CN108389804A CN 108389804 A CN108389804 A CN 108389804A CN 201810166863 A CN201810166863 A CN 201810166863A CN 108389804 A CN108389804 A CN 108389804A
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- 238000005245 sintering Methods 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 230000026267 regulation of growth Effects 0.000 claims abstract description 8
- 239000010931 gold Substances 0.000 claims description 125
- 238000009713 electroplating Methods 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention is suitable for technical field of semiconductors, and the sintering method and GaN chips to be sintered, this method for providing a kind of GaN chips include：In one metal of back side growth regulation of GaN chips；Au metal layers are grown on the surface of the first metal layer；Au/Sn alloy-layers are grown on the surface in Au metal layers region corresponding with region to be sintered；It is sintered by Au/Sn sintering process.The present invention can reduce the cavity generated in sintering process, reduce the overall thermal resistance and process costs of device, simplify processing step, improve the consistency of production efficiency and product.
Description
Technical field
The invention belongs to the sintering methods and GaN cores to be sintered of technical field of semiconductors more particularly to a kind of GaN chips
Piece.
Background technology
GaN device is due to high-breakdown-voltage, high power density, high electron mobility, high electronics saturation drift velocity
The advantages that, it all has broad application prospects in the dual-use field such as radar, aerospace, communication, automotive electronics.
GaN device has the characteristics that power density is high, operating voltage is high at work, active area temperature when determining its work
Degree is very high, and junction temperature may be up to 200 DEG C or more, and it is unstable that junction temperature height often results in device performance.Although GaN material is usually grown
In the very high SiC substrate of thermal conductivity, but chip also directly affects core with shell or heat sink sintered interface and solder varieties
Piece radiates, and then influences the junction temperature and device performance of device overall work.
The current high-power common sintering processing of GaN chips is that Au/Sn solders are sintered automatically, and when sintering is first burning shell
It is preheated on knot platform, then manipulator is placed on shell designated position, last manipulator by the Au/Sn weld tabs for needing shape is processed into
GaN tube cores are drawn to be sintered.This sintering processing is due to using weld tabs sintering process, weld tabs and heat sink, shell all to there is sky
Gas, weld tabs melt rear surface out-of-flatness, and when sintering causes voidage high, influences sintering quality.
Invention content
In view of this, an embodiment of the present invention provides a kind of sintering method of GaN chips and GaN chips to be sintered, with
Solve the problems, such as that the sintering method of GaN chips in the prior art causes voidage high.
The first aspect of the embodiment of the present invention provides a kind of sintering method of GaN chips, including：
In one metal of back side growth regulation of GaN chips；
Au metal layers are grown on the surface of the first metal layer；
Au/Sn alloy-layers are grown on the surface in Au metal layers region corresponding with region to be sintered；
The GaN chips after growth Au/Sn alloy-layers are sintered by Au/Sn sintering process.
Optionally, described before one metal of back side growth regulation of GaN chips, the method further includes：
By the GaN chip bondings on carrier, wherein the front of the GaN chips is contacted with the carrier.
Further, described that the GaN chips after growth Au/Sn alloy-layers are sintered by Au/Sn sintering process, it wraps
It includes：
The GaN chips are detached and cut with the carrier；
The GaN chips after cutting are sintered on heat sink carrier using automatic sintering platform, wherein sintering temperature is
315 DEG C to 325 DEG C.
Optionally, one metal of back side growth regulation in GaN chips, including：
By sputtering technology the GaN chips back spatter the first metal layer.
Optionally, described to grow Au metal layers on the surface of the first metal layer, including:
By electroplating technology the first metal layer electroplating surface Au metal layers.
It is optionally, described in the surface of Au metal layers region growing Au/Sn alloy-layers corresponding with region to be sintered,
Including：
By photoetching process in the surface of Au metal layers region overlay photoresist layer corresponding with first area,
In, the first area is the region in addition to the sintering region；
Pass through the electroplating surface Au/Sn alloy-layers of the Au metal layer of the electroplating technology after covering photoresist layer；
Remove the photoresist layer.
Optionally, the first metal layer includes Ti/Au layers, TiW/Au layers or Ti/Ni/Au.
Optionally, the thickness of the first metal layer is 400 nanometers to 600 nanometers；The thickness of the Au metal layers is 3 micro-
Rice is to 5 microns；The thickness of the Au/Sn alloy-layers is 3 microns to 7 microns.
Optionally, the mass fraction of Au is 70% to 80% in the Au/Sn alloy-layers.
The second aspect of the embodiment of the present invention provides a kind of GaN chips to be sintered, including GaN chips, the GaN cores
The back side of piece covers the first metal layer；The surface of the first metal layer covers Au metal layers, the Au metal layers and sintering zone
The surface in the corresponding region in domain covers Au/Sn alloy-layers.
Existing advantageous effect is the embodiment of the present invention compared with prior art：The embodiment of the present invention passes through in GaN chips
The back side grow the first metal layer and Au metal layers successively, Au metal layers region corresponding with region to be sintered surface grow
Au/Sn alloy-layers are sintered finally by Au/Sn sintering process, since Au/Sn alloy-layers are fitted closely with chip, and
The thickness evenness that can ensure Au/Sn alloy-layers, so as to reduce the cavity generated in sintering process.Traditional sintering side
The thickness of formula Au/Sn weld tabs is usually 15 microns to 40 microns, and the thickness of the Au/Sn alloy-layers in the embodiment of the present invention only needs
3 microns to 7 microns are wanted, the overall thermal resistance and process costs of device can be reduced.Sintering method provided in an embodiment of the present invention without
It needs to draw, place the step of Au/Sn weld tabs, processing step can be simplified, improve production efficiency, and avoid different batches Au/
Influence of the difference of Sn weld tabs to sintering quality, can improve the consistency of product.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some
Embodiment for those of ordinary skill in the art without having to pay creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the sintering method implementation process schematic diagram for the GaN chips that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram of the sintering method for the GaN chips that the embodiment of the present invention one provides；
Fig. 3 is the structural schematic diagram of GaN chips to be sintered provided by Embodiment 2 of the present invention.
Specific implementation mode
In being described below, for illustration and not for limitation, it is proposed that such as tool of particular system structure, technology etc
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention can also be realized in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
In order to illustrate technical solutions according to the invention, illustrated below by specific embodiment.
Embodiment one
Referring to FIG. 1, the sintering method of GaN chips includes：
Step S101, in one metal of back side growth regulation of GaN chips.
In embodiments of the present invention, the first metal layer is seed layer, the adhesion layer as conductive layer and Au metal layers.First
Metal layer includes but not limited to Ti/Au layers, TiW/Au layers or Ti/Ni/Au layers.The thickness of the first metal layer is 400 nanometers to 600
Nanometer.Wherein, the front of chip is the preparation face of device, the i.e. picture surface of chip, and the back side of chip is the phase in face where device
Opposite, the i.e. non-graphic face of chip.
Optionally, it please refers to Fig.2 (1), before step S101, the method further includes：The GaN chips 202 are bonded
On carrier 201, wherein the front of the GaN chips 202 is contacted with the carrier 201, i.e. GaN chips 202 in Fig. 2 (1)
Upper surface is the back side.
In embodiments of the present invention, one side carrier 201 plays the role of that GaN chips 202 is supported on the other hand to pass through
The front of GaN chips 202 is contacted with carrier 201,202 positive device of protection GaN chips avoids the front of GaN chips 202
It is stain in subsequent technique.
Optionally, it please refers to Fig.2 (2), the implementation method of step S101 is：By sputtering technology in the GaN chips 202
Back spatter the first metal layer 203.
In embodiments of the present invention, the first metal layer 203 is sputtered by sputtering technology, keeps the back side of GaN chips 202 whole
The first metal layer 203 is covered, sputtering technology can ensure the thickness evenness of the first metal layer 203.
Step S102 grows Au metal layers on the surface of the first metal layer.
Au metal layers can prevent the Au/Sn alloys grown in subsequent technique as separation layer in embodiments of the present invention
Layer corrodes the first metal layer, and can prevent Au/Sn alloy-layers from falling off.The thickness of Au metal layers is 3 microns to 5 microns.
Optionally, it please refers to Fig.2 (3), the concrete methods of realizing of step S102 is：By electroplating technology in first gold medal
Belong to the electroplating surface Au metal layers 204 of layer 203.
In embodiments of the present invention, made in the electroplating surface Au metal layers 204 of the first metal layer 203 by electroplating technology
The surface of the first metal layer 203 all covers Au metal layers 204, and electroplating technology can ensure that the thickness of Au metal layers 204 is uniform
Property.
Step S103 grows Au/Sn alloy-layers on the surface in Au metal layers region corresponding with region to be sintered.
In embodiments of the present invention, Au/Sn alloy-layers are only placed only in Au metal layers region corresponding with region to be sintered
Surface, to carry out subsequent sintering process.The mass fraction of Au is the content mistake of 70% to 80%, Au in Au/Sn alloy-layers
It is more or it is very few can cause Au/Sn alloy-layer fusing points to increase, or even can not melt, therefore, it is necessary to control the content of Au to ensure
Excellent sintering quality.
Optionally, the thickness of Au/Sn alloy-layers is 3 microns to 7 microns.The thickness of Au/Sn alloy-layers is burnt much smaller than tradition
The thickness for tying the Au/Sn weld tabs in technique, so as to reduce the overall thermal resistance and process costs of device.Au/Sn alloy-layers
Precise thickness is determined according to sintering process, is not limited herein.
Optionally, (4) to 2 (6) are please referred to Fig.2, the specific implementation of step S103 is：By photoetching process described
The surface in the region corresponding with first area of Au metal layers 204 covers photoresist layer 205, wherein the first area is except institute
State the region other than sintering region；Pass through the electroplating surface of the Au metal layer 204 of the electroplating technology after covering photoresist layer
Au/Sn alloy-layers 206；Remove the photoresist layer 205.
In embodiments of the present invention, first, by gluing, exposure, development, post bake, in Au metal layers 204 and first area
The surface in corresponding region covers photoresist layer 205, exposes region corresponding with region to be sintered, wherein photoresist layer 205
Thickness is 5 microns to 10 microns.Then, Au/Sn alloy-layers 206 are electroplated by electroplating technology, Au/Sn alloy-layers 206 are covered in
The surface on the surface and photoresist layer 205 of the Au metal layers 204 of exposing.Finally, photoresist layer 205,205 table of photoresist layer are removed
The Au/Sn alloy-layers 206 in face are also removed together, in the surface of Au metal layers 204 region corresponding with region to be sintered
Form Au/Sn alloy-layers.
Step S104 is sintered the GaN chips after growth Au/Sn alloy-layers by Au/Sn sintering process.
Optionally, the specific implementation of step S104 is：
The GaN chips are detached and cut with the carrier；
The GaN chips after cutting are sintered on heat sink carrier using automatic sintering platform, wherein sintering temperature is
315 DEG C to 325 DEG C.
It is sintered 50 GaN chips using the sintering method of GaN chips provided in an embodiment of the present invention, wherein Au/Sn alloys
The thickness of layer is 5 microns.It reuses traditional sintering method and is sintered same 50 GaN chips, wherein the thickness of Au/Sn weld tabs
Degree is 30 microns.Finally, the voidage for the GaN chips being sintered using two methods of X-ray check, traditional uses Au/Sn weld tabs
Sintering method voidage be 4% to 8%, and sintering method voidage provided in an embodiment of the present invention be 3% to 4%.As it can be seen that
The embodiment of the present invention can significantly reduce voidage.
The embodiment of the present invention by growing the first metal layer and Au metal layers successively at the back side of GaN chips, in Au metals
The surface in layer region corresponding with region to be sintered grows Au/Sn alloy-layers, is sintered finally by Au/Sn sintering process,
Since Au/Sn alloy-layers are fitted closely with chip, and it can ensure the thickness evenness of Au/Sn alloy-layers, so as to subtract
The thickness of the empty traditional sintering processing Au/Sn weld tabs generated in few sintering process is usually 15 microns to 40 microns, and this
The thickness of Au/Sn alloy-layers in inventive embodiments only needs 3 microns to 7 microns, can reduce the overall thermal resistance and work of device
Skill cost.Sintering method provided in an embodiment of the present invention can simplify technique step without drawing, placing the step of Au/Sn weld tabs
Suddenly, production efficiency is improved, and avoids influence of the difference of different batches Au/Sn weld tabs to sintering quality, product can be improved
Consistency.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
Embodiment two
Referring to FIG. 3, GaN chips to be sintered include GaN chips 202, the back side covering first of the GaN chips 202
Metal layer 203；The surface covering Au metal layers 204 of the first metal layer 203, the Au metal layers 204 and sintering region pair
The surface covering Au/Sn alloy-layers 206 in the region answered.
GaN chips to be sintered provided in an embodiment of the present invention by covering the first gold medal successively at the back side of GaN chips 202
Belong to layer 203 and Au metal layers 204, grows Au/Sn alloy-layers on the surface in the region corresponding with region to be sintered of Au metal layers 204
206, it is sintered finally by Au/Sn sintering process, since Au/Sn alloy-layers 206 are fitted closely with chip, and can protect
The thickness evenness for demonstrate,proving Au/Sn alloy-layers 206, so as to reduce the cavity generated in sintering process.Traditional sintering processing
The thickness of Au/Sn weld tabs is usually 15 microns to 40 microns, and the thickness of the Au/Sn alloy-layers 206 in the embodiment of the present invention is only
3 microns to 7 microns are needed, the overall thermal resistance and process costs of device can be reduced.It waits burning using provided in an embodiment of the present invention
The GaN chips of knot can be directly sintered, and without drawing, placing the step of Au/Sn weld tabs, can be simplified processing step, be carried
High efficiency, and influence of the difference of different batches Au/Sn weld tabs to sintering quality is avoided, the consistent of product can be improved
Property.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although with reference to aforementioned reality
Applying example, invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to aforementioned each
Technical solution recorded in embodiment is modified or equivalent replacement of some of the technical features；And these are changed
Or replace, the spirit and scope for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution should all
It is included within protection scope of the present invention.
Claims (10)
1. a kind of sintering method of GaN chips, which is characterized in that including：
In one metal of back side growth regulation of GaN chips；
Au metal layers are grown on the surface of the first metal layer；
Au/Sn alloy-layers are grown on the surface in Au metal layers region corresponding with region to be sintered；
The GaN chips after growth Au/Sn alloy-layers are sintered by Au/Sn sintering process.
2. the sintering method of GaN chips as described in claim 1, which is characterized in that the back side growth regulation in GaN chips
Before one metal, the method further includes：
By the GaN chip bondings on carrier, wherein the front of the GaN chips is contacted with the carrier.
3. the sintering method of GaN chips as claimed in claim 2, which is characterized in that it is described by Au/Sn sintering process to life
GaN chips after long Au/Sn alloy-layers are sintered, including：
The GaN chips are detached and cut with the carrier；
The GaN chips after cutting are sintered on heat sink carrier using automatic sintering platform, wherein sintering temperature is 315 DEG C
To 325 DEG C.
4. the sintering method of GaN chips as described in claim 1, which is characterized in that the back side growth regulation in GaN chips
One metal, including：
By sputtering technology the GaN chips back spatter the first metal layer.
5. the sintering method of GaN chips as described in claim 1, which is characterized in that the table in the first metal layer
It looks unfamiliar long Au metal layers, including:
By electroplating technology the first metal layer electroplating surface Au metal layers.
6. the sintering method of GaN chips as described in claim 1, which is characterized in that described on the surface of the Au metal layers
Region growing Au/Sn alloy-layers corresponding with region to be sintered, including：
By photoetching process in the surface of Au metal layers region overlay photoresist layer corresponding with first area, wherein institute
It is the region in addition to the sintering region to state first area；
Pass through the electroplating surface Au/Sn alloy-layers of the Au metal layer of the electroplating technology after covering photoresist layer；
Remove the photoresist layer.
7. the sintering method of GaN chips as described in claim 1, which is characterized in that the first metal layer be Ti/Au layers,
TiW/Au layers or Ti/Ni/Au layers.
8. the sintering method of GaN chips as described in claim 1, which is characterized in that the thickness of the first metal layer is 400
Nanometer is to 600 nanometers；The thickness of the Au metal layers is 3 microns to 5 microns；The thickness of the Au/Sn alloy-layers be 3 microns extremely
7 microns.
9. such as the sintering method of claim 1 to 8 any one of them GaN chips, which is characterized in that the Au/Sn alloy-layers
The mass fraction of middle Au is 70% to 80%.
10. a kind of GaN chips to be sintered, including GaN chips, which is characterized in that the back side of the GaN chips covers the first gold medal
Belong to layer；The surface of the first metal layer covers Au metal layers, the surface in Au metal layers region corresponding with sintering region
Cover Au/Sn alloy-layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810166863.4A CN108389804A (en) | 2018-02-28 | 2018-02-28 | The sintering method of GaN chips and GaN chips to be sintered |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810166863.4A CN108389804A (en) | 2018-02-28 | 2018-02-28 | The sintering method of GaN chips and GaN chips to be sintered |
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| CN108389804A true CN108389804A (en) | 2018-08-10 |
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ID=63069452
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| CN201810166863.4A Pending CN108389804A (en) | 2018-02-28 | 2018-02-28 | The sintering method of GaN chips and GaN chips to be sintered |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623356A (en) * | 2011-12-31 | 2012-08-01 | 广东风华高新科技股份有限公司 | Preparation method of chip-scale weldable ceramic heat sink |
| CN103227161A (en) * | 2013-05-15 | 2013-07-31 | 中国电子科技集团公司第四十三研究所 | Welding substrate for electronic product and manufacturing method of welding substrate |
| CN104078369A (en) * | 2014-06-11 | 2014-10-01 | 昆山华太电子技术有限公司 | Low-cost high-power electronic device packaging technology |
| CN205542755U (en) * | 2015-12-11 | 2016-08-31 | 福建安特微电子有限公司 | Highly reliable power device eutectic silicon back metallization structure |
| CN107104060A (en) * | 2016-02-22 | 2017-08-29 | 映瑞光电科技(上海)有限公司 | Golden tin bonding method for patterned surface |
| CN107195606A (en) * | 2017-06-26 | 2017-09-22 | 昆山昊盛泰纳米科技有限公司 | A kind of silicon chip back side metallized film and preparation method thereof |
-
2018
- 2018-02-28 CN CN201810166863.4A patent/CN108389804A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623356A (en) * | 2011-12-31 | 2012-08-01 | 广东风华高新科技股份有限公司 | Preparation method of chip-scale weldable ceramic heat sink |
| CN103227161A (en) * | 2013-05-15 | 2013-07-31 | 中国电子科技集团公司第四十三研究所 | Welding substrate for electronic product and manufacturing method of welding substrate |
| CN104078369A (en) * | 2014-06-11 | 2014-10-01 | 昆山华太电子技术有限公司 | Low-cost high-power electronic device packaging technology |
| CN205542755U (en) * | 2015-12-11 | 2016-08-31 | 福建安特微电子有限公司 | Highly reliable power device eutectic silicon back metallization structure |
| CN107104060A (en) * | 2016-02-22 | 2017-08-29 | 映瑞光电科技(上海)有限公司 | Golden tin bonding method for patterned surface |
| CN107195606A (en) * | 2017-06-26 | 2017-09-22 | 昆山昊盛泰纳米科技有限公司 | A kind of silicon chip back side metallized film and preparation method thereof |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180810 |