CN102931107B - Method for slowing down growth of intermetallic compound - Google Patents

Method for slowing down growth of intermetallic compound Download PDF

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Publication number
CN102931107B
CN102931107B CN201210061784.XA CN201210061784A CN102931107B CN 102931107 B CN102931107 B CN 102931107B CN 201210061784 A CN201210061784 A CN 201210061784A CN 102931107 B CN102931107 B CN 102931107B
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solder
intermetallic compound
metal
thin
copper
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CN102931107A (en
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陈智
杜经宁
萧翔耀
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Spring Foundation of NCTU
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Spring Foundation of NCTU
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
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    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
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Abstract

The invention relates to a method for slowing down growth of intermetallic compounds. The method comprises the following steps: (i) preparing a substrate element, including electroplating at least one metal pad layer on a substrate, then electroplating at least one thin solder on the metal pad layer, and performing appropriate heat treatment process; (ii) plating solder with proper thickness on the substrate element; after proper heat treatment, the thin solder reacts with the metal of the metal pad to form a thin intermetallic compound, so that the formation rate of the intermetallic compound can be inhibited in the subsequent reflow process, thereby slowing down the reaction of the micro-joint solder and the metal on the metal pad to form the intermetallic compound. Once the growth rate of intermetallic compounds can be slowed down, the growth of tin whisker (Sn.

Description

For slowing down the method that intermetallic compound is grown up
Technical field
The invention relates to a kind of for slowing down the method that intermetallic compound is grown up, a kind of particularly method forming intermetallic compound for slowing down scolding tin and metal pedestal layer.In addition, the present invention also has the structure about a kind of chip bonding.
Background technology
The development trend of semiconductor technology and encapsulation is that density is more and more higher, and contact (interconnects) is more and more less, and the size (diameter) covering brilliant solder joints is at present about 100 microns (μm).Existingly covering brilliant solder joints, with reference to Fig. 1, Fig. 2 A, Fig. 2 B, is copper (Cu) metal pedestal layer (12) plating a thickness 5 microns at a silicon (Si) plate (11); Nickel (Ni) metal level (13) of a thickness 3 microns is plated afterwards at this copper metal pedestal layer (12); And the scolding tin (14) of thickness about 70 to 100 microns is plated at this nickel metal layer, form the semiconductor chip components (1) that contains micro-solder joints; Then carry out covering crystalline substance (Flip-Chip) program, by this element (1) with silicon plate (21) is coated with copper metal pedestal layer (22), the element (2) of nickel metal layer (23) engages.Usually for very little contact, such as, micro-solder joints (microbumps) (with reference to Fig. 2 B) in 3DIC, the gross thickness (bumpheight) of contact is about 20 microns, and solder thickness only has approximate number micron to 10 micron, the copper of upper and lower side or nickel metal pedestal layer (under-bump-metallization, UBM) gross thickness respectively about 8 microns.When contact technique complete or through 10 reflows test after, or in use for some time, solder joints all will convert the intermetallic compound contact of such as Cu-Sn, Ni-Sn or Cu-Ni-Sn and so on to, find that this kind of intermetallic properties is more crisp, therefore the engineering properties of solder joints can be had a strong impact on, if such as element is for portable product, after dropping or striking, contact likely can rupture.In recent years, the settling mode improving the problems referred to above plates one deck nickel again as diffusion trapping layer at micro-solder joints (microbumps), but the cost of this mode is higher, and due to the stress of nickel comparatively large, the engineering properties of docking point also has negative impact.
Scolding tin is the most frequently used solder of encapsulation field, early stage encapsulation practitioner be with eutectic tin lead welding tin and copper or nickel metal in the molten state (such as temperature about 220 DEG C) engage.But eutectic tin lead welding tin can react with copper, and generate as Cu 3sn and/or Cu 6sn 5and so on intermetallic compound.Due to lead-containing materials hostile environment, therefore along with the attention of environmental consciousness, this type of eutectic lead welding tin material has been prohibited to be used as the solder of flip chip contact, and then replaces with Pb-free solder.
The comparatively normal Pb-free solder used, such as tin silver, SAC etc. at present, their fusing point, usually than the fusing point height about 50 DEG C of existing eutectic tin lead welding tin, that is, uses Pb-free solder to need to engage to the higher temperature of 260 DEG C at about 250 DEG C.But the reaction of most Pb-free solder and copper nickel is faster, can form thicker such as Cu-Sn compound.Although the engineering properties of scolding tin itself is better, the stress of total body can be absorbed, but react the engineering properties poor (such as more crisp) of the Cu-Sn compound produced, therefore, if form thicker Cu-Sn compound, when total body is subject to stress, easily destroy total body from the brittle failure of Cu-Sn compound.
The reaction of copper and tin is very fast, and even at room temperature will react, prior art does not have way and slows down or control as Cu 6sn 5and so on the formation of intermetallic compound.Generally, at larger-size solder joints, as covered brilliant solder joints, generate intermetallic compound and can form contact, the engineering properties of contact can't be affected, but for very little contact, such as, micro-solder joints (microbumps) in 3DIC technique, scolding tin volume is only about one of percentage covering brilliant solder joints, when contact technique completes or after repeatedly (such as 10 times) reflow test, or in use for some time, solder joints all will convert Cu-Sn intermetallic compound contact to, because this intermetallic properties is more crisp, therefore the engineering properties of contact can be badly influenced.
Current settling mode, usually plate one deck nickel again as diffusion trapping layer at micro-solder joints, but the cost of this mode is higher, and due to the stress of nickel comparatively large, the engineering properties of docking point has negative impact.
Another kind of prior art, the method cosputtering copper and the nickel that utilize sputtering (sputtering), but this method does not have way plates thick film, cost is higher, in addition, because Pb-free solder is more a lot of soon than leaded scolding tin with the reaction rate of copper and nickel, this method also cannot be applicable to Pb-free solder.
In prior art, as US Patent No. 6,716,738B2 (date of declaration: on April 6th, 2004) open [being covered the method (MethodoffabricatingmultilayeredUBMforflipchipinterconnec tionsbyelectroplating) of the multilayer UBM of crystalline phase mutual connection by plating manufacture], this patent electroplates by adjustment the metal level obtained, become Cu-Ni metal level to control the stress of metal level and the composition of metal level that plate, it utilizes nickel as reaction trapping layer, reacts to slow down copper, nickel and scolding tin the compound thickness formed.This shortcoming of trapping layer that utilizes is simultaneously copper facing and nickel metal layer, complex process and composition is wayward, and the stress of metal level is also not easy to control, and therefore stability is bad, can affect conforming product rate, and in addition, copper also can with scolding tin reaction.
US Patent No. 6,602,777 (date of declaration: on August 5th, 2003) open [method (Methodforcontrollingtheformationofintermetalliccompoundi nsolderjoints) that the intermetallic compound controlling solder joints is formed], this patent controls intermetallic compound (intermetalliccompound) kind that scolding tin and nickel metal layer formed, such as (Cu by the copper concentration in adjustment scolding tin 1-xni x) 6sn 5, or (Ni 1-ycu y) 3sn 4.But this method can not control the thickness of the intermetallic compound that copper and scolding tin generate.
Taiwan patent I338344 (date of declaration: on March 1st, 2011) open [there is solder projection with the semiconductor chip suppressing intermetallic compound and grow up and manufacture method thereof], this patent utilizes the penetrated bed material infiltrating solder projection, change the solder projection that solder projection becomes many compositions, with the growth of Inhibitor.This section of patent changes solder compositions to suppress the growth of intermetallic compound (IMC), but be but very limited to the reaction suppressing Cu-Sn compound.
In addition, in prior art, open source literature is also had, [by reacting with Sn (Cu) scolding tin of band copper the Ni slowed down on Ni (P) substrate 3p crystal layer is grown up] (" RetardinggrowthofNi3PcrystallinelayerinNi (P) substratebyreactingwithCu-bearingSn (Cu) solders); S.J.Wang; C.Y.Liu; ScriptaMaterialia49 (2003) 813-818); this document is the reaction being controlled this scolding tin and nickel by the copper concentration in adjustment Sn-Cu scolding tin, to suppress Ni 3the generation of P phase, but it also cannot suppress the growth of Cu-Sn or Ni-Sn compound.
For avoiding problem and the shortcoming of above-mentioned prior art, the present inventor proposes to utilize the thickness controlling the intermetallic compound forming scolding tin and copper, that is, scolding tin and copper first can react rapidly before splicing and produce intermetallic compound (as Sn-Cu compound), and after engaging, make the growth of the thickness of this intermetallic compound slow down.
Summary of the invention
An object of the present invention is to provide a kind of for slowing down the method that intermetallic compound is grown up, and comprises step:
I () prepares a substrate components, comprising:
(i-1) on a substrate, a few metal pedestal layer is electroplated to,
(i-2) on this metal pedestal layer, be electroplated to a few thin solder, then heat-treat technique, with an obtained substrate components; This heat treatment can be liquid under reflow process or solid-state aging technique plates the scolding tin of a suitable thickness again on this substrate components; And
(ii) this element and other element are made subsequent joining process.
The present invention is particularly suitable for slowing down the formation of the intermetallic compound of scolding tin and copper metal pedestal layer in encapsulation, as above-mentioned method of the present invention, before carrying out chip join, metal pedestal layer on substrate first plates the very thin thin solder of one deck, through Technology for Heating Processing, this thin solder can react in advance with the metal of metal pedestal layer, thus changes form and the kind of generated intermetallic compound.Then carry out follow-up covering brilliant butt-joint process, because this very thin thin solder generates a very thin intermetallic compound with the metal of metal pedestal layer before joint, the effect of the generating rate of the intermetallic compound suppressing this contact (or projection) can be produced upon engagement.
According to method of the present invention, with reference to Fig. 3, a substrate is electroplated a metal pedestal layer (step, S201), then on this metal pedestal layer, a thin solder (step is electroplated, S301), then carry out high-temperature heat treatment process, obtain a substrate components, wherein, this thin solder, after high-temperature heat treatment, can react the thin intermetallic compound of formation one (step, S401) with the metal of metal pedestal layer.Plate the scolding tin (step, S501) of suitable thickness afterwards again, the substrate components obtained by step S101,201,301,401,501 can be made subsequent joining process (step, S600).
In method of the present invention, the intermetallic compound that the metal reaction of this thin solder and metal pedestal layer is formed all has the function of isolation, the metallic atom that can reduce metal pedestal layer is through the passage of intermetallic compound and solder reaction, allow the metal of metal pedestal layer and solder projection isolate, effectively can suppress the growth of the intermetallic compound of joining zone according to this.When semiconductor element (such as semiconductor chip) carries out chip bonding technique, owing to can first form an intermetallic compound between the metal pedestal layer on substrate and solder, the metallic atom that can reduce upon engagement in metal pedestal layer infiltrates solder joint, therefore, after carrying out reflow or repeatedly reflow program again after joint, have the effect of the intermetallic compound formation reducing solder joint, on the other hand, the metallic atom consumption of metal pedestal layer also can reduce.
Another object of the present invention is to the structure that a kind of chip bonding or scolding tin interface are provided, comprising:
(A) substrate components, contains:
(A-1) substrate,
(A-2) at least one metal pedestal layer, this metal pedestal layer is that plating is formed on this substrate,
(A-3) at least one thin solder, this thin solder is plated on this metal pedestal layer;
(A-4) soldering-tin layer of a suitable thickness is plated again at this substrate components;
Wherein, (A) substrate components can present chip bonding with other substrate components, through reflow program, obtain the structure of a chip bonding, it is characterized in that this thin solder described forms continuous stratiform or the thin intermetallic compound close to pantostrat before splicing with the metal of metal pedestal layer.
In structure of the present invention, formed one thin intermetallic compound has the metal of isolating metal bed course and the function of solder joint (or projection), therefore effectively can suppress the growth of the intermetallic compound of joining zone.
In the present invention, the method for plated metal bed course or solder is not particularly limited, can existing electroplating technology in technical field for this reason, such as: electro-coppering can use copper-bath; Electrotinning silver soldering tin can use Sn 2p 2o 7and the solution of AgI.
In the present invention, the substrate of use is not particularly limited, and according to a specific embodiment of the present invention, this substrate can be semiconductor chip, silicon, macromolecule or glass.
In the present invention, the metal material of the metal pedestal layer of use is not particularly limited, and according to a specific embodiment of the present invention, this metal material can be copper, nickel, gold or its alloy, is preferably copper.The thickness range of metal pedestal layer of the present invention is approximate number micron to 100 micron.
In the present invention, the solder of use is not particularly limited, and according to a specific embodiment of the present invention, this solder can be lead-free solder, is preferably Pb-free solder.
According to a specific embodiment of the present invention, described thin solder thickness is no more than 4 microns, is preferably 2 microns.In the present invention, after joint, the gross thickness of solder joint is no more than 100 microns, is preferably 20 microns.
Of the present invention for slowing down the method that intermetallic compound is grown up, be especially applicable to being applied to the products such as 3DIC industrial field (such as 3DIC encapsulation technology), central processing unit (CPU), mobile phone, image processing chip, DRAM (Dynamic Random Access Memory) (DRAM).
Below will describe in more detail the present invention, the specific embodiment proposed and accompanying drawing are for further illustrating the present invention, and are not used in restriction technical scope of the present invention.
Accompanying drawing explanation
Fig. 1 describes the existing schematic diagram covering brilliant solder joints.
Fig. 2 A describes the existing scanning electron microscope image (cross-sectionalscanningelectronmicroscope (SEM) image) covering brilliant solder joints section.
Fig. 2 B describes existing 20 microns of scanning electron microscope images covering brilliant micro-solder joints section.
Fig. 3 describes according to method flow diagram of the present invention.
Fig. 4 A describes according to method of the present invention, and substrate components is coated with the specific embodiment schematic diagram of a thin solder.
Fig. 4 B describes according to method of the present invention, and substrate components is coated with the specific embodiment schematic diagram of a solder.
Fig. 5 A is according to method of the present invention, the electron microscope cross-sectional view after the copper pad of 5 micron thickness plates 2 microns of solders.
Fig. 5 B is according to method of the present invention, after the copper pad of 5 micron thickness plates 2 microns of solders and through the electron microscope cross-sectional view of 260 DEG C of reflows after 10 minutes.
Fig. 6 A describes according to method of the present invention, and " 2-μm of-SnAg test piece " 260 DEG C of reflows after 10 minutes, then plates 20 microns of solders, then at the electron microscope cross-sectional view of 260 DEG C of reflows after 1 minute.
Fig. 6 B describes according to method of the present invention, and " 2-μm of-SnAg test piece " 260 DEG C of reflows after 10 minutes, then plates 20 microns of solders, then at the electron microscope cross-sectional view of 260 DEG C of reflows after 5 minutes.
Fig. 6 C describes according to method of the present invention, and " 2-μm of-SnAg test piece " 260 DEG C of reflows after 10 minutes, then plates 20 microns of solders, then at the electron microscope cross-sectional view of 260 DEG C of reflows after 10 minutes.
Fig. 7 A is that " 19-μm of-SnAg test piece " is at the electron microscope cross-sectional view of 260 DEG C of reflows after 1 minute.
Fig. 7 B is that " 19-μm of-SnAg test piece " is at the electron microscope cross-sectional view of 260 DEG C of reflows after 5 minutes.
Fig. 7 C is that " 19-μm of-SnAg test piece " is at the electron microscope cross-sectional view of 260 DEG C of reflows after 10 minutes.
Fig. 8 is the thickness of the interface Cu-Sn compound measured, at 260 DEG C, and the variation diagram increased along with the reflow time.
[main element symbol description]
31 first substrates;
32 first bronze medal metal pedestal layer;
33 lead-free solders;
41 second substrates;
42 second bronze medal metal pedestal layer;
43 lead-free solders;
IMC intermetallic compound.
Embodiment
For making object of the present invention, technical scheme and beneficial effect clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
First, the test piece " test piece of 2-μm of-SnAg/ copper packing layer " that is electroplate with thin solder is prepared.
Preparation is electroplate with the test piece " 2-μm of-SnAg test piece " of the first thin thin solder, with the test piece " 19-μm of-SnAg test piece " being electroplate with the second solder.
With reference to Fig. 4 A, preparation one is electroplate with the test piece " 2-μm of-SnAg test piece " of the first thin thin solder.
First, prepare a silicon as one first substrate (31), it is electroplate with a thickness 5 microns the first bronze medal metal pedestal layer (CuUBM) (321,322,32n, be called herein below " 32 "); Then, this the first bronze medal metal pedestal layer (32) upper plating a layer thickness 2 microns SnAg lead-free solder (331,332,33n, below be called herein " 33 "), reflow (reflowing) is carried out at 260 DEG C of temperature, last about 10 minutes, this lead-free solder is after 260 DEG C of reflows and cooling, can with copper metal reaction and form a first very thin thin Cu-Sn intermetallic compound (Cu-SnIMC) (sign), obtain according to this " 2-μm of-SnAg test piece ".
With reference to Fig. 4 B, preparation one is electroplate with the test piece " 19-μm of-SnAg test piece " of the second solder.
Prepare another silicon as one second substrate (41), the second bronze medal metal pedestal layer (CuUBM) (421,422,423, be called herein below " 42 ") of another thickness 20 microns in this second substrate (41) plating; Then, upper plating one thickness 19 microns of this second bronze medal metal pedestal layer (42) SnAg lead-free solder (431,432,43n, below " 43 " are claimed herein), reflow (reflowing) is carried out at 260 DEG C of temperature, last about 1-10 minute, this lead-free solder, after 260 DEG C of reflows and cooling, can be formed thicker Cu-Sn intermetallic compound (Cu-SnIMC) (sign), obtain according to this " 19-μm of-SnAg test piece ".
In above-mentioned technique, plated first solder (33) of very thin solder before carrying out follow-up splice program, first can form thin Cu-Sn intermetallic compound with the copper metal reaction of copper metal pedestal layer, this Cu-Sn intermetallic compound can reduce the passage that copper atom reacts through Cu-Sn intermetallic compound and lead-free solder, allows the first bronze medal metal pedestal layer (32) and solder joint (or projection) isolate.
In the present embodiment, utilize scanning electron microscopy (SEM) to detect the cross-sectional view of this structure, allow this structure carry out reflow program again at 260 DEG C of temperature, last 5 minutes and 10 minutes, to carry out the test of solder joint.
With reference to Fig. 5 A, 5B, test piece be " 2-μm of-SnAg test piece ", Fig. 5 A be just preparation afterwards and Fig. 5 B be the cross-sectional view of the scanning electron microscopy of reflow after 10 minutes.Can clear view arrive, when reflow is after 10 minutes, the Pb-free solder of top almost total overall reaction becomes Cu-Sn intermetallic compound.And its structure presents layer structure.Namely this layer structure Cu-Sn intermetallic compound is used to slow down the trapping layer that copper is diffused into solder in following joint technology.
With reference to Fig. 6 A, 6B, 6C, test piece is in " 2-μm of-SnAg test piece " reflow after 10 minutes, then plates the solder of thick about 20 microns, then the cross-sectional view of the scanning electron microscopy of reflow after 1,5 and 10 minutes.Even if can find out that reflow is after 10 minutes, Cu-Sn intermetallic compound still almost maintains layer structure.Therefore, the passage between Cu-Sn intermetallic compound tails off, and therefore copper atom will diffuse into reaction in scolding tin and become more difficult.
On the other hand, test result shows, if do not use the method, Cu-Sn intermetallic compound can be grown up comparatively fast.With reference to Fig. 7 A, 7B, 7C, this test piece is the cross-sectional view in the scanning electron microscopy of " 19-μm of-SnAg test piece " reflow after 1,5 and 10 minutes.Can find out that the situation that Cu-Sn intermetallic compound can obviously thicken along with the increase of reflow time produces.And pattern presents semicircular in shape, therefore the passage of copper atom easily in the middle of Cu-Sn intermetallic compound diffuses in scolding tin and reacts.So Cu-Sn intermetallic compound can obviously increase along with the time and thicken.
With reference to Fig. 8, the relation that the Cu-Sn intermetallic compound thickness that this figure display measurement arrives increased along with the reflow time.The Cu-Sn intermetallic compound that can be observed through holding through reflow " the 2-μm of-SnAg test piece " of 10 minutes in advance has situation about thickening significantly to produce compared with increasing along with the time, when reflow is after 10 minutes, observes the increase only about 0.2 micron of thickness; But " 19-μm of-SnAg test piece " reflow is after 10 minutes, Cu-Sn intermetallic compound increase about 1.6 microns.Therefore susceptible of proof, according to method of the present invention, before joint, first plate a thin solder at metal gasket, really can reach the effect suppressing Cu-Sn intermetallic compound thickness to be grown up, copper metal pedestal layer and solder projection are isolated simultaneously, also allow the consumption thickness of copper metal layer reduce significantly.
In addition, for of the present invention for slowing down the method that intermetallic compound is grown up, the mechanism that it can reach the effect suppressing Cu-Sn intermetallic compound to thicken is inquired into, mainly owing to following factors:
(1) when before joint, not when metal pedestal layer first plates a very thin solder, Cu-Sn intermetallic compound (the such as Cu of generation 6sn 5compound) be the shape of similar dome-type.The shape of the Cu-Sn compound that " 19-μm of-SnAg test piece " holds after 1 minute of reflow as shown in Figure 7 A, should " 19-μm of-SnAg test piece " be utilized etching solution, etch away remaining solder, can be observed the Cu-Sn intermetallic compound shape generated, at dome-type Cu 6sn 5between have many passages (channels), beneath copper can be allowed to continue to be diffused into scolding tin internal-response.
In addition, when before joint, when metal pedestal layer first plates a very thin solder, as above-mentioned method of the present invention, observe " 2-μm of-SnAg test piece ", after the reflow process of 10 minutes, the Cu of generation 6sn 5or Cu 3sn compound is class quasi-lamellar structure, and does not almost have passage, this is because scolding tin only has 2 micron thickness, after the reflow process of 10 minutes, scolding tin almost all runs out of, Cu 6sn 5between passage also just close.Therefore, when " 2-μm of-SnAg test piece " plates solder again, just clearly suppressed in the Cu-Sn reaction of " 2-μm of-SnAg test piece ".
(2) because the scolding tin plated is very thin, such as only have 2 micron thickness, after the reflow process of 10 minutes, scolding tin almost all runs out of, Cu 6sn 5compound also may all or part of Cu being transformed into layer structure 3sn compound, the copper of below will be diffused into reaction in scolding tin and comparatively be not easy, and therefore Cu-Sn reaction is just clearly suppressed.According to this, Cu-Sn compound thickness can be suppressed to thicken.
By above-mentioned specific embodiment susceptible of proof, the growth of intermetallic compound thickness really effectively can be slowed down according to method of the present invention.Once intermetallic compound growth rate can be slowed down, the growth of tin content (Snwhisker) also can be suppressed.Therefore the present invention also can be applied to the growth suppressing tin content.
The present invention can when not departing from category of the present invention, realize in a variety of forms, above-described embodiment is only citing for convenience of description, be understood that the interest field that (unless otherwise) the present invention advocates should be as the criterion with described in claim certainly, but not be only limitted to above-described embodiment.

Claims (4)

1., for slowing down the method that intermetallic compound is grown up, it is characterized in that, comprise step:
I () prepares a substrate components, comprising:
(i-1) on a substrate, a few metal pedestal layer is electroplated to,
(i-2) on this metal pedestal layer, be electroplated to a few thin solder, then heat-treat technique, with an obtained substrate components; Plate the scolding tin of suitable thickness again; And
This element and another element are made subsequent joining process by (II),
Wherein, this thin solder is a Pb-free solder, and it is after high-temperature heat treatment, before covering brilliant docking, forms a thin intermetallic compound with the metal reaction of metal pedestal layer.
2. method according to claim 1, is characterized in that, this substrate is semiconductor chip.
3. method according to claim 1, is characterized in that, the metal of this metal pedestal layer is copper.
4. method according to claim 1, is characterized in that, the thickness of this thin solder is no more than 4 microns.
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