CN107195606A - A kind of silicon chip back side metallized film and preparation method thereof - Google Patents
A kind of silicon chip back side metallized film and preparation method thereof Download PDFInfo
- Publication number
- CN107195606A CN107195606A CN201710491088.5A CN201710491088A CN107195606A CN 107195606 A CN107195606 A CN 107195606A CN 201710491088 A CN201710491088 A CN 201710491088A CN 107195606 A CN107195606 A CN 107195606A
- Authority
- CN
- China
- Prior art keywords
- silicon chip
- silicon
- back side
- metal levels
- eutectic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 67
- 239000010703 silicon Substances 0.000 title claims abstract description 67
- 239000011104 metalized film Substances 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 230000005496 eutectics Effects 0.000 claims abstract description 34
- 238000001465 metallisation Methods 0.000 claims abstract description 13
- 239000000203 mixture Substances 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910015363 Au—Sn Inorganic materials 0.000 claims description 24
- 229910045601 alloy Inorganic materials 0.000 claims description 19
- 239000000956 alloy Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000010408 film Substances 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 239000006023 eutectic alloy Substances 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 3
- 231100000252 nontoxic Toxicity 0.000 abstract description 2
- 230000003000 nontoxic effect Effects 0.000 abstract description 2
- 229910001128 Sn alloy Inorganic materials 0.000 abstract 2
- 239000010931 gold Substances 0.000 description 14
- 210000002381 plasma Anatomy 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011257 shell material Substances 0.000 description 3
- 229910015365 Au—Si Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910018731 Sn—Au Inorganic materials 0.000 description 1
- VJRVSSUCOHZSHP-UHFFFAOYSA-N [As].[Au] Chemical compound [As].[Au] VJRVSSUCOHZSHP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 210000001787 dendrite Anatomy 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000008014 freezing Effects 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4835—Cleaning, e.g. removing of solder
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physical Vapour Deposition (AREA)
Abstract
The invention discloses a kind of silicon chip back side metallized film composition and preparation method thereof, wherein silicon chip back side metallization eutectic structure, including the Ti metal levels being arranged on silicon chip, the Ta metal levels being arranged on Ti metal levels and the Au Sn alloy eutectic metal levels that are arranged on Ta metal levels.The present invention replaces the pure Au of individual layer to be used as the coat of metal of silicon chip back side by multiple layer metal, and good Ohmic contact can be formed with silicon chip；Eutectic alloy is used as by magnetron sputtering Au Sn alloy firms simultaneously, has the advantages that nontoxic, cost is low.
Description
Technical field
The present invention relates to silicon chip back side metallized film and its manufacturing process, more particularly to a kind of silicon chip back side metallization is thin
Film and preparation method thereof.
Background technology
Eutectic welding technology is used widely in Electronic Packaging industry, as chip is bonding with substrate, substrate and shell
Bonding, shell sealing cap etc..Compared with traditional epoxy conductive glue sticking, eutectic welding is with thermal conductivity is high, resistance is small, heat transfer
Hurry up, the big advantage of shearing force after highly reliable, bonding, it is adaptable to high frequency, high power device chips and substrate, substrate and shell
Interconnection.For there is the power device of higher cooling requirements must be using eutectic welding.Eutectic weldering make use of eutectic alloy
Characteristic completes welding procedure.
Eutectic alloy has following characteristic:(I) it is lower than pure constituent element fusing point, simplify melting process；(2) eutectic alloy is than pure
Metal has more preferable mobility, can prevent from hindering the dendrite of liquid flowing to be formed in solidification, so as to improve casting character；
(3) isothermal transformation (no solidification temperature range) reduces casting flaw, such as segregation and shrinkage cavity；(4) eutectic freezing can obtain a variety of
The microscopic structure of form, especially regularly arranged stratiform or shaft-like eutectic structure can turn into the In-situ reaction material of excellent properties
Material.
Eutectic refers to that the phenomenon of eutectic thing fusion occurs for eutectic solder at relatively low temperature, eutectic alloy directly from
Solid-state changes to liquid, and without the plastic stage.Its fusion temperature claims eutectic temperature.
Usually used back face metalization eutectic technology is used as metal plating layer on back with proof gold, by annealing process come real
The eutectic alloy of existing back metal.Proof gold price is again extremely expensive, and reliability is not high, although have patent using evaporation Ti/Ni/
The technology of Au-Sn alloys, but be due to that adhesive force is low and can not stop the diffusion of Au-Sn and silicon very well, so not being very
Desirable process program.
The content of the invention
In order to overcome drawbacks described above, the invention provides a kind of silicon chip back side metallized film and preparation method thereof.
The technical scheme that is used to solve its technical problem of the present invention is：A kind of silicon chip back side metallized film and its
Preparation method, including the metallization eutectic structure of silicon chip back side is arranged on, the metallization eutectic structure is by being arranged on silicon chip
Ti metal levels, the Ta metal levels being arranged on Ti metal levels and the Au-Sn alloy eutectic metals being arranged on Ta metal levels
Layer composition.
As a further improvement on the present invention, in addition to be arranged on Au-Sn alloy eutectics metal level (4) on Au metal levels
(5)。
A kind of preparation method of silicon chip back side metallized film, it is characterised in that：Comprise the following steps:
1. will be thinned after silicon chip be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon chip
Cleaned；
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Penetrate Ti, Ta, Au-Sn and Au film.
As a further improvement on the present invention, the method for silicon corrosion and silicon dioxide etching is specially in the step:Make
With passing through 1:20 HF erodes the silicon dioxide layer of presence；Finally bath is dried.
A kind of preparation method of silicon chip back side metallized film, it is characterised in that：Comprise the following steps:
1. will be thinned after silicon chip be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon chip
Cleaned；
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Penetrate Ti, Ta, Au-Sn and Au film.
The beneficial effects of the invention are as follows：The present invention replaces the gold-arsenic alloy or proof gold of individual layer to be used as by multiple layer metal
The coat of metal of silicon chip back side, can form good Ohmic contact with silicon chip；Eutectic is produced by the evaporation of Sn-Au alloys simultaneously
Alloy, has the advantages that nontoxic, cost is low.
Brief description of the drawings
Fig. 1 is schematic structural view of the invention；
Indicated in figure：1- silicon chips；2-Ti metal levels；3-Ta metal levels；4-Au-Sn alloy eutectic metal levels；5-Au metal levels.
Embodiment
In order to deepen the understanding of the present invention, below in conjunction with embodiment and accompanying drawing, the invention will be further described, should
Embodiment is only used for explaining the present invention, is not intended to limit the scope of the present invention..
Fig. 1 shows a kind of a kind of embodiment of silicon chip back side metallized film of the invention, including is arranged on the silicon chip back of the body
The metallization eutectic structure in face, the metallization eutectic structure by be arranged on silicon chip 1 Ti metal levels 2, be arranged on Ti metals
Ta metal levels 3 and the Au-Sn alloy eutectics metal level 4 that is arranged on Ta metal levels 3 on layer 2 are constituted, in addition to are arranged on
Au metal levels 5 on Au-Sn alloy eutectics metal 4.
Embodiment 1
The silicon chip back side metallization eutectic structure of the present embodiment, including the Ti metal levels being arranged on silicon chip I, are arranged on Ti metals
Ta metal levels 3 and the Au-Sn alloy eutectics metal level 4 that is arranged on Ta metal levels 3 on layer 2.
The manufacturing process of the silicon chip back side metallization eutectic structure of the present embodiment, comprises the following steps:
1. will be thinned after silicon chip I be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon
Piece I is cleaned.Silicon corrodes and the method for silicon dioxide etching is specially:Use 1:20 HF erodes what be there may exist
Silicon dioxide layer
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Ti, Ta, Au-Sn and Au film are penetrated, Au-Sn alloys there can also be the conjunction of similarity using Au-Si etc. with Au-Sn alloys
Gold.
Illustrate:Using four cun of silicon wafers, the silicon chip for being thinned to 210 microns is carried out using HF-HN03 mixed acid
The back side is corroded, and corrosion to silicon wafer thickness is 200 ± 20 microns, and I is used after cleaning:20 HF acid solutions are further cleaned, and bath is got rid of
Magnetic-controlled sputtering coating equipment is sent into after dry.Cleaned using 500W radio frequency plasmas, magnetron sputtering skill is then used successively
Art is deposited with metal membrane:First layer Ti;It is 1000 ± 80 A to control thickness;Second layer Ta, control thickness for 1500 ±
150 A;Third layer Au-Sn alloys, it is 5000 ± 500A to control thickness.
Embodiment 2
The present embodiment silicon chip back side metallization eutectic structure, including be arranged on silicon chip Ti metal levels 2, be arranged on Ti metals
Ta metal levels 3, the Au-Sn alloy eutectics metal level 4 that is arranged on Ta metal levels 3 on layer 2 and it is arranged on Au-Sn alloys
Au metal levels 5 on eutectic metal level 4.
The manufacturing process of the silicon chip back side metallization eutectic structure of the present embodiment, comprises the following steps:
1. will be thinned after silicon chip be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon chip
I is cleaned.Silicon corrodes and the method for silicon dioxide etching is specially:Use 1:20 HF erodes there may exist two
Silicon oxide layer；
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Ti, Ta, Au-Sn and Au film are penetrated, Au-Sn alloys there can also be the conjunction of similarity using Au-Si etc. with Au-Sn alloys
Gold.
Illustrate:Using six cun of silicon wafers, 230 microns of silicon chips will be thinned to and carry out the back side with HF-HN03 mixed acid
Corrosion, corrosion to silicon wafer thickness is 225 ± 20 microns, and I is used after cleaning:20 HF acid solutions are further cleaned, and bath is dried
After send into magnetic-controlled sputtering coating equipment.Cleaned using 500W radio frequency plasmas, magnetron sputtering technique is then used successively
Deposition is with metal membrane:First layer Ti;It is 2000 ± 200 A to control thickness;Second layer Ta, it is 1000 ± 100 to control thickness
A;Third layer Au-Sn alloys, it is 3000 ± 500A to control thickness.4th layer of Au, it is 1000 ± 100A to control thickness.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (5)
1. a kind of silicon chip back side metallized film, it is characterised in that：Metallization eutectic structure including being arranged on silicon chip back side, institute
Metallization eutectic structure is stated by the Ti metal levels (2) being arranged on silicon chip (1), the Ta metal levels being arranged on Ti metal levels (2)
(3) and be arranged on Ta metal levels (3) Au-Sn alloy eutectic metal levels (4) composition.
2. silicon chip back side metallized film according to claim 1, it is characterised in that：Also include being arranged on Au-Sn alloys
Au metal levels (5) on eutectic metal (4).
3. a kind of preparation method of silicon chip back side metallized film, it is characterised in that：Comprise the following steps:
1. will be thinned after silicon chip be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon chip
Cleaned；
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Penetrate Ti, Ta, Au-Sn and Au film.
4. a kind of preparation method of silicon chip back side metallized film according to claim 3, it is characterised in that：The step
Middle silicon corrosion and the method for silicon dioxide etching are specially:Using passing through 1:20 HF erodes the silicon dioxide layer of presence；Most
Bath is dried afterwards.
5. a kind of preparation method of silicon chip back side metallized film, it is characterised in that：Comprise the following steps:
1. will be thinned after silicon chip be put into etching tank, by silicon corrode and silicon dioxide etching method to be thinned after silicon chip
Cleaned；
2. the silicon chip after cleaning is sent into and radio frequency plasma reverse sputtering cleaning is carried out in magnetic-controlled sputtering coating equipment, then successively splashed
Penetrate Ti, Ta, Au-Sn and Au film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710491088.5A CN107195606A (en) | 2017-06-26 | 2017-06-26 | A kind of silicon chip back side metallized film and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710491088.5A CN107195606A (en) | 2017-06-26 | 2017-06-26 | A kind of silicon chip back side metallized film and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107195606A true CN107195606A (en) | 2017-09-22 |
Family
ID=59878808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710491088.5A Pending CN107195606A (en) | 2017-06-26 | 2017-06-26 | A kind of silicon chip back side metallized film and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107195606A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389804A (en) * | 2018-02-28 | 2018-08-10 | 中国电子科技集团公司第十三研究所 | The sintering method of GaN chips and GaN chips to be sintered |
| CN110783292A (en) * | 2020-01-02 | 2020-02-11 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094170A (en) * | 2011-11-07 | 2013-05-08 | 英飞凌科技股份有限公司 | Method for separating a plurality of dies and a processing device for separating a plurality of dies |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
| CN104299922A (en) * | 2014-11-03 | 2015-01-21 | 苏州同冠微电子有限公司 | Back metallization eutectic process method |
-
2017
- 2017-06-26 CN CN201710491088.5A patent/CN107195606A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094170A (en) * | 2011-11-07 | 2013-05-08 | 英飞凌科技股份有限公司 | Method for separating a plurality of dies and a processing device for separating a plurality of dies |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
| CN104299922A (en) * | 2014-11-03 | 2015-01-21 | 苏州同冠微电子有限公司 | Back metallization eutectic process method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389804A (en) * | 2018-02-28 | 2018-08-10 | 中国电子科技集团公司第十三研究所 | The sintering method of GaN chips and GaN chips to be sintered |
| CN110783292A (en) * | 2020-01-02 | 2020-02-11 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process thereof |
| WO2021136222A1 (en) * | 2020-01-02 | 2021-07-08 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108520855B (en) | Method for improving reliability of ceramic copper-clad plate by using nano silver paste | |
| CN108033810A (en) | A kind of preparation method of aluminium nitride ceramics copper-clad plate | |
| JPH0212829A (en) | Bonding pad alloy layer and bonding pad structure | |
| CN105633038B (en) | A kind of copper pillar bump interconnection structure of oriented growth and preparation method thereof | |
| CN100481425C (en) | Semiconductor device having aluminum electrode and metallic electrode | |
| CN103963375B (en) | Silicon chip back side metallization eutectic structure and manufacturing process thereof | |
| CN102142465A (en) | Front electrode structure of schottky diode and process manufacturing method of front electrode structure | |
| TW200846497A (en) | Selective etch of TiW for capture pad formation | |
| CN105679683A (en) | Copper nanorod based copper-tin-copper bonding process and structure | |
| CN107195606A (en) | A kind of silicon chip back side metallized film and preparation method thereof | |
| CN1529343A (en) | Gold-tin-eutectic-based silicon/silicon bonding method | |
| CN105834541A (en) | Preparing method for low-temperature-connection and high-temperature-use Cu/Sn/Cu brazing interface and structure | |
| US3140527A (en) | Manufacture of semiconductor elements | |
| CN202736904U (en) | Copper pour silicon basal plate | |
| CN102064120A (en) | Soldering flux-free reflow technological method based on indium bumps | |
| CN203179893U (en) | Metallization eutectic structure on back surface of silicon wafer | |
| CN103151430B (en) | Nano metal particles realize the preparation method of the low-temperature metal interface connection of LED | |
| CN107195559A (en) | A kind of method for covering tin nano porous copper low-temperature bonding | |
| US9231139B2 (en) | Structure and design of concentrator solar cell assembly receiver substrate | |
| CN105489515B (en) | The eutectic welding method of semiconductor chip | |
| CN204257627U (en) | A kind of thin film integrated circuit with Sn/Au eutectic pad | |
| CN202208757U (en) | Ceramic sputtering target | |
| US5031822A (en) | Methods of joining components | |
| TW578250B (en) | Testing method of flip-chip junction | |
| CN206546818U (en) | The back metal structure of gallium arsenide chips |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170922 |