CN104299922A - Back metallization eutectic process method - Google Patents
Back metallization eutectic process method Download PDFInfo
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- CN104299922A CN104299922A CN201410608820.9A CN201410608820A CN104299922A CN 104299922 A CN104299922 A CN 104299922A CN 201410608820 A CN201410608820 A CN 201410608820A CN 104299922 A CN104299922 A CN 104299922A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/24—Vacuum evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/085—Material
- H01L2224/08501—Material at the bonding interface
- H01L2224/08502—Material at the bonding interface comprising an eutectic alloy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01321—Isomorphous Alloys
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a semiconductor processing process method and provides a back metallization eutectic process method. The method includes the following steps that (1) thinning processing is conducted on a silicon wafer through a thinning device; (2) first corrosion processing is conducted on the upper surface of a silicon slice; (3) the silicon slice is cleaned; (4) second corrosion processing is conducted on the upper surface of the silicon slice; (5) the silicon slice is flushed and dried; (6) metal evaporation processing is conducted on the upper surface of the silicon slice, and a titanium metal layer, a nickel metal layer and a tin antimony eutectic alloy layer are sequentially formed on the silicon slice; (7) encapsulation processing is conducted on the silicon slice through an eutectic welding process. According to the back metallization eutectic process method, the metal evaporation is conducted on the silicon slice to form a plurality of layers of metal layers, the first layer of the silicon slice is the titanium metal layer which can make good ohmic contact with the silicon slice, the second layer is the nickel layer which can make good contact with the titanium metal layer, the third layer is the tin antimony eutectic alloy layer which is free of highly toxic, safe and reliable, the process defects of an original back metallization eutectic process method are overcome, and the process cost is reduced.
Description
Technical field
The present invention relates to a kind of semiconducter process method, particularly relate to a kind of back face metalization eutectic technology method.
Background technology
Eutectic refers to the phenomenon of eutectic solder generation eutectic thing fusion at relatively low temperature, and eutectic alloy directly changes to liquid state from solid-state, and without the plastic stage.Its fusion temperature claims eutectic temperature.
Eutectic alloy has following characteristic:
(1) lower than pure constituent element fusing point, simplify melting process;
(2) eutectic alloy has better mobility than simple metal, can prevent the dendrite hindering liquid flow from being formed, thus improve casting character in solidifying;
(3) isothermal transformation, without solidification temperature range, decreases casting flaw, as segregation and shrinkage cavity;
(4) eutectic freezing can obtain the microscopic structure of variform, and especially regularly arranged stratiform or shaft-like eutectic structure, can become the in-situ composite of excellent properties.
Eutectic welding technology is used widely in Electronic Packaging industry, as bonding, the shell sealing cap etc. of bonding, substrate and the shell of chip and substrate.Compared with bonding with traditional epoxy conducting, eutectic welding has the advantage that thermal conductivity is high, resistance is little, heat transfer is fast, reliability is strong, bonding rear shearing force is large, be applicable to high frequency, high power device chips and substrate, substrate and shell interconnected.Eutectic must be adopted to weld for there being the power device of higher cooling requirements.Eutectic weldering be make use of eutectic alloy characteristic to complete welding procedure.
In prior art, normally used back face metalization eutectic technology gold-arsenic alloy or proof gold are used as metal plating layer on back, are realized the eutectic alloy of back metal by annealing process.Because arsenic has severe toxicity, proof gold price is extremely expensive again, so process program has a lot of defect.
Summary of the invention
The technical problem to be solved in the present invention is: adopt separately the problem of proof gold coating high cost in order to the arsenic solving gold-arsenic alloy in the coat of metal in existing back face metalization eutectic technology method has severe toxicity dangerous, the invention provides a kind of fail safe high nontoxic and cost reduces back face metalization eutectic technology method solves the problems referred to above.
The technical solution adopted for the present invention to solve the technical problems is: a kind of back face metalization eutectic technology method comprises the steps:
1) carry out reduction processing by stripping apparatus in silicon wafer, obtain the silicon chip as substrate;
2) first time corrosion treatment is carried out at described silicon chip upper surface, by further for silicon chip corrosion thinning;
3) clean water is carried out to described silicon chip;
4) evaporation of metal process is carried out to silicon chip upper surface, form titanium coating at silicon chip upper surface;
5) evaporation of metal process is proceeded to silicon chip, titanium coating forms nickel metal layer;
6) further evaporation of metal process is carried out to silicon chip, nickel metal layer is formed tin antimony eutectic alloy metal level;
7) eutectic welding procedure is adopted to carry out encapsulation process to silicon chip.
Further preferably, in step 3) after and in step 4) before, carry out step 3a) process, described step 3a) be carry out second time corrosion treatment at silicon chip (1) upper surface, the silicon dioxide layer that silicon chip (1) surface exists is removed, and then silicon chip (1) is carried out bath washing drying.
Further preferably, described step 2) and step 3a) corrosion treatment be carry out in etching tank, carry out control corrosion rate speed by the temperature of the corrosive liquid in control corrosion rate groove, described temperature is between 30 DEG C-80 DEG C.Make the silicon wafer thickness after corrosion controlled, can ensure that silicon chip obtains satisfactory thickness after corrosion.
Further preferably, described step 3a) in the corrosive liquid that uses of corrosion treatment be HF, the mass concentration of described HF is 1%.Corrosive liquid meets technological requirement, is easy to realize.
Further preferably, described step 2) in the corrosive liquid that uses of corrosion treatment be HF and HNO
3mixed acid, HF and HNO
3quality proportioning be 1:3.Corrosive liquid meets technological requirement, is easy to realize.
Further preferably, described step 4), 5) and 6) in technical process carry out carrying on the back in gold evaporation stove.Process equipment manipulation is simple, and cost is low.
Further preferably, described process can also in step 6) and step 7) between further evaporation of metal process is carried out to silicon chip, tin antimony eutectic alloy metal level forms gold metal layer.Superposition gold metal layer, with the requirement of satisfied different eutectic packaging technique.
Further preferably, described silicon chip is 4 cun of silicon wafer, and described titanium coating thickness is
nickel metal layer thickness is
tin antimony eutectic alloy metal layer thickness is
the metal layer thickness of this structure meets 4 cun of silicon wafer in technologic requirement.
Preferably another kind of, described silicon chip is 6 cun of silicon wafer, and described titanium coating thickness is
nickel metal layer thickness is
tin antimony eutectic alloy metal layer thickness is
the metal layer thickness of this structure meets 6 cun of silicon wafer in technologic requirement.
The invention has the beneficial effects as follows, more metal layers is formed in the enterprising row metal evaporation of silicon chip in back face metalization eutectic technology method of the present invention, ground floor on silicon chip is titanium coating, good ohmic can be formed with silicon chip to contact, the second layer is that nickel metal layer can form good contact with titanium coating, third layer is tin antimony eutectic alloy metal level, no longer adopt gold-arsenic alloy as metal level, safe and reliable without severe toxicity, without the need to adopting separately proof gold coating, process costs is low, change the defective workmanship of original back face metalization eutectic technology method, reduce process costs.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the silicon chip back side metal-layer structure schematic diagram of silicon chip after back face metalization eutectic technology method of the present invention process.
In figure 1, silicon chip; 2, titanium coating; 3, nickel metal layer; 4, tin antimony eutectic alloy metal level.
Embodiment
In conjunction with the accompanying drawings, the present invention is further detailed explanation.These accompanying drawings are the schematic diagram of simplification, only basic structure of the present invention are described in a schematic way, and therefore it only shows the formation relevant with the present invention.
As shown in Figure 1, the embodiment of the present invention one: adopt back face metalization eutectic technology method to 4 cun of silicon wafer, step is as follows:
1) carry out reduction processing by stripping apparatus in silicon wafer, silicon wafer is thinned to 210 microns, obtains the silicon chip 1 as substrate;
2) in etching tank, carry out first time corrosion treatment to silicon chip 1 upper surface, carry out control corrosion rate speed by the temperature of the corrosive liquid in control corrosion rate groove, described temperature is between 30 DEG C-80 DEG C, and the corrosive liquid of use is HF and HNO
3mixed acid, HF and HNO
3quality proportioning be 1:3, corrosion after silicon chip 1 thickness be 200 ± 20 microns;
3) clean water is carried out to described silicon chip 1;
4) in etching tank, second time corrosion treatment is carried out to silicon chip 1 upper surface, the corrosive liquid of use to be mass concentration be 1% HF, the silicon dioxide layer that silicon chip 1 surface exists is removed;
5) silicon chip 1 is carried out bath to dry;
6) in back of the body gold evaporation stove, carry out evaporation of metal process to silicon chip 1 upper surface, form titanium coating 2 at silicon chip 1 upper surface, titanium coating 2 thickness is
7) in back of the body gold evaporation stove, proceed evaporation of metal process to silicon chip 1, titanium coating 2 is formed nickel metal layer 3, and nickel metal layer 3 thickness is
8) in back of the body gold evaporation stove, carry out evaporation of metal process further to silicon chip 1, nickel metal layer 3 is formed tin antimony eutectic alloy metal level 4, and tin antimony eutectic alloy metal level 4 thickness is
9) eutectic welding procedure is adopted to carry out encapsulation process to silicon chip 1.
Be appreciated that embodiment one, when silicon chip 1 not existing silicon dioxide layer, step 4) and step 5) can omit.
As shown in Figure 1, the embodiment of the present invention two: adopt back face metalization eutectic technology method to 6 cun of silicon wafer, step is as follows:
1) carry out reduction processing by stripping apparatus in silicon wafer, silicon wafer is thinned to 230 microns, obtains the silicon chip 1 as substrate;
2) in etching tank, carry out first time corrosion treatment to silicon chip 1 upper surface, carry out control corrosion rate speed by the temperature of the corrosive liquid in control corrosion rate groove, described temperature is between 30 DEG C-80 DEG C, and the corrosive liquid of use is HF and HNO
3mixed acid, HF and HNO
3quality proportioning be 1:3, corrosion after silicon chip 1 thickness be 225 ± 20 microns;
3) clean water is carried out to described silicon chip 1;
4) in etching tank, second time corrosion treatment is carried out to silicon chip 1 upper surface, the corrosive liquid of use to be mass concentration be 1% HF, the silicon dioxide layer that silicon chip 1 surface exists is removed;
5) silicon chip 1 is carried out bath to dry;
6) in back of the body gold evaporation stove, carry out evaporation of metal process to silicon chip 1 upper surface, form titanium coating 2 at silicon chip 1 upper surface, titanium coating 2 thickness is
7) in back of the body gold evaporation stove, proceed evaporation of metal process to silicon chip 1, titanium coating 2 is formed nickel metal layer 3, and nickel metal layer 3 thickness is
8) in back of the body gold evaporation stove, carry out evaporation of metal process further to silicon chip 1, nickel metal layer 3 is formed tin antimony eutectic alloy metal level 4, and tin antimony eutectic alloy metal level 4 thickness is
9) eutectic welding procedure is adopted to carry out encapsulation process to silicon chip.
Same concerning embodiment two, be appreciated that when silicon chip 1 not existing silicon dioxide layer, step 4) and step 5) can omit.
To the process in above-described embodiment one and embodiment two, according to the requirement of different eutectic packaging technique, can in step 8) and step 9) between further evaporation of metal process is carried out to silicon chip 1, tin antimony eutectic alloy metal level 4 forms gold metal layer.
More metal layers is formed in the enterprising row metal evaporation of silicon chip 1 in back face metalization eutectic technology method of the present invention, ground floor on silicon chip 1 is titanium coating 2, good ohmic can be formed with silicon chip 1 to contact, the second layer is that nickel metal layer 3 can form good contact with titanium coating 2, third layer is tin antimony eutectic alloy metal level, no longer adopt gold-arsenic alloy as metal level, safe and reliable without severe toxicity, without the need to adopting separately proof gold coating, process costs is low, change the defective workmanship of original back face metalization eutectic technology method, reduce process costs.
With above-mentioned according to desirable embodiment of the present invention for enlightenment, by above-mentioned description, relevant staff in the scope not departing from this invention technological thought, can carry out various change and amendment completely.The technical scope of this invention is not limited to the content on specification, must determine its technical scope according to right.
Claims (9)
1. a back face metalization eutectic technology method, its step is as follows:
1) carry out reduction processing by stripping apparatus in silicon wafer, obtain the silicon chip (1) as substrate;
2) first time corrosion treatment is carried out at described silicon chip (1) upper surface, by silicon chip (1) corrosion thinning further;
3) clean water is carried out to described silicon chip (1);
4) evaporation of metal process is carried out to silicon chip (1) upper surface, form titanium coating (2) at silicon chip (1) upper surface;
5) evaporation of metal process is proceeded to silicon chip (1), titanium coating (2) is formed nickel metal layer (3);
6) further evaporation of metal process is carried out to silicon chip (1), at nickel metal layer (3) upper formation tin antimony eutectic alloy metal level (4);
7) eutectic welding procedure is adopted to carry out encapsulation process to silicon chip (1).
2. back face metalization eutectic technology method according to claim 1, it is characterized in that: in step 3) and step 4) between, carry out step 3a) process, described step 3a) be carry out second time corrosion treatment at silicon chip (1) upper surface, the silicon dioxide layer that silicon chip (1) surface exists is removed, and then silicon chip (1) is carried out bath washing drying.
3. back face metalization eutectic technology method according to claim 2, it is characterized in that: described step 2) and step 3a) corrosion treatment be carry out in etching tank, carry out control corrosion rate speed by the temperature of the corrosive liquid in control corrosion rate groove, described temperature is between 30 DEG C-80 DEG C.
4. back face metalization eutectic technology method according to claim 2, is characterized in that: described step 3a) in corrosion treatment use corrosive liquid be HF, the mass concentration of described HF is 1%.
5. back face metalization eutectic technology method according to claim 1, is characterized in that: described step 2) in corrosion treatment use corrosive liquid be HF and HNO
3mixed acid, HF and HNO
3quality proportioning be 1:3.
6. back face metalization eutectic technology method according to claim 1, is characterized in that: described step 4), 5) and 6) in technical process carry out in back of the body gold evaporation stove.
7. back face metalization eutectic technology method according to claim 1, it is characterized in that: described process can also in step 6) and step 7) between further evaporation of metal process is carried out to silicon chip (1), tin antimony eutectic alloy metal level (4) forms gold metal layer.
8. back face metalization eutectic technology method according to claim 1, is characterized in that: described silicon chip (1) is 4 cun of silicon wafer, and described titanium coating (2) thickness is
nickel metal layer (3) thickness is
tin antimony eutectic alloy metal level (4) thickness is
9. back face metalization eutectic technology method according to claim 1, is characterized in that: described silicon chip (1) is 6 cun of silicon wafer, and described titanium coating (2) thickness is
nickel metal layer (3) thickness is
tin antimony eutectic alloy metal level (4) thickness is
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410608820.9A CN104299922A (en) | 2014-11-03 | 2014-11-03 | Back metallization eutectic process method |
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| CN201410608820.9A CN104299922A (en) | 2014-11-03 | 2014-11-03 | Back metallization eutectic process method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195606A (en) * | 2017-06-26 | 2017-09-22 | 昆山昊盛泰纳米科技有限公司 | A kind of silicon chip back side metallized film and preparation method thereof |
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| CN101887862A (en) * | 2009-05-13 | 2010-11-17 | 华越微电子有限公司 | Silicon wafer back metalizing process for eutectic bonding |
| KR20120096198A (en) * | 2011-02-22 | 2012-08-30 | 서울대학교산학협력단 | Ceramic coating method for corrosion resistant member and corrosion resistant member coated by ceramic |
| CN103579158A (en) * | 2013-11-08 | 2014-02-12 | 天水天光半导体有限责任公司 | Eutectic bonding silicon metalized metal piece and metallization process thereof |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
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2014
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101641785A (en) * | 2006-11-09 | 2010-02-03 | 跃进封装公司 | Microcircuit package having ductile layer |
| CN101887862A (en) * | 2009-05-13 | 2010-11-17 | 华越微电子有限公司 | Silicon wafer back metalizing process for eutectic bonding |
| KR20120096198A (en) * | 2011-02-22 | 2012-08-30 | 서울대학교산학협력단 | Ceramic coating method for corrosion resistant member and corrosion resistant member coated by ceramic |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107195606A (en) * | 2017-06-26 | 2017-09-22 | 昆山昊盛泰纳米科技有限公司 | A kind of silicon chip back side metallized film and preparation method thereof |
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