CN102437177B - Novel Schottky flip-chip and manufacturing process thereof - Google Patents
Novel Schottky flip-chip and manufacturing process thereof Download PDFInfo
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- CN102437177B CN102437177B CN 201110392125 CN201110392125A CN102437177B CN 102437177 B CN102437177 B CN 102437177B CN 201110392125 CN201110392125 CN 201110392125 CN 201110392125 A CN201110392125 A CN 201110392125A CN 102437177 B CN102437177 B CN 102437177B
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Abstract
The invention discloses a novel Schottky flip-chip which comprises a packaging body, a chip anode, a chip cathode, a silicon chip, a silicon chip anode and a silicon chip cathode. The silicon chip anode is connected with the chip anode. The silicon chip cathode is connected with the chip cathode. The silicon chip anode and the silicon chip cathode are positioned at a same side surface of the silicon chip. The silicon chip anode is on a surface of the silicon chip. A groove is provided beside the silicon chip anode. The silicon chip cathode is positioned in the groove. The invention also discloses manufacturing process of the novel Schottky flip-chip. The manufacturing process comprises the following steps: providing an original epitaxial silicon chip; carrying out oxidation on the original epitaxial silicon chip; carrying out photoetching for the first time; carrying out p-ring diffusion; carrying out photoetching groove for the second time; carrying out photoetching for the third time; carrying out corrosion for the first time, sputtering metal Pt and Ni; evaporating contact metal Ti, Ni and Ag; carrying out soldering tin and packaging to obtain a finished product. The novel Schottky flip-chip has the advantages of a small volume, thinness and good performance.
Description
Technical field
The present invention relates to a kind of Schottky and fall packaged chip and manufacturing process, relate in particular to novel Schottky that a kind of both positive and negative polarity is positioned at same side and negative pole indent and fall packaged chip and manufacturing process.
Background technology
It is the Schottky chip that adopts the production of falling the encapsulation technology that Schottky falls packaged chip, tin playing skill art is adopted in the encapsulation of falling of current chip, this technology has replaced traditional pin encapsulation, the form of leaded package, thereby in the important function that has played electric interconnection and mechanical support aspect the tin ball, be a kind of more satisfactory encapsulation technology.
Adopt the Schottky chip of tin playing skill art processing at present, its structure is for arranging the tin ball of projection as positive pole and the negative pole of chip on the surface of silicon chip.This structure makes the thickness of product increase on the one hand because the link of projection is set, will go under the more and more littler situation its adaptability worse and worse in modern society to the volume of electronic product; Distance is not far and do not carry out isolation processing between positive pole and the negative pole on the other hand, so the isolation effect between the positive and negative electrode of its output is not fine, when in the circuit of some high request, using, can can't not satisfy instructions for use because the isolation between its positive and negative electrode is not high.
Summary of the invention
Purpose of the present invention is fallen packaged chip and manufacturing process with regard to the novel Schottky that provides a kind of both positive and negative polarity to be positioned at same side and negative pole indent in order to address the above problem is provided.
In order to achieve the above object, the present invention has adopted following technical scheme:
A kind of Schottky falls the manufacturing process of packaged chip, described Schottky falls packaged chip and comprises packaging body, chip positive pole, chip negative pole, silicon chip, silicon chip positive pole and silicon chip negative pole, the anodal connection of the anodal and described chip of described silicon chip, described silicon chip negative pole is connected with described chip negative pole, and described silicon chip positive pole and described silicon chip negative pole are positioned at the same side of described silicon chip; Described silicon chip positive pole is positioned on the surface of described silicon chip, and the next door of described silicon chip positive pole is provided with groove, and described silicon chip negative pole is positioned at described groove, is provided with isolated groove between described silicon chip positive pole and the described groove; Described manufacturing process may further comprise the steps:
(1) provides an original epitaxial silicon chip;
(2) original epitaxial silicon chip is carried out oxidation, form oxide layer;
(3) photoetching form once anodal groove and an isolated groove;
(4) P ring diffusion is spread by the once anodal groove in the oxide layer and an isolated groove, and the position corresponding with anodal groove once and isolated groove forms P respectively and encircle in epitaxial silicon chip;
(5) secondary light ditch groove forms one time the negative pole groove;
(6) once corrosion forms anodal groove blank, isolated groove blank and negative pole groove blank;
(7) third photo etching forms the anodal groove in band angle, band angle isolated groove and band angle negative pole groove;
(8) anticaustic forms smooth anodal groove, smooth isolated groove and smooth negative pole groove;
(9) at smooth anodal groove and smooth negative pole groove difference splash-proofing sputtering metal Pt, Ni;
(10) evaporation contacting metal Ti, Ni, Ag form the anodal and silicon chip negative pole of silicon chip;
(11) scolding tin connects the anodal and chip positive pole of silicon chip, connects silicon chip negative pole and chip negative pole, and encapsulation gets finished product.
Particularly, the epitaxy layer thickness of original epitaxial silicon chip is 5-10 microns in described (1); Thickness of oxide layer is 5000 dusts in described (2); Ambient temperature is 450 ℃ in described (9), and the mass percent of nitrogen and hydrogen is respectively 90% and 10%; In described (6) and described (8), the component of the corrosive liquid that described corrosion is used is: HF, HAC, HNO
3The quality proportioning of the each component of described corrosive liquid is: HF:HAC:HNO
3=1:1:15-25.
Beneficial effect of the present invention is:
Anodal and silicon chip negative pole is arranged at the same side of silicon chip because the present invention is with silicon chip, and the thickness of entire product is reduced greatly; Because the silicon chip negative pole is arranged in the groove, the thickness of entire product is further reduced, and make the isolation performance between silicon chip positive pole and the silicon chip negative pole better, satisfy various circuit fully to the high request of isolation performance between the positive and negative electrode; By between silicon chip positive pole and silicon chip negative pole, isolated groove being set, the isolation performance between silicon chip positive pole and the silicon chip negative pole is further improved.Manufacturing process of the present invention can realize that precision is ± 0.15 micron smooth groove, satisfy the high-precision requirement of Schottky chip fully, and the surface area that makes silicon enlarge about more than 20%, so same chip area adopts manufacturing process of the present invention that the product operating efficiency is improved near 20%.
Description of drawings
Fig. 1 is that Schottky falls the main TV structure schematic diagram of packaged chip among the present invention;
Fig. 2 is that Schottky falls the main TV structure schematic diagram of silicon chip of packaged chip among the present invention;
Fig. 3 be among the present invention Schottky fall packaged chip silicon chip look up structural representation;
Fig. 4 is that Schottky falls the manufacturing process flow diagram of packaged chip among the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described in detail:
As Fig. 1, Fig. 2 and shown in Figure 3, the novel Schottky among the present invention falls packaged chip and comprises packaging body 16, chip positive pole 13, chip negative pole 14, silicon chip 12, silicon chip anodal 10 and silicon chip negative pole 11, and the gross thickness of packaging body 16 is 0.6-0.7mm; Silicon chip anodal 10 is connected with chip anodal 13, and silicon chip negative pole 11 is connected with chip negative pole 14; Silicon chip anodal 10 and silicon chip negative pole 11 are arranged in the same side (Fig. 1 and Fig. 2's is following) of silicon chip 12; Silicon chip positive pole 10 is positioned on the surface of silicon chip 12, and the next door of silicon chip positive pole 10 is provided with groove 37, and silicon chip negative pole 11 is positioned at groove 37.The degree of depth of groove 37 is 15-20 microns.1 is the epitaxial loayer of silicon chip 12 among the figure, and its thickness is between 5-10 microns, and 2 is oxide layer, and general about 1 micron, 8 is a metal level between silicon chip anodal 10 and the epitaxial loayer 1, and 9 is a metal level between silicon chip negative pole 11 and the silicon chip 12.
As Fig. 1, Fig. 2 and shown in Figure 3, be provided with isolated groove 34 between silicon chip anodal 10 and the groove 37.Isolated groove 34 makes the isolation performance between silicon chip anodal 10 and the silicon chip negative pole 11 better.
As shown in Figure 1, the surface of the surface of silicon chip positive pole 10 and silicon chip negative pole 11 is provided with soldering-tin layer 15, and silicon chip anodal 10 is connected with chip anodal 13 by soldering-tin layer 15, and the soldering-tin layer 15 on silicon chip negative pole 11 surfaces is connected with chip negative pole 14 by lead.Chip anodal 13 and chip negative pole 14 all are positioned at the surface of packaging body 16.
As Fig. 1, Fig. 2 and shown in Figure 3, silicon chip anodal 10 and silicon chip negative pole 11 are arranged at the same side of silicon chip 12, the thickness of entire chip is reduced greatly; The setting of groove 37 has guaranteed that then the isolation performance between silicon chip anodal 10 and the silicon chip negative pole 11 satisfies its instructions for use fully.
As shown in Figure 4, the Schottky among the present invention falls the manufacturing process of packaged chip, may further comprise the steps:
(1) provide 400 microns of original epitaxial silicon chip 12(gross thickness, the thickness of Biao Shi silicon chip 12 is compressed here much doubly, just illustrates its existence), the thickness of its epitaxial loayer 1 is 5 microns;
(2) original epitaxial silicon chip 12 is carried out oxidation, form oxide layer 2(silicon dioxide, chemical formula: SiO
2), the thickness of oxide layer 2 is 5000 dusts;
(3) photoetching form once anodal groove 3 and an isolated groove 4; From this width of cloth figure, in order to explain structural change, the thickness of oxide layer 2 and epitaxial loayer 1 has been amplified, the thickness of silicon chip 12 is compressed much doubly, just illustrates its existence;
(4) P ring diffusion is spread by the once anodal groove in the oxide layer and an isolated groove, and the position corresponding with anodal groove once and isolated groove forms P respectively and encircle in epitaxial silicon chip;
(5) secondary light ditch groove forms one time negative pole groove 5;
(6) once corrosion forms anodal groove blank 23, isolated groove blank 24 and negative pole groove blank 25;
(7) third photo etching forms the anodal groove 6 in band angle, band angle isolated groove 24 and band angle negative pole groove 7;
(8) anticaustic forms smooth anodal groove 36, smooth isolated groove 34 and smooth negative pole groove 37;
(9) at smooth anodal groove 36 and smooth negative pole groove 37 symbol of splash-proofing sputtering metal Pt(chemical elements " platinum " respectively), the symbol of Ni(chemical element " nickel "), form an anodal metal level 8 and metal level 9 of negative pole;
(10) symbol of evaporation contacting metal Ti(chemical element " titanium "), the symbol of Ni, Ag(chemical element " silver "), forming anodal secondary metals layer is that silicon chip anodal 10 and negative pole secondary metals layer are silicon chip negative pole 11;
(11) scolding tin forms soldering-tin layer 15, connects silicon chip anodal 10 and chip positive pole 13, connects silicon chip negative pole 10 and chip negative pole 14, and encapsulation gets finished product.
Ambient temperature is 450 ℃ in above-mentioned (9), and the mass percent of nitrogen and hydrogen is respectively 90% and 10%; In above-mentioned (6) and (8), the component of the corrosive liquid that described corrosion is used is: HF, HAC, HNO
3The quality proportioning of the each component of described corrosive liquid is: HF:HAC:HNO
3=1:1:15-25.Above-mentioned corrosive liquid utilizes high-accuracy temperature control instrument of the prior art for hanging down the heating corrosive liquid at a slow speed, and temperature control just can be finished processing at 13 ℃-17 ℃.
Claims (5)
1. a Schottky falls the manufacturing process of packaged chip, described Schottky falls packaged chip and comprises packaging body, chip positive pole, chip negative pole, silicon chip, silicon chip positive pole and silicon chip negative pole, the anodal connection of the anodal and described chip of described silicon chip, described silicon chip negative pole is connected with described chip negative pole, and described silicon chip positive pole and described silicon chip negative pole are positioned at the same side of described silicon chip; Described silicon chip positive pole is positioned on the surface of described silicon chip, and the next door of described silicon chip positive pole is provided with groove, and described silicon chip negative pole is positioned at described groove, is provided with isolated groove between described silicon chip positive pole and the described groove; It is characterized in that: described manufacturing process may further comprise the steps:
(1) provides an original epitaxial silicon chip;
(2) original epitaxial silicon chip is carried out oxidation, form oxide layer;
(3) photoetching form once anodal groove and an isolated groove;
(4) P ring diffusion is spread by the once anodal groove in the oxide layer and an isolated groove, and the position corresponding with anodal groove once and isolated groove forms P respectively and encircle in epitaxial silicon chip;
(5) secondary light ditch groove forms one time the negative pole groove;
(6) once corrosion forms anodal groove blank, isolated groove blank and negative pole groove blank;
(7) third photo etching forms the anodal groove in band angle, band angle isolated groove and band angle negative pole groove;
(8) anticaustic forms smooth anodal groove, smooth isolated groove and smooth negative pole groove;
(9) at smooth anodal groove and smooth negative pole groove difference splash-proofing sputtering metal Pt, Ni;
(10) evaporation contacting metal Ti, Ni, Ag form the anodal and silicon chip negative pole of silicon chip;
(11) scolding tin connects the anodal and chip positive pole of silicon chip, connects silicon chip negative pole and chip negative pole, and encapsulation gets finished product.
2. Schottky according to claim 1 falls the manufacturing process of packaged chip, and it is characterized in that: the epitaxy layer thickness of original epitaxial silicon chip is the 5-10 micron in described (1); Thickness of oxide layer is 5000 dusts in described (2).
3. Schottky according to claim 1 falls the manufacturing process of packaged chip, it is characterized in that: ambient temperature is 450 ℃ in described (9), and the mass percent of nitrogen and hydrogen is respectively 90% and 10%.
4. Schottky according to claim 1 falls the manufacturing process of packaged chip, and it is characterized in that: in described (6) and described (8), the component of the corrosive liquid that described corrosion is used is: HF, HAC, HNO
3
5. Schottky according to claim 4 falls the manufacturing process of packaged chip, and it is characterized in that: the quality proportioning of the each component of described corrosive liquid is: HF: HAC: HNO
3=1: 1: 15-25.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110392125 CN102437177B (en) | 2011-12-01 | 2011-12-01 | Novel Schottky flip-chip and manufacturing process thereof |
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|---|---|---|---|
| CN 201110392125 CN102437177B (en) | 2011-12-01 | 2011-12-01 | Novel Schottky flip-chip and manufacturing process thereof |
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| CN102437177B true CN102437177B (en) | 2013-09-04 |
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| CN108538924A (en) * | 2018-05-16 | 2018-09-14 | 捷捷半导体有限公司 | A kind of plastic packaging SiC Schottky diode device and its manufacturing method |
| CN109346405B (en) * | 2018-11-23 | 2021-12-03 | 江苏新广联科技股份有限公司 | Preparation method of GaN-based SBD flip chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5930636A (en) * | 1996-05-13 | 1999-07-27 | Trw Inc. | Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes |
| CN102184853A (en) * | 2011-05-06 | 2011-09-14 | 上海宏力半导体制造有限公司 | Manufacturing method of Schottky diode |
| CN202363463U (en) * | 2011-12-01 | 2012-08-01 | 重庆平伟实业股份有限公司 | Novel Schottky flip packaging chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008085190A (en) * | 2006-09-28 | 2008-04-10 | Sanyo Electric Co Ltd | Semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5930636A (en) * | 1996-05-13 | 1999-07-27 | Trw Inc. | Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes |
| CN102184853A (en) * | 2011-05-06 | 2011-09-14 | 上海宏力半导体制造有限公司 | Manufacturing method of Schottky diode |
| CN202363463U (en) * | 2011-12-01 | 2012-08-01 | 重庆平伟实业股份有限公司 | Novel Schottky flip packaging chip |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2008-85190A 2008.04.10 |
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