CN108376711A - The method for preparing the two-dimensional semiconductor transistor with top gate structure and polymer dielectric dielectric layer - Google Patents
The method for preparing the two-dimensional semiconductor transistor with top gate structure and polymer dielectric dielectric layer Download PDFInfo
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- CN108376711A CN108376711A CN201810014816.8A CN201810014816A CN108376711A CN 108376711 A CN108376711 A CN 108376711A CN 201810014816 A CN201810014816 A CN 201810014816A CN 108376711 A CN108376711 A CN 108376711A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229920000642 polymer Polymers 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000007772 electrode material Substances 0.000 claims abstract description 10
- 239000003792 electrolyte Substances 0.000 claims abstract description 10
- 238000004528 spin coating Methods 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 42
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 27
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 14
- 239000012528 membrane Substances 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 8
- 229920003171 Poly (ethylene oxide) Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000006701 autoxidation reaction Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- MHCFAGZWMAWTNR-UHFFFAOYSA-M lithium perchlorate Chemical compound [Li+].[O-]Cl(=O)(=O)=O MHCFAGZWMAWTNR-UHFFFAOYSA-M 0.000 claims description 3
- 229910001486 lithium perchlorate Inorganic materials 0.000 claims description 3
- 239000005518 polymer electrolyte Substances 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 150000003839 salts Chemical class 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 241000209094 Oryza Species 0.000 claims 2
- 235000007164 Oryza sativa Nutrition 0.000 claims 2
- 235000009566 rice Nutrition 0.000 claims 2
- 238000001704 evaporation Methods 0.000 claims 1
- 230000008020 evaporation Effects 0.000 claims 1
- XQHAGELNRSUUGU-UHFFFAOYSA-M lithium chlorate Chemical compound [Li+].[O-]Cl(=O)=O XQHAGELNRSUUGU-UHFFFAOYSA-M 0.000 claims 1
- CZMRCDWAGMRECN-UGDNZRGBSA-N Sucrose Chemical compound O[C@H]1[C@H](O)[C@@H](CO)O[C@@]1(CO)O[C@@H]1[C@H](O)[C@@H](O)[C@H](O)[C@@H](CO)O1 CZMRCDWAGMRECN-UGDNZRGBSA-N 0.000 abstract 1
- 229930006000 Sucrose Natural products 0.000 abstract 1
- 239000005720 sucrose Substances 0.000 abstract 1
- 238000002360 preparation method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 235000010210 aluminium Nutrition 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 2
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 241001282153 Scopelogadus mizolepis Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003760 magnetic stirring Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention belongs to two-dimensional semiconductor transistor arts, specially a kind of method preparing the two-dimensional semiconductor transistor with top gate structure and polymer dielectric dielectric layer.The method of the present invention includes prepares a series of stacked structures, the stacked structure is bottom-up be successively substrate, two-dimensional semiconductor material, the metal electrode material for serving as source electrode and drain electrode, spin coating formation electrolyte medium film, serve as the metal electrode material of grid.Electrolyte specific capacitance with bigger compared with traditional sucrose material, and the topological structure that the grid is top-gated.Therefore, the method for the present invention can solve application problem of the two-dimensional semiconductor field-effect transistor on low-work voltage, low-power consumption, high speed circuit and flexible circuit.
Description
Technical field
The invention belongs to two-dimensional semiconductor transistor arts, and in particular to the preparation side of two-dimensional semiconductor transistor
Method.
Background technology
Since the structure of double-layer electric can be formed at polymer dielectric and electrode interface, so they are normal relative to high dielectric
Number material still has prodigious specific capacitance（〜10μF·cm-2）.Sensing carrier density in semiconductor can be continuously adjusted to 5
×1013cm-2, field-effect transistor can be thus adjusted between p-type and N-shaped（FET）Polarity.This is not only characterization half
Conductor, and provide unique advantage for various device applications.Solution processability at room temperature can also be applied to big
Scale circuit.Recently, they are used as basic research and improve the powerful platform of emerging two-dimensional layer material performance index.Due to
Lack dangling bonds or functional group on the basal plane of two-dimensional layer material, therefore uses atomic layer deposition on two-dimensional layer material surface
The gate-dielectric that long-pending mode forms high-k is very difficult.Thin electrolytic thin-membrane may be to solve the problems, such as this
Ideal scheme.In addition, the impressionability and foldability of thin electrolytic thin-membrane also become next-generation printing and flexible electrical
The possibility of sub- products application selects.However, top-gated mostly uses the mode of photoetching and defines in traditional semiconductor technology, but photoetching
Process can but pollute polymer dielectric, and influence its performance, and which has limited the structures of top-gated in polymer dielectric transistor
On application.In addition, if polymer electrolyte film is in direct contact with source drain electrode, such transistor can possess
Larger grid leakage current increases additional power consumption.
Invention content
If two-dimensional semiconductor material, using traditional dielectric material as dielectric layer, transistor usually has work
Voltage is high, power consumption is big, the inflexible disadvantage of dielectric layer；If existing preparation process is used on electrolytic thin film transistor,
There is a problem of that grid leakage current is excessive again；Electrolytic thin film transistor is difficult to define top-gated by the way of photoetching；According to
The grid-control mode of side grid structure, and there is the response speed for leading to transistor because electrolyte intermediate ion effective mobility is apart from excessive
Spend slow problem.In view of such situation, present invention aims at provide it is a kind of it is completely new with top gate structure with polymer
Preparation method of the electrolyte as the high-performance two-dimensional semiconductor transistor of dielectric layer, to solve the above problems.
The method provided by the invention for preparing two-dimensional semiconductor field-effect transistor is related to preparing a series of stacked structures,
The bottom-up stacked structure is substrate, two-dimensional semiconductor material, the metal electrode material for serving as source electrode and drain electrode, rotation successively
Apply the electrolyte medium layer formed, the metal electrode material for serving as grid.Wherein, the material for serving as dielectric layer is polymer electrolytic
Matter；There is one layer of alumina protective layer between the metal electrode material and dielectric layer of source electrode and drain electrode；Gate electrode is the topology of top-gated
Structure.
Preparation is as follows：
（1）Two-dimensional semiconductor material layer is prepared on substrate；
（2）Metal electrode material is prepared in two-dimensional semiconductor material layer, as source electrode and drain electrode；
（3）One layer of aluminium oxide is deposited in the source electrode and drain electrode, as protective layer, specific method includes：Number nanogold is deposited
Belong to aluminium, its autoxidation is allowed to obtain alumina layer；Or the form of aluminium oxide is directly deposited directly by the way of atomic layer deposition
Obtain alumina layer；
（4）In the structure handled through above-mentioned steps（Including two-dimensional semiconductor material layer, alumina layer）Upper spin on polymers electrolysis
Matter, to form polymer dielectric dielectric layer in homogeneous thickness（Film）, specific method：The polymer dielectric is dissolved in methanol
In, the methanol solution of polymer dielectric is obtained, then solution is spun in two-dimensional semiconductor material layer using spin-coating method, is steamed
Methanol is sent out, polymer dielectric dielectric thin film layer is obtained；
（5）On being formed by electrolytic thin-membrane, the gate electrode of transistor is made, which is the topological structure of top-gated.Tool
Body method includes：Top-gated position is defined with the hard mask plate of high-precision, forms top-gated metal electricity by the way of vapor deposition or sputtering
Pole.
In the present invention, the substrate can be substrate commonly used in the art, as glass substrate, Sapphire Substrate, quartz substrate,
Silicon substrate etc., or flexible substrate is used, flexible circuit is made.
In the present invention, the thickness of the protective layer of alumina is about several nanometers, such as 3-8 nanometers.
In the present invention, the electrolytic polymer, usually by polymer（Such as：Polyethylene oxide（PEO））Be dissolved in
Li salt therein（Such as：Lithium perchlorate（LiClO4））Composition.Its mass ratio is PEO：LiClO4 is 7:1—10:1, preferably matter
Amount is than being 8:1.
In the present invention, formed a film using the polymer dielectric that spin-coating method is formed, speed is fast, and film is uniform, and thickness is controllable.It is poly-
Polymer electrolyte film forming thickness is generally 1 micron -10 microns.
The high-performance using polymer dielectric as dielectric layer with top gate structure has been prepared by the method for the present invention
Two-dimensional semiconductor transistor.
Invention effect
According to the present invention, a kind of flexible electrolysis that quickly formation is uniform on two-dimensional semiconductor material, thickness is controllable is provided
The method of matter dielectric film solves the problems, such as that two-dimensional semiconductor transistor operating voltage is high, power consumption is big, dielectric layer is inflexible；
Solve the problems, such as that the grid of electrolytic thin film transistor has larger leakage current；It is realized using the technology of the hard mask plate of high-precision
The device topological structure of top-gated shortens the effective mobility distance of ion in electrolyte medium, improves the switching speed of transistor.
Current two-dimensional semiconductor transistor is breached, is expected to be applied in the production of large scale integrated circuit in future.
Description of the drawings
Fig. 1 is the substrate schematic diagram covered by two-dimensional semiconductor material.
Fig. 2 is source drain metal electrode and leakage protection layer schematic diagram.
Fig. 3 is the homogeneous electrolyte film schematic diagram to be formed.
Fig. 4 is the schematic diagram that top-gated is defined using the hard mask plate of high-precision.
Figure label：1001 be substrate, and 1002 be two-dimensional semiconductor material, and 2001 be source-drain electrode, and 2002 be aluminium oxide
Protective layer, 3001 be electrolytic thin-membrane, and 4001 be the hard mask plate of high-precision.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar material or method with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.For simplification
Disclosure of the invention is hereinafter described the material of specific examples and method.Certainly, they are merely examples, and mesh
Do not lie in limitation the present invention.In addition, the present invention provides various specific techniques and material example, but this field is general
Logical technical staff can be appreciated that the applicable property of other techniques and/or the use of other materials.
Hereinafter, being directed to the one of the preparation method of magnesium-yttrium-transition metal compound film according to the present invention according to appended attached drawing
Example illustrates.
According to one embodiment of present invention, one is provided to prepare with top gate structure using electrolytic thin-membrane as dielectric
The method of the two-dimensional semiconductor transistor of layer.
The substrate 1001 covered by two-dimensional semiconductor material 1002 is shown in FIG. 1.Substrate 1001 can be this field
Common substrate, such as glass substrate, Sapphire Substrate, quartz substrate, silicon substrate, or flexible substrate is used so that flexible electrical is made
Road.Two-dimensional semiconductor material 1002 may be used the modes such as mechanical stripping, chemical vapor deposition and be formed.As specific an example,
It has selected silica as substrate 1001 in the present embodiment, the mode of mechanical stripping is used in combination to be prepared for molybdenum disulfide film 1002.
Fig. 2 shows source-drain electrodes 2001 and anticreep aluminum oxide protective layer 2002.Source-drain electrode 2001 can be Au,
The various common conductive metals such as Ag, Ti, Pt.Its forming process includes using photoetching definition region, then sputter or be deposited target gold
Belong to material to form electrode film.As specific an example, Ti/Au (5nm/30nm) is selected to be leaked as source electrode in the present embodiment
Pole metal 2001 selects electron beam evaporation plating 3nm metallic aluminiums and the mode of its autoxidation is allowed to form leakage protection layer 2002.
Fig. 3 shows the electrolytic thin-membrane 3001 to be formed.The mode that spin coating may be used in electrolytic thin-membrane 3001 prepares thickness
Spend controllable homogeneous electrolyte film.As specific an example, PEO/LiClO has been selected in the present embodiment4As electrolyte.System
Standby process includes selecting a certain proportion of PEO/LiClO4It is dissolved in methanol, and is put on magnetic stirring apparatus and it is allowed fully to dissolve.Electricity
It includes dropping in the electrolyte solution for being centainly dissolved in methanol to be covered by molybdenum disulfide 1002 to solve 3001 deposition process of matter film
Silicon oxide substrate 1001 on, then use glue spreader spin coating and bake 5 minutes at 70 DEG C to form electrolytic thin-membrane 3001.
Fig. 4 shows the preparation process of top-gated metal.The hard mask plate of high-precision may be used and define top-gated position, using steaming
The mode of plating or sputtering forms top-gated metal electrode.The hard mask of high-precision has first been used as specific an example, in the present embodiment
Version 4001 has defined top-gated region, then uses the mode of magnetron sputtering and deposited the gold electrode of 40nm as top-gated.
More than, for the present invention, a kind of high-performance two using polymer dielectric as dielectric layer with top gate structure
The process of dimension semiconductor transistor is explained in detail, but the present invention is not limited to above examples, are not departing from this
In the range of the main idea of invention, naturally it is also possible to carry out various improvement, deformation.
Claims (10)
1. a kind of method preparing the two-dimensional semiconductor transistor with top gate structure and polymer dielectric dielectric layer, is related to making
A series of standby stacked structures, it is substrate successively that the stacked structure is bottom-up, two-dimensional semiconductor material, serves as source electrode and drain electrode
Metal electrode material, spin coating formed polymer dielectric dielectric layer, serve as the metal electrode material of grid；Wherein, source electrode
There is one layer of alumina protective layer between the metal electrode material and dielectric layer of drain electrode；It is as follows：
（1）Two-dimensional semiconductor material layer is prepared on substrate；
（2）Metal electrode material is prepared in two-dimensional semiconductor material layer, as source electrode and drain electrode；
（3）One layer of aluminium oxide is prepared in the source electrode and drain electrode, as protective layer；
（4）The spin on polymers electrolyte in the structure handled through above-mentioned steps, to form polymer dielectric in homogeneous thickness
Medium layer film；
（5）On being formed by electrolytic thin-membrane, the gate electrode of transistor is made, which is the topological structure of top-gated.
2. according to the method described in claim 1, it is characterized in that, the substrate is glass substrate, Sapphire Substrate, quartz lining
Bottom, silicon substrate or flexible substrate, so that flexible circuit is made.
3. according to the method described in claim 1, it is characterized in that, step（3）The middle specific method for preparing aluminium oxide is：Vapor deposition
Metallic aluminium allows its autoxidation to obtain alumina layer；Or the shape of aluminium oxide is directly deposited directly by the way of atomic layer deposition
Formula obtains alumina layer.
4. method according to claim 1,2 or 3, which is characterized in that the thickness of the protective layer of alumina is received for 3-8
Rice.
5. method according to claim 1,2 or 3, which is characterized in that step（4）Middle formation polymer dielectric dielectric layer
Method be：The polymer dielectric is dissolved in methanol, the methanol solution of polymer dielectric is obtained, then uses spin coating
Solution is spun in two-dimensional semiconductor material layer by method, Evaporation of methanol, obtains polymer dielectric dielectric thin film layer.
6. according to the method described in claim 5, it is characterized in that, step（5）The middle method of gate electrode for making transistor is：
Top-gated position is defined with the hard mask plate of high-precision, top-gated metal electrode is formed by the way of vapor deposition or sputtering.
7. according to the method described in claim 1, it is characterized in that, the electrolytic polymer, by polymer and is dissolved in it
In Li salt composition.
8. the method according to the description of claim 7 is characterized in that the polymer is polyethylene oxide, the Li salt is height
The mass ratio of lithium chlorate, polyethylene oxide and lithium perchlorate is（7-10）:1.
9. according to the method described in claim 1,7 or 8, which is characterized in that the polymer electrolyte film thickness is 1 micro-
- 10 microns of rice.
10. the two-dimensional semiconductor field-effect transistor being prepared by the method described in claim 1-9 has top gate structure,
And using polymer dielectric as dielectric layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950321A (en) * | 2019-03-25 | 2019-06-28 | 暨南大学 | A kind of p type field effect transistor and preparation method thereof based on tungsten oxide |
| CN110112293A (en) * | 2019-04-03 | 2019-08-09 | 华东师范大学 | A kind of high molecular polymer thin film transistor (TFT) and preparation method thereof |
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| CN101022152A (en) * | 2007-03-20 | 2007-08-22 | 华南理工大学 | Polymer electrolytic thin film transistor |
| CN102217072A (en) * | 2008-09-19 | 2011-10-12 | 南洋理工大学 | Electronic device with channel, electrodes and semiconductor formed on respective bonded substrates |
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| CN109950321A (en) * | 2019-03-25 | 2019-06-28 | 暨南大学 | A kind of p type field effect transistor and preparation method thereof based on tungsten oxide |
| CN110112293A (en) * | 2019-04-03 | 2019-08-09 | 华东师范大学 | A kind of high molecular polymer thin film transistor (TFT) and preparation method thereof |
| CN110112293B (en) * | 2019-04-03 | 2020-10-16 | 华东师范大学 | High-molecular polymer thin film transistor and preparation method thereof |
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