CN108364601A - A kind of shift register, gate driving circuit and display device - Google Patents
A kind of shift register, gate driving circuit and display device Download PDFInfo
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- CN108364601A CN108364601A CN201810185522.1A CN201810185522A CN108364601A CN 108364601 A CN108364601 A CN 108364601A CN 201810185522 A CN201810185522 A CN 201810185522A CN 108364601 A CN108364601 A CN 108364601A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Computer Hardware Design (AREA)
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- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
A kind of shift register, gate driving circuit and display device provided in an embodiment of the present invention, wherein shift register include input module, node reset module, the first output module, the second output module, capacitance module, output reseting module and reset control module；Wherein, reset the current potential that control module is used to control second node, output reseting module is set to be resetted to second signal output module under the control of the current potential of second node, output reseting module is controlled by resetting control module, without being changed to output reseting module and the first output module, i.e. no need to increase the driving voltages of shift register has saved the energy to reduce the energy consumption of shift register.
Description
Technical field
The present invention relates to display technology field, espespecially a kind of shift register, gate driving circuit and display device.
Background technology
In panel display board, usually by each thin film transistor (TFT) from gate driving circuit to pixel region (TFT,
Thin Film Transistor) grid provide grid open signal.Gate driving circuit can be formed by array processes
In the array substrate of panel display board, i.e., array substrate row drives (Gate Driver on Array, GOA) technique, this
Kind integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in the both sides panel display board (Panel), together
When, it also eliminates the binding region (Bonding) of grid integrated circuits (IC, Integrated Circuit) and is fanned out to
(Fan-out) wiring space, so as to realize the design of narrow frame.
Gate driving circuit is made of multiple cascade shift registers cascades, shift registers at different levels be used for this
The grid line that the signal output end of grade shift register is connected provides grid open signal to open the pixel region of corresponding row
TFT.Shift register in the prior art is as shown in Figure 1, the first pole of third transistor M3 and the second reference voltage signal end
VREF2 is connected, wherein the second reference voltage signal end VREF2 provides high level for the first pole of third transistor M3, it is therefore, right
The reset of second signal output end OUTPUT2 fully relies on the 4th transistor M4 to complete, and the grid of the 4th transistor M4 with
First signal output end OUTPUT1 of next stage shift register is connected, in order to ensure the second signal of this grade of shift register
The rising time of output end OUTPUT2 institutes output signal in default range, need to increase simultaneously the 4th transistor M4 and
The size of 5th transistor M5, the power consumption of gate driving circuit will certainly be increased by increasing the size of the 5th transistor M5, cause to consume
The increase of energy.
Therefore, how in the case of the normal output and reset of second signal output end, reduce the energy of shift register
Consumption is those skilled in the art's technical problem urgently to be resolved hurrily.
Invention content
In view of this, a kind of shift register of offer of the embodiment of the present invention, gate driving circuit and display device, to solve
Since the size of transistor is larger in certainly existing shift register, the problem for causing the energy consumption of shift register larger.
A kind of shift register provided in an embodiment of the present invention, including：Input module, node reset module, the first output
Module, the second output module, capacitance module, output reseting module and reset control module；Wherein,
The input module by the signal at the input signal end under the control at input signal end for being supplied to first
Node；
The signal at the first reference signal end for being supplied to by the node reset module under the control at reset signal end
The first node；
First output module is used to believe the clock of clock signal terminal under the control of the current potential of the first node
Number it is supplied to the first signal output end；
Second output module is used for the second reference voltage signal end under the control of the current potential of the first node
Signal be supplied to second signal output end；
The capacitance module is used to keep the voltage stabilization of the first node and first signal output end；
The reset control module is used for first reference voltage signal end under the control of the clock signal terminal
Signal be supplied to second node；Or by second reference voltage signal under the control at second reference voltage signal end
The signal at end is supplied to the second node；
The output reseting module is used to believe first reference voltage under the control of the current potential of the second node
Number end signal be supplied to the second signal output end.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the input
Module includes：The first transistor；
The first of the grid of the first transistor and the first transistor is extremely connected with the input signal end, institute
The second pole for stating the first transistor is connected with the first node.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the node
Reseting module includes：Second transistor；
The grid of the second transistor is connected with the reset signal end, the first pole of the second transistor with it is described
First reference voltage signal end is connected, and the second pole of the second transistor is connected with the first node.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described first
Output module includes：5th transistor；
The grid of 5th transistor is connected with the first node, the first pole of the 5th transistor with it is described when
Clock signal end is connected, and the second pole of the 5th transistor is connected with first signal output end.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the capacitance
Module includes：First capacitance；
One end of first capacitance is connected with the first node, and the other end of first capacitance is believed with described first
Number output end is connected.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described second
Output module includes：Third transistor；
The grid of the third transistor is connected with the first node, the first pole of the third transistor and described the
Two reference voltage signal ends are connected, and the second pole of the third transistor is connected with the second signal output end.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the reset
Control module includes the 6th transistor and the 7th transistor；
The grid of 6th transistor and the first of the 6th transistor extremely with second reference voltage signal
End is connected, and the second pole of the 6th transistor is connected with the second node；
The grid of 7th transistor is connected with the clock signal terminal, the first pole of the 7th transistor with it is described
First reference voltage signal end is connected, and the second pole of the 7th transistor is connected with the second node.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the output
Reseting module includes：4th transistor；
The grid of 4th transistor is connected with the second node, the first pole of the 4th transistor and described the
One reference voltage signal end is connected, and the second pole of the 4th transistor is connected with the second signal output end.
Correspondingly, the embodiment of the present invention additionally provides a kind of gate driving circuit, including cascade multiple present invention are implemented
The above-mentioned shift register that example provides；Wherein,
In addition to first order shift register, remaining first signal output end per level-one shift register respectively with its phase
The reset signal end of adjacent upper level shift register is connected；
In addition to afterbody shift register, remaining first signal output end per level-one shift register respectively with its
The input signal end of adjacent next stage shift register is connected.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention provide it is any of the above-described
Kind gate driving circuit.
The present invention has the beneficial effect that：
Above-mentioned shift register, gate driving circuit and display device provided in an embodiment of the present invention, wherein shift LD
Device includes input module, node reset module, the first output module, the second output module, capacitance module, output reseting module
With reset control module；Wherein, the current potential that control module is used to control second node is resetted, makes output reseting module in the second section
Point current potential control under second signal output module is resetted, i.e., by reset control module to output reseting module into
Row control, without being changed to output reseting module and the first output module, i.e., no need to increase the drives of shift register
Dynamic voltage has saved the energy to reduce the energy consumption of shift register.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram for shift register that the prior art provides；
Fig. 2 is the structural schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 is one of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 4 is the two of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 5 is Fig. 3 and a kind of corresponding input and output sequential chart of shift register shown in Fig. 4.
Specific implementation mode
Below in conjunction with the accompanying drawings, to shift register provided in an embodiment of the present invention, gate driving circuit and display device
Specific implementation mode is described in detail.
A kind of shift register provided in an embodiment of the present invention, as shown in Fig. 2, including：Input module 1, node reset mould
Block 2, the first output module 3, the second output module 4, capacitance module 5, output reseting module 7 and reset control module 6；Wherein,
Input module 1 is used to that the signal of input signal end INPUT to be supplied to the under the control of input signal end INPUT
One node PU；
Node reset module 2 is used for the signal of the first reference signal end VREF1 under the control of reset signal end RESET
It is supplied to first node PU；
First output module 3 is used for the clock signal of clock signal terminal CLK under the control of the current potential of first node PU
It is supplied to the first signal output end OUTPUT1；
Second output module 4 is used for the second reference voltage signal end VREF2 under the control of the current potential of first node PU
Signal be supplied to second signal output end OUTPUT2；
Capacitance module 5 is used to keep the voltage stabilization of first node PU and the first signal output end OUTPUT1；
Control module 6 is resetted to be used for the letter of the first reference voltage signal end VREF1 under the control of clock signal terminal CLK
Number it is supplied to second node A；Or by the second reference voltage signal end under the control of the second reference voltage signal end VREF2
The signal of VREF2 is supplied to second node A；
Reseting module 7 is exported to be used for the first reference voltage signal end VREF1's under the control of the current potential of second node A
Signal is supplied to second signal output end OUTPUT2.
Above-mentioned shift register provided in an embodiment of the present invention includes input module, node reset module, the first output mould
Block, the second output module, capacitance module, output reseting module and reset control module；Wherein, control module is resetted for controlling
The current potential of second node makes output reseting module be answered second signal output module under the control of the current potential of second node
Position controls output reseting module by resetting control module, without to output reseting module and the first output
Module is changed, i.e., no need to increase the driving voltages of shift register, to reduce the energy consumption of shift register, is saved
The energy.
With reference to specific embodiment, the present invention is described in detail.It should be noted that the present embodiment is in order to more
The good explanation present invention, but do not limit the present invention.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, input module 1
Including：The first transistor M1；
The grid of the first transistor M1 and the first of the first transistor M1 is extremely connected with input signal end INPUT, and first
The second pole of transistor M1 is connected with first node PU.
It the above is only the concrete structure for illustrating input module in shift register, in the specific implementation, input module
Concrete structure be not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot
Structure does not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, node reset
Module 2 includes：Second transistor M2；
The grid of second transistor M2 is connected with reset signal end RESET, the first pole of second transistor M2 and the first ginseng
It examines voltage signal end VREF1 to be connected, the second pole of second transistor M2 is connected with first node PU.
It the above is only the concrete structure for illustrating shift register interior joint reseting module, in the specific implementation, node
The concrete structure of reseting module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the first output
Module 3 includes：5th transistor M5；
The grid of 5th transistor M5 is connected with first node PU, the first pole of the 5th transistor M5 and clock signal terminal
CLK is connected, and the second pole of the 5th transistor M5 is connected with the first signal output end OUTPUT1.
It the above is only the concrete structure for illustrating the first output module in shift register, in the specific implementation, first
The concrete structure of output module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, capacitance module 5
Including：First capacitance C1；
One end of first capacitance C1 is connected with first node PU, the other end and the first signal output end of the first capacitance C1
OUTPUT1 is connected.
It the above is only the concrete structure for illustrating capacitance module in shift register, in the specific implementation, capacitance module
Concrete structure be not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot
Structure does not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, the second output
Module 4 includes：Third transistor M3；
The grid of third transistor M3 is connected with first node PU, the first pole and the second reference voltage of third transistor M3
Signal end VREF2 is connected, and the second pole of third transistor M3 is connected with second signal output end OUTPUT2.
It the above is only the concrete structure for illustrating the second output module in shift register, in the specific implementation, second
The concrete structure of output module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, resetting control
Module 6 includes the 6th transistor M6 and the 7th transistor M7；
The grid of 6th transistor M6 and the first of the 6th transistor M6 extremely with the second reference voltage signal end VREF2 phases
Even, the second pole of the 6th transistor M6 is connected with second node A；
The grid of 7th transistor M7 is connected with clock signal terminal CLK, the first pole of the 7th transistor M7 and the first reference
Voltage signal end VREF1 is connected, and the second pole of the 7th transistor M7 is connected with second node A.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, when first node is low-voltage, third
Transistor cutoff, the 6th transistor is under the control at the second reference voltage signal end by second ginseng at the second reference voltage signal end
It examines voltage signal and is supplied to second node, wherein the second reference voltage signal is high voltage signal, the i.e. electricity of second node at this time
Pressure is high voltage, and first reference voltage signal at the first reference voltage signal end is supplied to second signal by the 4th transistor turns
Output end resets second signal output end；When first node is high voltage, third transistor and the 5th transistor are led
Logical, the first signal output end and second signal output end export high level signal, at this point, the clock signal of clock signal terminal
For high level signal, the 7th transistor is connected under control of the clock signal, and the voltage at the first reference voltage signal end is provided
To second node, the voltage of second node is low-voltage, and the 4th transistor is in cut-off state, cannot believe the first reference voltage
Number end signal be supplied to second signal output end, ensure that the stabilization of second signal output end institute output signal.
It the above is only the concrete structure for illustrating and resetting control module in shift register, in the specific implementation, reset
The concrete structure of control module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, output resets
Module 7 includes：4th transistor M4；
The grid of 4th transistor M4 is connected with second node A, the first pole and the first reference voltage of the 4th transistor M4
Signal end VREF1 is connected, and the second pole of the 4th transistor M4 is connected with second signal output end OUTPUT2.
It the above is only the concrete structure for illustrating and exporting reseting module in shift register, in the specific implementation, output
The concrete structure of reseting module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
It should be noted that above-described embodiment is illustrated using all transistors as N-type transistor, still,
In above-mentioned shift register provided in an embodiment of the present invention, in order to simplify manufacture craft, transistor generally uses same material
Transistor, therefore, all transistors are N-type transistor or are P-type transistor.In the specific implementation, when the grid of needs
When the current potential of pole open signal is high potential, all transistors are N-type transistor；When the current potential of the grid open signal of needs
For low potential when, all transistors are P-type transistor.
Further, in the specific implementation, N-type transistor is connected under high potential effect, ends under low potential effect；
P-type transistor ends under high potential effect, is connected under low potential effect.
It should be noted that the transistor mentioned in the above embodiment of the present invention is metal oxide semiconductor field-effect
It manages (MOS, Metal Oxide Semiconductor).In specific implementation, the extremely source electrode of the first of these transistors, second
It extremely drains or first extremely drains, the second extremely source electrode does not do specific differentiation herein.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, in addition to including above-described embodiment
In module except, as shown in figure 4, can also include node initial reset module 8, the first output end initial reset module 9, the
Two output end initial reset modules 10, pull-up module 11 and pull-down module 12, the concrete structure of above-mentioned module can make existing knot
Any one in structure is not limited in a kind of structure shown in Fig. 4, and this is no longer going to repeat them for concrete structure.
Combined circuit sequence diagram separately below makees the course of work of above-mentioned shift register provided in an embodiment of the present invention
With description.High potential signal is indicated with 1,0 indicates low-potential signal, wherein 1 and 0 is to high potential and low respectively in described below
The statement of current potential, it is not intended that the voltage of high potential is 1, the voltage of low potential is 0, the specific voltage of high potential and low potential
Value is selected according to actual conditions, is not limited thereto.
Embodiment
By taking shift register shown in Fig. 3 as an example, wherein the transistor in shift register shown in Fig. 3 is N-type crystalline substance
Body pipe, the first reference voltage signal end VREF1 are low potential, and the second reference voltage signal end VREF2 is high potential.Corresponding one
Kind input and output sequential chart is as shown in Figure 5.
In the t1 stages：CLK=0, INPUT=1, RESET=0.
The signal of input signal end INPUT makes the first transistor M1 be connected, and the signal of input signal end INPUT passes through first
Transistor M1 makes the current potential of first node PU draw high, first node PU control third transistor M3 and the 5th transistor M5 conductings,
At this point, the clock signal of clock signal terminal CLK is low level signal, and the 7th transistor M7 cut-offs, the second reference voltage signal end
The signal of VREF2 is high level, and the high potential of the second reference voltage signal end VREF2 is supplied to by the 6th transistor M6 conductings
The low potential of first reference voltage signal end VREF1 is supplied to second signal to export by second node A, the 4th transistor M4 conductings
OUTPUT2, the current potential of second signal output end OUTPUT2 is held to be pulled low.
In the t2 stages：CLK=1, INPUT=0, RESET=0.
At this point, the clock signal of clock signal terminal CLK is high level, due to the boot strap of the first capacitance C1, first segment
The current potential of point PU is raised again, the 5th transistor M5 and third transistor M3 conducting, the first signal output end OUTPUT1 and the
Binary signal output end OUTPUT2 exports the height electricity by clock signal terminal CLK and the second reference voltage signal end VREF2 offers respectively
Ordinary mail number, because clock signal terminal CLK is high level signal, the 7th transistor M7 conductings, the first reference voltage signal end VREF1
The low level signal of the first reference voltage signal end VREF1 is provided to second node A by the 7th transistor M7 of conducting, the 4th
Transistor M4 cut-offs, can not be supplied to second signal output end by the low level signal of the first reference voltage signal end VREF1
OUTPUT2, so that the signal that second signal output end OUTPUT2 is exported keeps stablizing.
In the t3 stages：CLK=0, INPUT=0, RESET=1.
At this point, reset signal end RESET=1, second transistor M2 conductings, by the first reference voltage signal end VREF1's
Low level signal is supplied to first node PU, to be resetted to first node PU.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driving circuit, including cascade multiple
Any of the above-described kind of shift register provided in an embodiment of the present invention：Wherein,
In addition to first order shift register, remaining first signal output end per level-one shift register respectively with its phase
The reset signal end of adjacent upper level shift register is connected；
In addition to afterbody shift register, remaining first signal output end per level-one shift register respectively with its
The input signal end of adjacent next stage shift register is connected.
It should be noted that the first signal output end in shift register be used for in gate driving circuit higher level or
Subordinate's shift register is cascaded, and second signal output end is used to provide control letter to the corresponding grid line of this grade of shift register
Number.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned gate driving
Circuit provides scanning signal by the gate driving circuit for each grid line in array substrate in display device.The display device
Can be：Mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator etc. are any to have display work(
The product or component of energy.The implementation of the display device may refer to the embodiment of above-mentioned gate driving circuit, repeat place no longer
It repeats.
Above-mentioned shift register, gate driving circuit and display device provided in an embodiment of the present invention, wherein shift LD
Device includes input module, node reset module, the first output module, the second output module, capacitance module, output reseting module
With reset control module；Wherein, the current potential that control module is used to control second node is resetted, makes output reseting module in the second section
Point current potential control under second signal output module is resetted, i.e., by reset control module to output reseting module into
Row control, without being changed to output reseting module and the first output module, i.e., no need to increase the drives of shift register
Dynamic voltage has saved the energy to reduce the energy consumption of shift register.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of shift register, which is characterized in that including：Input module, node reset module, the first output module, second
Output module, capacitance module, output reseting module and reset control module；Wherein,
The input module by the signal at the input signal end under the control at input signal end for being supplied to first node；
The node reset module is used under the control at reset signal end the signal at the first reference signal end being supplied to described
First node；
First output module is for putting forward the clock signal of clock signal terminal under the control of the current potential of the first node
Supply the first signal output end；
Second output module is used for the letter at the second reference voltage signal end under the control of the current potential of the first node
Number it is supplied to second signal output end；
The capacitance module is used to keep the voltage stabilization of the first node and first signal output end；
The reset control module is used for the letter at first reference voltage signal end under the control of the clock signal terminal
Number it is supplied to second node；Or by second reference voltage signal end under the control at second reference voltage signal end
Signal is supplied to the second node；
The output reseting module is used for first reference voltage signal end under the control of the current potential of the second node
Signal be supplied to the second signal output end.
2. shift register as described in claim 1, which is characterized in that the input module includes：The first transistor；
The first of the grid of the first transistor and the first transistor is extremely connected with the input signal end, and described
Second pole of one transistor is connected with the first node.
3. shift register as described in claim 1, which is characterized in that the node reset module includes：Second transistor；
The grid of the second transistor is connected with the reset signal end, the first pole of the second transistor and described first
Reference voltage signal end is connected, and the second pole of the second transistor is connected with the first node.
4. shift register as described in claim 1, which is characterized in that first output module includes：5th transistor；
The grid of 5th transistor is connected with the first node, and the first pole and the clock of the 5th transistor are believed
Number end be connected, the second pole of the 5th transistor is connected with first signal output end.
5. shift register as described in claim 1, which is characterized in that the capacitance module includes：First capacitance；
One end of first capacitance is connected with the first node, and the other end of first capacitance and first signal are defeated
Outlet is connected.
6. shift register as described in claim 1, which is characterized in that second output module includes：Third transistor；
The grid of the third transistor is connected with the first node, and the first pole of the third transistor is joined with described second
It examines voltage signal end to be connected, the second pole of the third transistor is connected with the second signal output end.
7. shift register as described in claim 1, which is characterized in that the reset control module include the 6th transistor and
7th transistor；
The grid of 6th transistor and the first of the 6th transistor extremely with second reference voltage signal end phase
Even, the second pole of the 6th transistor is connected with the second node；
The grid of 7th transistor is connected with the clock signal terminal, the first pole and described first of the 7th transistor
Reference voltage signal end is connected, and the second pole of the 7th transistor is connected with the second node.
8. shift register as described in claim 1, which is characterized in that the output reseting module includes：4th transistor；
The grid of 4th transistor is connected with the second node, and the first pole of the 4th transistor is joined with described first
It examines voltage signal end to be connected, the second pole of the 4th transistor is connected with the second signal output end.
9. a kind of gate driving circuit, which is characterized in that including cascade multiple as claim 1-8 any one of them shifts
Register；Wherein,
In addition to first order shift register, remaining distinguishes adjacent thereto per the first signal output end of level-one shift register
The reset signal end of upper level shift register is connected；
In addition to afterbody shift register, the first signal output end difference of remaining every level-one shift register is adjacent thereto
Next stage shift register input signal end be connected.
10. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 9.
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| CN201810185522.1A CN108364601B (en) | 2018-03-07 | 2018-03-07 | Shifting register, grid driving circuit and display device |
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| CN201810185522.1A CN108364601B (en) | 2018-03-07 | 2018-03-07 | Shifting register, grid driving circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| TWI742752B (en) * | 2020-07-07 | 2021-10-11 | 凌巨科技股份有限公司 | Gate driving circuit of display panel |
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| Publication number | Publication date |
|---|---|
| CN108364601B (en) | 2020-07-07 |
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