CN108364601B - Shifting register, grid driving circuit and display device - Google Patents
Shifting register, grid driving circuit and display device Download PDFInfo
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- CN108364601B CN108364601B CN201810185522.1A CN201810185522A CN108364601B CN 108364601 B CN108364601 B CN 108364601B CN 201810185522 A CN201810185522 A CN 201810185522A CN 108364601 B CN108364601 B CN 108364601B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The shift register, the gate driving circuit and the display device provided by the embodiment of the invention comprise an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; the reset control module is used for controlling the potential of the second node, so that the output reset module resets the second signal output module under the control of the potential of the second node, namely, the output reset module is controlled through the reset control module, the output reset module and the first output module are not required to be changed, the driving voltage of the shift register is not required to be increased, the energy consumption of the shift register is reduced, and the energy is saved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit and a display device.
Background
In a flat panel display panel, a gate-on signal is generally supplied to a gate of each Thin Film Transistor (TFT) of a pixel region through a gate driving circuit. The Gate driving Circuit may be formed on an Array substrate of the flat Panel display Panel through an Array process, i.e., a Gate Driver on Array (GOA) process, which not only saves cost, but also may achieve an aesthetic design of bilateral symmetry of the flat Panel display Panel (Panel), and simultaneously, may also save a Bonding area of the Gate Integrated Circuit (IC) and a wiring space of the Fan-out (Fan-out), thereby implementing a design of a narrow bezel.
The grid driving circuit is formed by cascading a plurality of cascaded shift registers, and each stage of shift register is used for providing a grid opening signal for a grid line connected with a signal output end of the stage of shift register so as to open the TFT of the pixel area of the corresponding row. In the shift register of the prior art, as shown in fig. 1, a first pole of a third transistor M3 is connected to a second reference voltage signal terminal VREF2, wherein the second reference voltage signal terminal VREF2 provides a high level for the first pole of the third transistor M3, so that resetting of the second signal OUTPUT terminal OUTPUT2 is completed completely by means of a fourth transistor M4, and a gate of a fourth transistor M4 is connected to the first signal OUTPUT terminal OUTPUT1 of the next stage of shift register, in order to ensure that a rising edge time of a signal OUTPUT by the second signal OUTPUT terminal OUTPUT2 of the present stage of shift register is within a preset range, sizes of the fourth transistor M4 and the fifth transistor M5 need to be increased at the same time, and increasing the size of the fifth transistor M5 inevitably increases power consumption of the gate driving circuit, resulting in increased energy consumption.
Therefore, how to reduce the power consumption of the shift register under the conditions of normal output and reset of the second signal output terminal is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of this, embodiments of the present invention provide a shift register, a gate driving circuit and a display device, so as to solve the problem of large power consumption of the shift register due to large size of transistors in the conventional shift register.
The shift register provided by the embodiment of the invention comprises: the system comprises an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; wherein the content of the first and second substances,
the input module is used for providing a signal of an input signal end to a first node under the control of the input signal end;
the node reset module is used for providing a signal of a first reference signal end to the first node under the control of a reset signal end;
the first output module is used for providing a clock signal of a clock signal end to a first signal output end under the control of the electric potential of the first node;
the second output module is used for providing a signal of a second reference voltage signal end to a second signal output end under the control of the potential of the first node;
the capacitance module is used for keeping the voltage of the first node and the voltage of the first signal output end stable;
the reset control module is used for providing a signal of the first reference voltage signal end to a second node under the control of the clock signal end; or the signal of the second reference voltage signal terminal is provided to the second node under the control of the second reference voltage signal terminal;
the output reset module is used for providing the signal of the first reference voltage signal end to the second signal output end under the control of the potential of the second node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module includes: a first transistor;
the grid electrode of the first transistor and the first pole of the first transistor are both connected with the input signal end, and the second pole of the first transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the node resetting module includes: a second transistor;
the grid electrode of the second transistor is connected with the reset signal end, the first pole of the second transistor is connected with the first reference voltage signal end, and the second pole of the second transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output module includes: a fifth transistor;
the grid electrode of the fifth transistor is connected with the first node, the first pole of the fifth transistor is connected with the clock signal end, and the second pole of the fifth transistor is connected with the first signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the capacitance module includes: a first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is connected with the first signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output module includes: a third transistor;
a gate of the third transistor is coupled to the first node, a first pole of the third transistor is coupled to the second reference voltage signal terminal, and a second pole of the third transistor is coupled to the second signal output terminal.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the reset control module includes a sixth transistor and a seventh transistor;
a gate of the sixth transistor and a first pole of the sixth transistor are both connected to the second reference voltage signal terminal, and a second pole of the sixth transistor is connected to the second node;
the gate of the seventh transistor is connected to the clock signal terminal, the first pole of the seventh transistor is connected to the first reference voltage signal terminal, and the second pole of the seventh transistor is connected to the second node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output reset module includes: a fourth transistor;
the grid electrode of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first reference voltage signal end, and the second pole of the fourth transistor is connected with the second signal output end.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein the content of the first and second substances,
except the first stage of shift register, the first signal output end of each stage of shift register is respectively connected with the reset signal end of the adjacent shift register of the previous stage;
except the last stage of shift register, the first signal output end of each stage of shift register is respectively connected with the input signal end of the next stage of shift register adjacent to the first signal output end of the last stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the gate driving circuits.
The invention has the following beneficial effects:
the shift register, the gate driving circuit and the display device provided by the embodiment of the invention are characterized in that the shift register comprises an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; the reset control module is used for controlling the potential of the second node, so that the output reset module resets the second signal output module under the control of the potential of the second node, namely, the output reset module is controlled through the reset control module, the output reset module and the first output module are not required to be changed, the driving voltage of the shift register is not required to be increased, the energy consumption of the shift register is reduced, and the energy is saved.
Drawings
Fig. 1 is a schematic structural diagram of a shift register provided in the prior art;
fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;
fig. 4 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 5 is a timing chart of input and output of the shift register shown in fig. 3 and 4.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driver circuit, and a display device according to embodiments of the present invention with reference to the accompanying drawings.
As shown in fig. 2, a shift register according to an embodiment of the present invention includes: the system comprises an input module 1, a node reset module 2, a first output module 3, a second output module 4, a capacitance module 5, an output reset module 7 and a reset control module 6; wherein the content of the first and second substances,
the INPUT module 1 is used for providing a signal of an INPUT signal terminal INPUT to a first node PU under the control of the INPUT signal terminal INPUT;
the node RESET module 2 is configured to provide a signal of a first reference signal terminal VREF1 to the first node PU under the control of a RESET signal terminal RESET;
the first OUTPUT module 3 is configured to provide the clock signal of the clock signal terminal CLK to the first signal OUTPUT terminal OUTPUT1 under the control of the potential of the first node PU;
the second OUTPUT module 4 is configured to provide the signal of the second reference voltage signal terminal VREF2 to the second signal OUTPUT terminal OUTPUT2 under the control of the potential of the first node PU;
the capacitance module 5 is used for keeping the voltages of the first node PU and the first signal OUTPUT terminal OUTPUT1 stable;
the reset control module 6 is configured to provide a signal of a first reference voltage signal terminal VREF1 to the second node a under the control of the clock signal terminal CLK; or the signal of the second reference voltage signal terminal VREF2 is provided to the second node a under the control of the second reference voltage signal terminal VREF 2;
the OUTPUT reset module 7 is configured to provide the signal of the first reference voltage signal terminal VREF1 to the second signal OUTPUT terminal OUTPUT2 under the control of the potential of the second node a.
The shift register provided by the embodiment of the invention comprises an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; the reset control module is used for controlling the potential of the second node, so that the output reset module resets the second signal output module under the control of the potential of the second node, namely, the output reset module is controlled through the reset control module, the output reset module and the first output module are not required to be changed, the driving voltage of the shift register is not required to be increased, the energy consumption of the shift register is reduced, and the energy is saved.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the input module 1 includes: a first transistor M1;
the gate of the first transistor M1 and a first pole of the first transistor M1 are both connected to the INPUT signal terminal INPUT, and a second pole of the first transistor M1 is connected to the first node PU.
The above is merely an example of the specific structure of the input module in the shift register, and in the specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the node resetting module 2 includes: a second transistor M2;
the gate of the second transistor M2 is connected to a RESET signal terminal RESET, the first pole of the second transistor M2 is connected to a first reference voltage signal terminal VREF1, and the second pole of the second transistor M2 is connected to the first node PU.
The above is merely an example of the specific structure of the node reset module in the shift register, and in the specific implementation, the specific structure of the node reset module is not limited to the above structure provided in the embodiment of the present invention, and may also be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the first output module 3 includes: a fifth transistor M5;
a gate of the fifth transistor M5 is connected to the first node PU, a first pole of the fifth transistor M5 is connected to the clock signal terminal CLK, and a second pole of the fifth transistor M5 is connected to the first signal OUTPUT terminal OUTPUT 1.
The above is merely an example of the specific structure of the first output module in the shift register, and in the specific implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the capacitor module 5 includes: a first capacitance C1;
one terminal of the first capacitor C1 is connected to the first node PU, and the other terminal of the first capacitor C1 is connected to the first signal OUTPUT terminal OUTPUT 1.
The above is merely an example of the specific structure of the capacitor module in the shift register, and in the specific implementation, the specific structure of the capacitor module is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the second output module 4 includes: a third transistor M3;
a gate of the third transistor M3 is coupled to the first node PU, a first pole of the third transistor M3 is coupled to the second reference voltage signal terminal VREF2, and a second pole of the third transistor M3 is coupled to the second signal OUTPUT terminal OUTPUT 2.
The above is merely to illustrate a specific structure of the second output module in the shift register, and in a specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the reset control module 6 includes a sixth transistor M6 and a seventh transistor M7;
a gate of the sixth transistor M6 and a first pole of the sixth transistor M6 are both connected to the second reference voltage signal terminal VREF2, and a second pole of the sixth transistor M6 is connected to the second node a;
the gate of the seventh transistor M7 is connected to the clock signal terminal CLK, the first pole of the seventh transistor M7 is connected to the first reference voltage signal terminal VREF1, and the second pole of the seventh transistor M7 is connected to the second node a.
Specifically, in the shift register provided in the embodiment of the present invention, when the first node is at a low voltage, the third transistor is turned off, the sixth transistor provides the second reference voltage signal of the second reference voltage signal terminal to the second node under the control of the second reference voltage signal terminal, where the second reference voltage signal is a high voltage signal, that is, the voltage of the second node is at a high voltage, and the fourth transistor is turned on to provide the first reference voltage signal of the first reference voltage signal terminal to the second signal output terminal, so as to reset the second signal output terminal; when the first node is high voltage, the third transistor and the fifth transistor are turned on, the first signal output end and the second signal output end both output high level signals, at the moment, the clock signal of the clock signal end is also high level signals, the seventh transistor is turned on under the control of the clock signal, the voltage of the first reference voltage signal end is provided for the second node, the voltage of the second node is low voltage, the fourth transistor is in a cut-off state, the signal of the first reference voltage signal end cannot be provided for the second signal output end, and the stability of the signal output by the second signal output end is ensured.
The above is only an example of the specific structure of the reset control module in the shift register, and in the specific implementation, the specific structure of the reset control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the output reset module 7 includes: a fourth transistor M4;
the gate of the fourth transistor M4 is connected to the second node a, the first pole of the fourth transistor M4 is connected to the first reference voltage signal terminal VREF1, and the second pole of the fourth transistor M4 is connected to the second signal OUTPUT terminal OUTPUT 2.
The above is merely an example of the specific structure of the output reset module in the shift register, and in the specific implementation, the specific structure of the output reset module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In the shift register according to the embodiment of the present invention, all transistors are N-type transistors, but in order to simplify the manufacturing process, the transistors are generally made of the same material, and therefore all transistors are N-type transistors or P-type transistors. In specific implementation, when the electric potential of the required grid opening signal is high electric potential, all the transistors are N-type transistors; when the required grid opening signal is at low potential, all the transistors are P-type transistors.
Furthermore, in specific implementation, the N-type transistor is turned on under the action of high potential and is turned off under the action of low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.
It should be noted that the transistors mentioned in the above embodiments of the present invention are all Metal Oxide Semiconductor field effect transistors (MOS). In an implementation, the first electrodes of the transistors are the source electrodes and the second electrodes are the drain electrodes, or the first electrodes are the drain electrodes and the second electrodes are the source electrodes, which are not specifically distinguished here.
In specific implementation, in the shift register provided in the embodiment of the present invention, in addition to the modules in the above embodiment, as shown in fig. 4, the shift register may further include a node initial reset module 8, a first output end initial reset module 9, a second output end initial reset module 10, a pull-up module 11, and a pull-down module 12, where a specific structure of the above modules may be any one of existing structures, and is not limited to the structure shown in fig. 4, and specific structures are not described herein again.
The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram. In the following description, 1 denotes a high potential signal, 0 denotes a low potential signal, where 1 and 0 are expressions of a high potential and a low potential, respectively, but do not denote that a voltage of the high potential is 1, a voltage of the low potential is 0, and specific voltage values of the high potential and the low potential are selected according to actual situations, and are not limited herein.
Examples
Taking the shift register shown in fig. 3 as an example, wherein the transistors in the shift register shown in fig. 3 are all N-type transistors, the first reference voltage signal terminal VREF1 is at a low potential, and the second reference voltage signal terminal VREF2 is at a high potential. A corresponding input/output timing diagram is shown in fig. 5.
At stage t 1: CLK is 0, INPUT is 1, and RESET is 0.
The signal of the INPUT signal terminal INPUT turns on the first transistor M1, the signal of the INPUT signal terminal INPUT turns on the potential of the first node PU through the first transistor M1, the first node PU controls the third transistor M3 and the fifth transistor M5 to be turned on, at this time, the clock signal of the clock signal terminal CLK is a low level signal, the seventh transistor M7 is turned off, the signal of the second reference voltage signal terminal VREF2 is a high level, the sixth transistor M6 is turned on, the high level of the second reference voltage signal terminal VREF2 is provided to the second node a, the fourth transistor M4 is turned on, the low level of the first reference voltage signal terminal VREF1 is provided to the second signal OUTPUT terminal OUTPUT2, and the potential of the second signal OUTPUT terminal OUTPUT2 is turned off.
At stage t 2: CLK is 1, INPUT is 0, and RESET is 0.
At this time, the clock signal of the clock signal terminal CLK is at a high level, the potential of the first node PU is pulled high again due to the bootstrap action of the first capacitor C1, the fifth transistor M5 and the third transistor M3 are turned on, the first signal OUTPUT terminal OUTPUT1 and the second signal OUTPUT terminal OUTPUT2 OUTPUT high level signals provided by the clock signal terminal CLK and the second reference voltage signal terminal 2, respectively, because the clock signal terminal CLK is a high level signal, the seventh transistor M7 is turned on, the first reference voltage signal terminal VREF1 provides a low level signal of the first reference voltage signal terminal VREF1 to the second node a through the turned-on seventh transistor M7, the fourth transistor M4 is turned off, and a low level signal of the first reference voltage signal terminal VREF1 cannot be provided to the second signal OUTPUT terminal OUTPUT2, so that the signal OUTPUT by the second signal OUTPUT terminal OUTPUT2 is kept stable.
At stage t 3: CLK is 0, INPUT is 0, and RESET is 1.
At this time, the RESET signal terminal RESET is 1, the second transistor M2 is turned on, and a low level signal of the first reference voltage signal terminal VREF1 is supplied to the first node PU to RESET the first node PU.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, including a plurality of cascaded shift registers of any one of the shift registers provided by the embodiments of the present invention: wherein the content of the first and second substances,
except the first stage of shift register, the first signal output end of each stage of shift register is respectively connected with the reset signal end of the adjacent shift register of the previous stage;
except the last stage of shift register, the first signal output end of each stage of shift register is respectively connected with the input signal end of the next stage of shift register adjacent to the first signal output end of the last stage of shift register.
It should be noted that the first signal output end in the shift register is used for being cascaded with an upper stage or a lower stage shift register in the gate driving circuit, and the second signal output end is used for providing a control signal to a gate line corresponding to the shift register of the stage.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the gate driving circuit, where the gate driving circuit provides a scan signal for each gate line on an array substrate in the display device. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.
The shift register, the gate driving circuit and the display device provided by the embodiment of the invention are characterized in that the shift register comprises an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; the reset control module is used for controlling the potential of the second node, so that the output reset module resets the second signal output module under the control of the potential of the second node, namely, the output reset module is controlled through the reset control module, the output reset module and the first output module are not required to be changed, the driving voltage of the shift register is not required to be increased, the energy consumption of the shift register is reduced, and the energy is saved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A shift register, comprising: the system comprises an input module, a node reset module, a first output module, a second output module, a capacitor module, an output reset module and a reset control module; wherein the content of the first and second substances,
the input module is used for providing a signal of an input signal end to a first node under the control of the input signal end;
the node reset module is used for providing a signal of a first reference signal end to the first node under the control of a reset signal end;
the first output module is used for providing a clock signal of a clock signal end to a first signal output end under the control of the electric potential of the first node;
the second output module is used for providing a signal of a second reference voltage signal end to a second signal output end under the control of the potential of the first node;
the capacitance module is used for keeping the voltage of the first node and the voltage of the first signal output end stable;
the reset control module is used for providing a signal of the first reference voltage signal end to a second node under the control of the clock signal end; or the signal of the second reference voltage signal terminal is provided to the second node under the control of the second reference voltage signal terminal;
the output reset module is used for providing a signal of the first reference voltage signal end to the second signal output end under the control of the potential of the second node;
the reset control module comprises a sixth transistor and a seventh transistor;
a gate of the sixth transistor and a first pole of the sixth transistor are both connected to the second reference voltage signal terminal, and a second pole of the sixth transistor is connected to the second node;
the gate of the seventh transistor is connected to the clock signal terminal, the first pole of the seventh transistor is connected to the first reference voltage signal terminal, and the second pole of the seventh transistor is connected to the second node.
2. The shift register of claim 1, wherein the input module comprises: a first transistor;
the grid electrode of the first transistor and the first pole of the first transistor are both connected with the input signal end, and the second pole of the first transistor is connected with the first node.
3. The shift register of claim 1, wherein the node reset module comprises: a second transistor;
the grid electrode of the second transistor is connected with the reset signal end, the first pole of the second transistor is connected with the first reference voltage signal end, and the second pole of the second transistor is connected with the first node.
4. The shift register of claim 1, wherein the first output module comprises: a fifth transistor;
the grid electrode of the fifth transistor is connected with the first node, the first pole of the fifth transistor is connected with the clock signal end, and the second pole of the fifth transistor is connected with the first signal output end.
5. The shift register of claim 1, wherein the capacitance module comprises: a first capacitor;
one end of the first capacitor is connected with the first node, and the other end of the first capacitor is connected with the first signal output end.
6. The shift register of claim 1, wherein the second output module comprises: a third transistor;
a gate of the third transistor is coupled to the first node, a first pole of the third transistor is coupled to the second reference voltage signal terminal, and a second pole of the third transistor is coupled to the second signal output terminal.
7. The shift register of claim 1, wherein the output reset module comprises: a fourth transistor;
the grid electrode of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first reference voltage signal end, and the second pole of the fourth transistor is connected with the second signal output end.
8. A gate drive circuit comprising a plurality of shift registers according to any one of claims 1 to 7 in cascade; wherein the content of the first and second substances,
except the first stage of shift register, the first signal output end of each stage of shift register is respectively connected with the reset signal end of the adjacent shift register of the previous stage;
except the last stage of shift register, the first signal output end of each stage of shift register is respectively connected with the input signal end of the next stage of shift register adjacent to the first signal output end of the last stage of shift register.
9. A display device comprising the gate driver circuit according to claim 8.
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| TWI742752B (en) * | 2020-07-07 | 2021-10-11 | 凌巨科技股份有限公司 | Gate driving circuit of display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
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| CN105225635A (en) * | 2015-10-20 | 2016-01-06 | 信利（惠州）智能显示有限公司 | Array base palte horizontal drive circuit, shift register, array base palte and display |
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| CN107633799A (en) * | 2017-10-13 | 2018-01-26 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display device |
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| CN102783030B (en) * | 2010-03-02 | 2016-01-13 | 株式会社半导体能源研究所 | Output of pulse signal circuit and shift register |
| JP5436324B2 (en) * | 2010-05-10 | 2014-03-05 | 三菱電機株式会社 | Shift register circuit |
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| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| CN105206234A (en) * | 2015-09-17 | 2015-12-30 | 京东方科技集团股份有限公司 | Shift register unit, grid drive method, circuit and grid drive device |
| CN106601192A (en) * | 2015-10-16 | 2017-04-26 | 三星显示有限公司 | Gate driver and display device having the same |
| CN105225635A (en) * | 2015-10-20 | 2016-01-06 | 信利（惠州）智能显示有限公司 | Array base palte horizontal drive circuit, shift register, array base palte and display |
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| CN106023943A (en) * | 2016-08-02 | 2016-10-12 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof, grid drive circuit and display device |
| CN107633799A (en) * | 2017-10-13 | 2018-01-26 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display device |
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| CN108364601A (en) | 2018-08-03 |
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