CN108461062A - A kind of shift register, array substrate and its driving method, display device - Google Patents
A kind of shift register, array substrate and its driving method, display device Download PDFInfo
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- CN108461062A CN108461062A CN201810272167.1A CN201810272167A CN108461062A CN 108461062 A CN108461062 A CN 108461062A CN 201810272167 A CN201810272167 A CN 201810272167A CN 108461062 A CN108461062 A CN 108461062A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a kind of shift register, array substrate and its driving method, display device, which includes：Shift LD module, the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor and the 6th transistor；Under the control at first control signal end and second control signal end, second signal output end is made to export gated sweep signal, or two output end of signal is made to export gate off signal.When grid line of the second signal output end in array substrate exports gated sweep signal, the corresponding display area of the grid line is normally refreshed；When grid line of the second signal output end in array substrate exports gate off signal, the corresponding display area of the grid line is without refreshing.Display panel can be made to carry out local display by this kind setting, to achieve the purpose that reduce display panel power consumption.
Description
Technical field
The present invention relates to display technology field, espespecially a kind of shift register, array substrate and its driving method, display dress
It sets.
Background technology
In panel display board, usually by each thin film transistor (TFT) from gate driving circuit to pixel region (TFT,
Thin Film Transistor) grid provide grid open signal.Gate driving circuit can be formed by array processes
In the array substrate of panel display board, i.e., array substrate row drives (Gate Driver on Array, GOA) technique, this
Kind integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in the both sides panel display board (Panel), together
When, it also eliminates the binding region (Bonding) of grid integrated circuits (IC, Integrated Circuit) and is fanned out to
(Fan-out) wiring space, so as to realize the design of narrow frame.
Gate driving circuit in the related technology is made of multiple cascade shift register cascades, shift LDs at different levels
Device is used to provide grid open signal to the grid line being connected with the signal output end of this grade of shift register to open corresponding row
The TFT of pixel region.Wherein, in addition to first order shift register, the input signal end of remaining shift register at different levels is distinguished
It is connected with the signal output end of upper level shift register.But this kind setting only needs to carry out local display in display panel
When, it can not be only to the part grid line output control signal being arranged in array substrate, it still can be step by step in array substrate
Every grid line output control signal, makes the power consumption of display panel entirety that can greatly increase in this way.
Therefore, the local display for how realizing display panel, the power consumption to save display panel are one urgently to be resolved hurrily
The problem of.
Invention content
A kind of shift register of offer of the embodiment of the present invention, array substrate and its driving method, display device, to realize
The local display of display panel, to reduce the power consumption of display panel.
A kind of shift register provided in an embodiment of the present invention, including：Shift LD module, the first transistor, the second crystalline substance
Body pipe, third transistor, the 4th transistor, the 5th transistor and the 6th transistor；Wherein,
The shift LD module is used at the first clock signal terminal, second clock signal end, input signal end and first
The signal of first clock signal terminal is supplied to the first pole of the first transistor, by under the control at reference voltage signal end
The signal of two clock signal terminals is supplied to the first signal output end；
The first transistor is used for the first pole of the first transistor under the control at first control signal end
Signal is supplied to the grid of the 5th transistor；
The second transistor is used for first signal output end under the control at the first control signal end
Signal is supplied to the grid of the 6th transistor；
The third transistor is used for the signal at third reference voltage signal end under the control at second control signal end
It is supplied to the grid of the 6th transistor；
4th transistor is used for the second reference voltage signal end under the control at the second control signal end
Signal is supplied to the grid of the 5th transistor；
5th transistor be used for the second pole of the first transistor voltage or the 4th transistor the
The signal at third reference voltage signal end is supplied to second signal output end under the control of the voltage of two poles；
6th transistor be used for the second pole of the second transistor voltage or the third transistor the
The signal at second reference voltage signal end is supplied to second signal output end under the control of the voltage of two poles.
On the other hand, the embodiment of the present invention additionally provides a kind of array substrate, including cascade multiple such as above-described embodiment
The shift register and grid line；
In addition to afterbody shift register, remaining first signal output end per level-one shift register respectively with its
The input signal end of adjacent next stage shift register is connected；
The second signal output end of the shift register is connected with the grid line.
On the other hand, the embodiment of the present invention additionally provides a kind of driving method for the array substrate that above-described embodiment provides,
Including：
Obtain the image to be displayed in a frame time；
Judge that image to be displayed described in this frame whether there is identical image with previous frame image；
The image to be displayed described in this frame exists with previous frame image when differing image, corresponding according to image is differed
Time needed for the grid line scanning in region, determine the time that the first signal is inputted to the first control signal end, and to institute
State the time of second control signal end input second signal；
The image to be displayed described in this frame and previous frame image are there are when identical image, according to identical described in this frame image
The corresponding region of image grid line scanning needed for time, determine to the first control signal end input second signal when
Between, and to the second control signal end input the first signal time.
On the other hand, the embodiment of the present invention additionally provides a kind of display device, including：It is provided in an embodiment of the present invention above-mentioned
Array substrate.
The present invention has the beneficial effect that：
A kind of shift register, array substrate and its driving method provided in an embodiment of the present invention, display device, the displacement
Register includes：Shift LD module, the first transistor, second transistor, third transistor, the 4th transistor, the 5th crystal
Pipe and the 6th transistor；By the mutual cooperation of above-mentioned shift LD module and each transistor, at first control signal end and
Under the control of two control signal ends, second signal output end is made to export gated sweep signal, or two output end of signal is made to export
Gate off signal.When grid line of the second signal output end in array substrate exports gated sweep signal, which corresponds to
Display area normally refreshed；When grid line of the second signal output end in array substrate exports gate off signal
When, the corresponding display area of the grid line is without refreshing.Display panel can be made to carry out local display by this kind setting, to reach
To the purpose for reducing display panel power consumption.
Description of the drawings
Fig. 1 is the structural schematic diagram of gate driving circuit in the related technology；
Fig. 2 is a kind of structural schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another shift register provided in an embodiment of the present invention；
Fig. 4 is the corresponding a kind of sequence diagram of shift register provided in Fig. 3；
Fig. 5 is the corresponding another sequence diagram of shift register provided in Fig. 3；
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 7 is the flow chart of the driving method of array substrate provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of display device provided in an embodiment of the present invention.
Specific implementation mode
As shown in FIG. 1, FIG. 1 is the structural schematic diagrams of gate driving circuit in the related technology, grid in the related technology
Driving circuit, including cascade multiple shift registers：SR (1), SR (2) ... SR (n) ... SR (N-1), SR (N) (N number of displacements altogether
Register, 1≤n≤N)；Wherein, in addition to first order shift register SR (1), remaining every level-one shift register SR's (n)
The reset signal end reset that signal output end output distinguishes upper level shift register SR (n-1) adjacent thereto is connected；It removes
Except afterbody shift register SR (N), remaining per level-one shift register SR (n) signal output end output respectively with
The input signal end input of its adjacent next stage shift register SR (n+1) is connected.The setting of this kind of gate driving circuit is every
Grade shift register sends gated sweep signal to corresponding grid line, i.e., can only be carried out when display panel is shown complete
Screen display, and the regional area of display panel cannot only be made to be shown, but be not every when display panel is shown
One frame is required for all refreshing the whole region of display panel, the refreshing of regional area can be only carried out, to reduce display
The power consumption of panel.
In view of this, an embodiment of the present invention provides a kind of shift register, array substrate and its driving method, display dresses
It sets, to reduce the energy consumption of display panel.
In order to make the purpose of the present invention, technical solution and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention
Shift register, array substrate and its driving method of offer, the specific implementation mode of display device are described in detail.It answers
Work as understanding, preferred embodiment disclosed below is only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.And
In the case of not conflicting, the features in the embodiments and the embodiments of the present application can be combined with each other.
Obviously, described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, all other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.The shapes and sizes of each component do not reflect that actual proportions, purpose are only illustrated in attached drawing
Illustrate the content of present invention.
Specifically, an embodiment of the present invention provides a kind of shift registers, as shown in Fig. 2, Fig. 2 carries for the embodiment of the present invention
A kind of structural schematic diagram of the shift register supplied；The shift register includes：Shift LD module, the first transistor M1,
Two-transistor M2, third transistor M3, the 4th transistor M4, the 5th transistor M5 and the 6th transistor M6；Wherein,
Shift LD module is used at the first clock signal terminal CLK, second clock signal end CLKB, input signal end
The signal of the first clock signal terminal CLK is supplied to first crystal under the control of INPUT and the first reference voltage signal end VREF1
The signal of second clock signal end CLKB is supplied to the first signal output end OUTPUT1 by the first pole of pipe M1；
The first transistor M1 is used for the letter of the first pole of the first transistor M1 under the control of first control signal end PW1
Number it is supplied to the grid of the 5th transistor M5；
Second transistor M2 is used for the first signal output end OUTPUT1's under the control of first control signal end PW1
Signal is supplied to the grid of the 6th transistor M6；
Third transistor M3 is used for third reference voltage signal end VREF3 under the control of second control signal end PW2
Signal be supplied to the grid of the 6th transistor M6；
4th transistor M4 is used for the second reference voltage signal end VREF2 under the control of second control signal end PW2
Signal be supplied to the grid of the 5th transistor M5；
5th transistor M5 is used in the second pole of the voltage or the 4th transistor M4 of the second pole of the first transistor M1
The signal of third reference voltage signal end VREF3 is supplied to second signal output end OUTPUT2 under the control of voltage；
6th transistor M6 is used in the second pole of the voltage or third transistor M3 of the second pole of second transistor M2
The signal of the second reference voltage signal end VREF2 is supplied to second signal output end OUTPUT2 under the control of voltage.
A kind of shift register provided in an embodiment of the present invention includes：Shift LD module, the first transistor, the second crystal
Pipe, third transistor, the 4th transistor, the 5th transistor and the 6th transistor；Pass through above-mentioned shift LD module and each crystal
The mutual cooperation of pipe makes second signal output end export grid under the control at first control signal end and second control signal end
Pole scanning signal, or two output end of signal is made to export gate off signal.When second signal output end is in array substrate
When grid line exports gated sweep signal, the corresponding display area of the grid line is normally refreshed；When second signal output end to
When grid line in array substrate exports gate off signal, the corresponding display area of the grid line is without refreshing.It is set by this kind
Setting can make display panel carry out local display, to achieve the purpose that reduce display panel power consumption.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 2, with all transistors
It is P-type transistor, the second reference voltage signal end VREF2 is low level signal, and third reference voltage signal end VREF3 is height
It is illustrated for level signal, when the signal that first control signal end PW1 is provided is low level signal, second control signal end
When the signal that PW2 is provided is high level signal, the first transistor M1 and second transistor M2 conductings, third transistor M3 and the 4th
Transistor M4 cut-offs, at this point, the grid potential of the 6th transistor M6 is consistent with the current potential of the first signal output end OUTPUT1, the
The current potential of the grid of five transistor M5 is consistent with the current potential of second node N2, i.e., the current potential of second node N2 is with fourth node N4's
Current potential is consistent.When the current potential of the first signal output end OUTPUT1 is low level, the current potential of second node N2 is high level, the 6th
Transistor M6 conducting, the 5th transistor M5 cut-offs, at this point, the current potential of the second reference voltage signal end VREF2 pass through conducting the
Six transistor M2 are supplied to second signal output end OUTPUT2；When the current potential of the first signal output end OUTPUT1 is high level
The current potential of second node N2 is low level, the 6th transistor M6 cut-offs, the 5th transistor M5 conductings, at this point, third reference voltage
The current potential of signal end VRFE3 is supplied to second signal output end OUTPUT2, i.e. second signal by the 5th transistor M5 of conducting
Output end OUTPUT2 can correspond to grid line to it and export normal gate scanning signal.
When the signal that first control signal end PW1 is provided is high level signal, the signal that second control signal end PW2 is provided
For low level signal when, the first transistor M1 and second transistor M2 cut-off, third transistor M3 and the 4th transistor M4 conductings,
Third reference voltage signal VREF3 is supplied to third node N3, the 6th transistor M6 cut-offs by third transistor M3 conductings；4th
The voltage of second reference voltage signal end VREF2 is supplied to fourth node N4 by transistor M4 conducting, the 5th transistor M5 conductings,
To be supplied to second signal output end OUTPUT2, i.e. second signal to export the voltage of third reference voltage signal end VREF3
End OUTPUT2 unanimously exports high level, and high level is gate off signal at this time, cannot make the crystalline substance that grid line connects in array substrate
Body pipe is opened.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid of the first transistor M1 and first
Control signal end be connected, the first pole of the first transistor M1 is connected with shift LD module, the second pole of the first transistor M1 and
The grid of 5th transistor M5 is connected.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid of second transistor M2 and first
Control signal end is connected, and the first pole of second transistor M2 is connected with the first signal output end, the second pole of second transistor M2
It is connected with the grid of the 6th transistor M6.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid of third transistor M3 and second
Control signal end is connected, and the first pole of third transistor M3 is connected with third reference voltage signal end, and the of third transistor M3
Two poles are connected with the grid of the 6th transistor M6.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid and second of the 4th transistor M4
Control signal end is connected, and the first pole of the 4th transistor M4 is connected with the second reference voltage signal end, and the of the 4th transistor M4
Two poles are connected with the grid of the 5th transistor M5.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid of the 5th transistor M5 difference the
The second pole of four transistor M4 is extremely connected with the second of the first transistor M1, the first pole and the third reference electricity of the 5th transistor M5
Signal end is pressed to be connected, the second pole of the 5th transistor M5 is connected with second signal output end.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the grid of the 6th transistor M6 difference the
The second pole of two-transistor M2 is extremely connected with the second of third transistor M3, and the first pole of the 6th transistor M6 is with second with reference to electricity
Signal end is pressed to be connected, the second pole of the 6th transistor M6 is connected with second signal output end.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in figure 3, shift LD module packet
It includes：7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor M11, the tenth
Two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the first capacitance C1 and the second capacitance C2；
The grid of 7th transistor M7 is connected with the first clock signal terminal CLK, the first pole and the input of the 7th transistor M7
Signal end INPUT is connected, and the second pole of the 7th transistor M7 is extremely connected with the first of the 11st transistor M11；
The grid of 8th transistor M8 is connected with the first clock signal terminal CLK, the first pole and first of the 8th transistor M8
Reference voltage signal end VREF1 is connected, the second pole of the 8th transistor M8 respectively with the tenth two-transistor M12 and the 14th crystal
The grid of pipe M14 is connected；
The grid of 9th transistor M9 is connected with the first reference voltage signal end VREF1, the first pole of the 9th transistor M9
Extremely it is connected with the second of the 7th transistor M7, the second pole of the 9th transistor M9 is connected with the grid of the 13rd transistor M13；
The grid of tenth transistor M10 is extremely connected with the first of the 9th transistor M9, the first pole of the tenth transistor M10 with
First clock signal terminal CLK is connected, and the second pole of the tenth transistor M10 is connected with the grid of the tenth two-transistor M12；
The grid of 11st transistor M11 is connected with second clock signal end CLKB, the second pole of the 11st transistor M11
Extremely it is connected with the first of the tenth two-transistor M12；
The second pole of tenth two-transistor M12 is connected with third reference voltage signal end VREF3；
The first pole of 13rd transistor M13 is connected with second clock signal end CLKB, and the second of the 13rd transistor M13
Pole is connected with the first signal output end OUTPUT1；
14th the first poles transistor M14 are connected with the first signal output end OUTPUT1, the 14th transistor M14 second
Pole is connected with third reference voltage signal end VREF3；
One end of first capacitance C1 is connected with the grid of the 13rd transistor M13, the other end and first of the first capacitance C1
Signal output end OUTPUT1 is connected；
One end of second capacitance C2 is connected with the grid of the 14th transistor M14, the other end and first of the second capacitance C2
The first of transistor M1 is extremely connected.
It the above is only the concrete structure for illustrating shift LD module in shift register, in the specific implementation, displacement
The concrete structure of registration module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that
Other structures, do not limit herein.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, in order to simplify manufacture craft, transistor one
As be all made of the transistor of same material, therefore, all transistors are N-type transistor or P-type transistor.It is being embodied
When, when the current potential of the grid open signal of needs is high potential, all transistors are N-type transistor；When the grid of needs
When the current potential of open signal is low potential, all transistors are P-type transistor.
Further, in the specific implementation, N-type transistor is connected under high potential effect, ends under low potential effect；
P-type transistor ends under high potential effect, is connected under low potential effect.
It should be noted that the transistor mentioned in the above embodiment of the present invention is metal oxide semiconductor field-effect
It manages (MOS, Metal Oxide Scmiconductor).In specific implementation, the extremely source electrode of the first of these transistors, second
It extremely drains or first extremely drains, the second extremely source electrode does not do specific differentiation herein.
Combined circuit sequence diagram separately below makees the course of work of above-mentioned shift register provided in an embodiment of the present invention
With description.High potential signal is indicated with 1,0 indicates low-potential signal in described below.
Embodiment one
By taking shift register shown in Fig. 3 as an example, wherein transistor is P-type crystal in shift register shown in Fig. 3
Pipe, the first reference voltage signal end VREF1 are low potential, and third reference signal end VREF3 is high potential.In corresponding one kind
The sequence diagram for stating shift register is as shown in Figure 4.
In the t1 stages, INPUT=0, CLK=0, CLKB=1, PW1=1, PW2=0.
The signal of first clock signal terminal CLK makes the 7th transistor M7 conductings, and the signal of input signal end INPUT is distinguished
It is supplied to the grid of the first pole and the tenth transistor M10 of the 9th transistor M9, due to the first reference voltage signal end VREF1's
Voltage is low potential, and the 9th transistor M9 conductings, it is low level to make the current potential of first node N1, and the tenth transistor M10 conductings will
The signal of first clock signal terminal CLK is supplied to second node N2, therefore, the 14th transistor M14 conductings, by third with reference to electricity
The signal of pressure side VREF3 is supplied to the first signal output end OUTPUT1.
At this point, the current potential of first control signal end PW1 is high level, the current potential of second control signal end PW2 is low level,
The first transistor M1 and second transistor M2 cut-offs, third transistor M3 and the 4th transistor M4 conductings, the first reference voltage letter
The low potential of number end VREF1 is supplied to fourth node N4 by the 4th transistor M4 of conducting so that the 5th transistor M5 conducting,
The voltage of third reference voltage signal end VREF3 is supplied to second signal output end OUTPUT2, i.e. second signal output end
OUTPUT2 exports high level signal.
In the t2 stages, INPUT=1, CLK=1, CLKB=0, PW1=0, PW2=1.
Since the current potential of the first clock signal terminal CLK is high potential, the current potential of second node N2 is high potential, the tenth
Four transistor M14 cut-offs, since the current potential of second clock signal end CLKB is low potential, by the way that the 13rd transistor M13 is connected
Make the first signal output end OUTPUT1 output low level signals.
At this point, the current potential of first control signal end PW1 is low level, the current potential of second control signal end PW2 is high level,
The first transistor M1 and second transistor M2 conductings, third transistor M3 and the 4th transistor M4 cut-offs, the electricity of third node N3
Position is consistent with the current potential of the first signal output end OUTPUT1, is low level, the current potential of fourth node N4 is with second node N2's
Current potential is consistent, is high level, therefore the 5th transistor M5 cut-offs, the 6th transistor M6 are connected, the 6th transistor M6 of conducting
The voltage of first reference voltage signal end VREF1 is supplied to second signal output end OUTPUT2, therefore second signal output end
OUTPUT2 exports low level, consistent with the signal of the first signal output end OUTPUT1 outputs.
Embodiment two
By taking shift register shown in Fig. 3 as an example, wherein transistor is P-type crystal in shift register shown in Fig. 3
Pipe, the first reference signal end are low potential, and the first reference voltage signal end is same signal end, third with the second reference signal end
Reference signal end is high potential.The sequence diagram of the corresponding above-mentioned shift register of another kind is as shown in Figure 5.
In the t1 stages, INPUT=0, CLK=0, CLKB=1, PW1=0, PW2=1.
The signal of first clock signal terminal CLK makes the 7th transistor M7 conductings, and the signal of input signal end INPUT is distinguished
It is supplied to the grid of the first pole and the tenth transistor M10 of the 9th transistor M9, due to the first reference voltage signal end VRFE1's
Voltage is low potential, and the 9th transistor M9 conductings, it is low level to make the current potential of first node N1, and the tenth transistor M10 conductings will
The signal of first clock signal terminal CLK is supplied to second node N2, therefore, the 14th transistor M14 conductings, by three reference voltages
The signal of end VREF3 is supplied to the first signal output end OUTPUT1, i.e. the first signal output end OUTPUT1 to export high level.
At this point, the current potential of first control signal end PW1 is low level, the current potential of second control signal end PW2 is high level,
The first transistor M1 and second transistor M2 conductings, third transistor M3 and the 4th transistor M4 cut-offs, the electricity of third node N3
Position is consistent with the current potential of the first signal output end OUTPUT1, is high level, the current potential of fourth node N4 is with second node N2's
Current potential is consistent, is low level, therefore the 6th transistor M6 cut-offs, the 5th transistor M5 are connected, the 5th transistor M5 of conducting
The voltage of third reference voltage signal end VREF3 is supplied to second signal output end OUTPUT2, i.e. second signal output end
OUTPUT2 exports high level signal.
In the t2 stages, INPUT=1, CLK=1, CLKB=0, PW1=1, PW2=0.
Since the current potential of the first clock signal terminal CLK is high potential, the current potential of second node N2 is high potential, the tenth
Four transistor M14 cut-offs, since the current potential of second clock signal end CLKB is low potential, by the way that the 13rd transistor M13 is connected
Make the first signal output end OUTPUT1 output low level signals.
At this point, the current potential of first control signal end PW1 is high level, the current potential of second control signal end PW2 is low level,
The first transistor M1 and second transistor M2 cut-offs, third transistor M3 and the 4th transistor M4 conductings, the first reference voltage letter
The low potential of number end VREF1 is supplied to fourth node N4 by the 4th transistor M4 of conducting so that the 5th transistor M5 conducting,
The voltage of third reference voltage signal end VREF3 is supplied to second signal output end OUTPUT2, i.e. second signal output end
OUTPUT2 exports high level signal, that is to say, that second signal output end OUTPUT2 exports always high level signal.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of array substrate, as shown in fig. 6, including cascade
Multiple above-described embodiments in shift register and grid line；
In addition to afterbody shift register SR (N), the first signal output end of remaining every level-one shift register
The input signal end INPUT that OUTPUT1 distinguishes next stage shift register adjacent thereto is connected；
The second signal output end OUTPUT2 of shift register is connected with grid line.
It can be seen from the above, in gate driving circuit, the first signal output end is used to carry out between shift registers at different levels
Cascade, second signal output end for in array substrate grid line export gate drive signal, the first signal output end one
The cascade signal of straight output shift LD module output, second signal output end only need to brush in the corresponding region of display panel
Just the local display of display panel may be implemented by the setting of this kind of mode in output gated sweep signal when new, aobvious to reduce
Show the energy consumption of panel.
Specifically, in a kind of array substrate that the above embodiment of the present invention provides, further include：Processing module,
Processing module is used to obtain image to be displayed in a frame time, and identifies the refresh region of image to be displayed and non-
Refresh region, the sweep time needed for the corresponding grid line in refresh region and non-refresh region determine first control signal end and
Second control signal end needs to send out the sequential of signal.
It should be noted that above-mentioned refresh region refers to this frame image and the different region of previous frame image, non-brush
New region refers to this frame image region identical with previous frame image, and the refreshing is determined according to refresh region or non-refresh region
The number n of the corresponding grid line in region or non-refresh region determines the time needed for n grid line of scanning, so that it is determined that in flush zone
First controls new number end and second control signal to the sequential for needing to send out signal when domain or non-refresh region are scanned.
Based on same inventive concept, the embodiment of the present invention as shown in Figure 7 additionally provides a kind of driving method of array substrate,
Including：
Image to be displayed in S701, one frame time of acquisition；
S702, judge that this frame image to be displayed and previous frame image whether there is identical image；
S703, when this frame image to be displayed and previous frame image exist and differ image, corresponded to according to image is differed
Region grid line scanning needed for time, determine the time that the first signal is inputted to first control signal end, and to second
Control signal end inputs the time of second signal；
S704, when this frame image to be displayed and previous frame image are there are when identical image, according to identical figure in this frame image
Time as needed for the grid line scanning in corresponding region determines the time that second signal is inputted to first control signal end, and
The time of the first signal is inputted to second control signal end.
Specifically, the above embodiment of the present invention provide array substrate driving method in, as shown in figure 8, for example with
A longer article is being read at family, needs constantly to text region refresh that reading could be met, but reader is always
What is read is an article, there is no need to refresh in the Title area to article, therefore, and in addition to first frame, others one
In the time of frame, the image in the image in the text region of this frame image and the text region of previous frame image be it is different, i.e.,
The text region of display panel needs to refresh at any time in this frame time, and text region pair is determined according to the image in text region
The grid line number answered, so that it is determined that the time needed for the grid line of the corresponding number of scanning, and then determination is defeated to first control signal end
Enter the time of the first signal, and input the time of second signal to the second control signal end so that within the time with
The second signal output end of the shift register of the region grid line connection exports gated sweep signal.
Similarly, the image of the image of Title area and previous frame Title area is identical, and the Title area is in this frame time
It is interior to be not necessarily to be refreshed, the corresponding grid line number of Title area is determined according to the image of Title area, so that it is determined that scanning pair
It answers the time needed for the grid line of number, and then determines the time for inputting second signal to first control signal end, and to described
Second control signal end inputs the time of the first signal, so that the shift register that grid line is connect with the region within the time
Second signal output end exports gate off signal.
Wherein, how second signal output end is made to export by controlling first control signal end and second control signal end
Different signals, identical as principle shown in above-described embodiment, details are not described herein.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned array substrate.
The display device can be：Mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator etc. are any
Product with display function or component.The implementation of the display device may refer to the embodiment of above-mentioned gate driving circuit, weight
Multiple place repeats no more.
A kind of shift register, array substrate and its driving method provided in an embodiment of the present invention, display device, the displacement
Register includes：Shift LD module, the first transistor, second transistor, third transistor, the 4th transistor, the 5th crystal
Pipe and the 6th transistor；By the mutual cooperation of above-mentioned shift LD module and each transistor, at first control signal end and
Under the control of two control signal ends, second signal output end is made to export gated sweep signal, or two output end of signal is made to export
Gate off signal.When grid line of the second signal output end in array substrate exports gated sweep signal, which corresponds to
Display area normally refreshed；When grid line of the second signal output end in array substrate exports gate off signal
When, the corresponding display area of the grid line is without refreshing.Display panel can be made to carry out local display by this kind setting, to reach
To the purpose for reducing display panel power consumption.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (13)
1. a kind of shift register, which is characterized in that including：Shift LD module, the first transistor, second transistor, third
Transistor, the 4th transistor, the 5th transistor and the 6th transistor；Wherein,
The shift LD module is used in the first clock signal terminal, second clock signal end, input signal end and the first reference
The signal of first clock signal terminal is supplied to the first pole of the first transistor, when by second under the control of voltage signal end
The signal of clock signal end is supplied to the first signal output end；
The first transistor is used for the signal of the first pole of the first transistor under the control at first control signal end
It is supplied to the grid of the 5th transistor；
The second transistor is used for the signal of first signal output end under the control at the first control signal end
It is supplied to the grid of the 6th transistor；
The third transistor is for providing the signal at third reference voltage signal end under the control at second control signal end
To the grid of the 6th transistor；
4th transistor is used for the signal at the second reference voltage signal end under the control at the second control signal end
It is supplied to the grid of the 5th transistor；
5th transistor is used in the voltage of the second pole of the first transistor or the second pole of the 4th transistor
Voltage control under the signal at third reference voltage signal end is supplied to second signal output end；
6th transistor is used in the voltage of the second pole of the second transistor or the second pole of the third transistor
Voltage control under the signal at second reference voltage signal end is supplied to second signal output end.
2. shift register as described in claim 1, which is characterized in that the grid of the first transistor is controlled with described first
Signal end processed is connected, and the first pole of the first transistor is connected with the shift LD module, and the of the first transistor
Two poles are connected with the grid of the 5th transistor.
3. shift register as described in claim 1, which is characterized in that the grid of the second transistor is controlled with described first
Signal end processed is connected, and the first pole of the second transistor is connected with first signal output end, the second transistor
Second pole is connected with the grid of the 6th transistor.
4. shift register as described in claim 1, which is characterized in that the grid of the third transistor is controlled with described second
Signal end processed is connected, and the first pole of the third transistor is connected with third reference voltage signal end, the third crystal
Second pole of pipe is connected with the grid of the 6th transistor.
5. shift register as described in claim 1, which is characterized in that the grid of the 4th transistor is controlled with described second
Signal end processed is connected, and the first pole of the 4th transistor is connected with second reference voltage signal end, the 4th crystal
Second pole of pipe is connected with the grid of the 5th transistor.
6. shift register as described in claim 1, which is characterized in that the grid difference the described 4th of the 5th transistor
Second pole of transistor is extremely connected with the second of the first transistor, and the first pole and the third of the 5th transistor are joined
It examines voltage signal end to be connected, the second pole of the 5th transistor is connected with the second signal output end.
7. shift register as described in claim 1, which is characterized in that the grid difference described second of the 6th transistor
Second pole of transistor is extremely connected with the second of the third transistor, and the first pole of the 6th transistor is joined with described second
It examines voltage signal end to be connected, the second pole of the 6th transistor is connected with the second signal output end.
8. shift register as described in claim 1, which is characterized in that the shift LD module includes：7th transistor,
8th transistor, the 9th transistor, the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor, the tenth
Four transistors, the first capacitance and the second capacitance；
The grid of 7th transistor is connected with first clock signal terminal, the first pole of the 7th transistor with it is described
Input signal end is connected, and the second pole of the 7th transistor is extremely connected with the first of the 11st transistor；
The grid of 8th transistor is connected with first clock signal terminal, the first pole of the 8th transistor with it is described
First reference voltage signal end is connected, and the second pole of the 8th transistor is brilliant with the tenth two-transistor and the 14th respectively
The grid of body pipe is connected；
The grid of 9th transistor is connected with first reference voltage signal end, the first pole of the 9th transistor with
The second of 7th transistor is extremely connected, the grid phase of the second pole and the 13rd transistor of the 9th transistor
Even；
The grid of tenth transistor is extremely connected with the first of the 9th transistor, the first pole of the tenth transistor with
First clock signal terminal is connected, and the second pole of the tenth transistor is connected with the grid of the tenth two-transistor；
The grid of 11st transistor is connected with the second clock signal end, the second pole of the 11st transistor with
The first of tenth two-transistor is extremely connected；
Second pole of the tenth two-transistor is connected with third reference voltage signal end；
First pole of the 13rd transistor is connected with the second clock signal end, the second pole of the 13rd transistor
It is connected with first signal output end；
The first pole of 14th transistor is connected with first signal output end, the second pole of the 14th transistor and institute
Third reference voltage signal end is stated to be connected；
One end of first capacitance is connected with the grid of the 13rd transistor, the other end of first capacitance with it is described
First signal output end is connected；
One end of second capacitance is connected with the grid of the 14th transistor, the other end of second capacitance with it is described
The first of the first transistor is extremely connected.
9. such as claim 1-8 any one of them shift registers, which is characterized in that all transistors are N-type transistor
Or P-type transistor.
10. a kind of array substrate, which is characterized in that including cascade multiple as the displacement of claim 1-9 any one of them is posted
Storage and grid line；
In addition to afterbody shift register, the first signal output end difference of remaining every level-one shift register is adjacent thereto
Next stage shift register input signal end be connected；
The second signal output end of the shift register is connected with the grid line.
11. array substrate as claimed in claim 10, which is characterized in that further include：Processing module,
The processing module is used to obtain the image to be displayed in a frame time, and identifies the refresh region of the image to be displayed
With non-refresh region, the sweep time needed for the corresponding grid line in the refresh region and the non-refresh region determines first
Control signal end and second control signal end need to send out the sequential of signal.
12. a kind of driving method of array substrate as described in claim 10 or 11, which is characterized in that including：
Obtain the image to be displayed in a frame time；
Judge that image to be displayed described in this frame whether there is identical image with previous frame image；
The image to be displayed described in this frame exists with previous frame image when differing image, according to differing the corresponding region of image
Grid line scanning needed for time, determine the time that the first signal is inputted to the first control signal end, and to described the
Two control signal ends input the time of second signal；
The image to be displayed described in this frame and previous frame image are there are when identical image, according to identical image described in this frame image
Time needed for the grid line scanning in corresponding region, determine the time that second signal is inputted to the first control signal end, with
And the time of the first signal is inputted to the second control signal end.
13. a kind of display device, which is characterized in that include the array substrate as described in claim 10 or 11.
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