CN108461062B - Shifting register, array substrate, driving method of array substrate and display device - Google Patents

Shifting register, array substrate, driving method of array substrate and display device Download PDF

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Publication number
CN108461062B
CN108461062B CN201810272167.1A CN201810272167A CN108461062B CN 108461062 B CN108461062 B CN 108461062B CN 201810272167 A CN201810272167 A CN 201810272167A CN 108461062 B CN108461062 B CN 108461062B
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transistor
pole
signal
shift register
gate
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CN108461062A (en
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席克瑞
向东旭
崔婷婷
林柏全
李元
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Wuhan Tianma Microelectronics Co Ltd
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Shanghai Tianma AM OLED Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a shift register, an array substrate, a driving method thereof and a display device, wherein the shift register comprises: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; under the control of the first control signal end and the second control signal end, the second signal output end outputs a grid electrode scanning signal, or the second signal output end outputs a grid electrode closing signal. When the second signal output end outputs a grid scanning signal to the grid line on the array substrate, the display area corresponding to the grid line is refreshed normally; when the second signal output end outputs a grid electrode closing signal to the grid line on the array substrate, the display area corresponding to the grid line is not refreshed. The display panel can perform local display through the arrangement, so that the purpose of reducing the power consumption of the display panel is achieved.

Description

Shifting register, array substrate, driving method of array substrate and display device
Technical Field
The invention relates to the technical field of display, in particular to a shift register, an array substrate, a driving method of the array substrate and a display device.
Background
In a flat panel display panel, a gate-on signal is generally supplied to a gate of each Thin Film Transistor (TFT) of a pixel region through a gate driving circuit. The Gate driving Circuit may be formed on an Array substrate of the flat Panel display Panel through an Array process, i.e., a Gate Driver on Array (GOA) process, which not only saves cost, but also may achieve an aesthetic design of bilateral symmetry of the flat Panel display Panel (Panel), and simultaneously, may also save a Bonding area of the Gate Integrated Circuit (IC) and a wiring space of the Fan-out (Fan-out), thereby implementing a design of a narrow bezel.
The gate driving circuit in the related art is formed by cascading a plurality of cascaded shift registers, each shift register is used for providing a gate start signal to a gate line connected to a signal output end of the shift register to start the TFT of a pixel region of a corresponding row. Except the first stage of shift register, the input signal ends of the other shift registers are respectively connected with the signal output end of the shift register of the previous stage. However, when the display panel is only required to perform local display, the control signal cannot be output only to a part of the gate lines arranged on the array substrate, or the control signal can be output to each gate line on the array substrate step by step, so that the overall power consumption of the display panel can be greatly increased.
Therefore, how to implement local display of the display panel, thereby saving power consumption of the display panel is an urgent problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a shift register, an array substrate, a driving method of the array substrate and a display device, which are used for realizing local display of a display panel so as to reduce the power consumption of the display panel.
The shift register provided by the embodiment of the invention comprises: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the content of the first and second substances,
the shift register module is used for providing a signal of a first clock signal end to a first pole of the first transistor under the control of the first clock signal end, the second clock signal end, the input signal end and the first reference voltage signal end, and providing a signal of the second clock signal end to a first signal output end;
the first transistor is used for providing a signal of a first pole of the first transistor to a grid electrode of the fifth transistor under the control of a first control signal terminal;
the second transistor is used for providing a signal of the first signal output end to the grid electrode of the sixth transistor under the control of the first control signal end;
the third transistor is used for providing a signal of a third reference voltage signal end to a grid electrode of the sixth transistor under the control of a second control signal end;
the fourth transistor is used for providing a signal of a second reference voltage signal end to the grid electrode of the fifth transistor under the control of the second control signal end;
the fifth transistor is used for providing a signal of the third reference voltage signal end to a second signal output end under the control of the voltage of the second pole of the first transistor or the voltage of the second pole of the fourth transistor;
the sixth transistor is configured to provide a signal of the second reference voltage signal terminal to a second signal output terminal under control of a voltage of a second pole of the second transistor or a voltage of a second pole of the third transistor.
On the other hand, the embodiment of the invention also provides an array substrate, which comprises a plurality of cascaded shift registers and grid lines, wherein the shift registers and the grid lines are as described in the embodiment;
except the shift register of the last stage, the first signal output end of the shift register of each other stage is respectively connected with the input signal end of the next stage of the adjacent shift register;
and the second signal output end of the shift register is connected with the grid line.
On the other hand, an embodiment of the present invention further provides a driving method of the array substrate provided in the above embodiment, including:
acquiring an image to be displayed within a frame time;
judging whether the image to be displayed in the current frame and the image in the previous frame have the same image or not;
when the image to be displayed in the frame is different from the image in the previous frame, determining the time for inputting a first signal to the first control signal end and the time for inputting a second signal to the second control signal end according to the time required by the grid line scanning of the area corresponding to the different image;
when the image to be displayed in the current frame and the image in the previous frame have the same image, determining the time for inputting the second signal to the first control signal end and the time for inputting the first signal to the second control signal end according to the time required by the grid line scanning of the region corresponding to the same image in the current frame.
On the other hand, an embodiment of the present invention further provides a display device, including: the array substrate provided by the embodiment of the invention.
The invention has the following beneficial effects:
the embodiment of the invention provides a shift register, an array substrate, a driving method thereof and a display device, wherein the shift register comprises: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; through the mutual matching of the shift register module and each transistor, the second signal output end outputs a grid scanning signal or outputs a grid closing signal under the control of the first control signal end and the second control signal end. When the second signal output end outputs a grid scanning signal to the grid line on the array substrate, the display area corresponding to the grid line is refreshed normally; when the second signal output end outputs a grid electrode closing signal to the grid line on the array substrate, the display area corresponding to the grid line is not refreshed. The display panel can perform local display through the arrangement, so that the purpose of reducing the power consumption of the display panel is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a gate driving circuit in the related art;
fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the shift register shown in FIG. 3;
FIG. 5 is another timing diagram corresponding to the shift register provided in FIG. 3;
fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 7 is a flowchart of a driving method of an array substrate according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, fig. 1 is a schematic structural diagram of a gate driving circuit in the related art, where the gate driving circuit in the related art includes a plurality of cascaded shift registers: SR (1), SR (2) … SR (N) … SR (N-1), SR (N) (N shift registers, N is more than or equal to 1 and less than or equal to N); except for the first stage shift register SR (1), the signal output end output of each stage of shift register SR (n) is respectively connected with the reset signal end reset of the adjacent previous stage shift register SR (n-1); except for the last stage of shift register SR (N), the signal output terminals output of the shift registers SR (n) of each stage are respectively connected to the input signal terminals input of the next stage of shift register SR (n +1) adjacent thereto. In the arrangement of the gate driving circuit, each stage of shift register sends a gate scanning signal to the corresponding gate line, that is, when the display panel displays, only full-screen display can be performed, but only a partial area of the display panel cannot be displayed.
Embodiments of the present invention provide a shift register, an array substrate, a driving method thereof, and a display device, so as to reduce power consumption of a display panel.
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register, an array substrate, a driving method thereof and a display device according to embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
Specifically, an embodiment of the present invention provides a shift register, as shown in fig. 2, fig. 2 is a schematic structural diagram of the shift register provided in the embodiment of the present invention; the shift register includes: a shift register module, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6; wherein the content of the first and second substances,
the shift register module is used for providing a signal of the first clock signal terminal CLK to a first pole of the first transistor M1 under the control of the first clock signal terminal CLK, the second clock signal terminal CLKB, the INPUT signal terminal INPUT and the first reference voltage signal terminal VREF1, and providing a signal of the second clock signal terminal CLKB to the first signal OUTPUT terminal OUTPUT 1;
the first transistor M1 is used for providing a signal of a first pole of the first transistor M1 to a gate of the fifth transistor M5 under the control of a first control signal terminal PW 1;
the second transistor M2 is used to provide the signal of the first signal OUTPUT terminal OUTPUT1 to the gate of the sixth transistor M6 under the control of the first control signal terminal PW 1;
the third transistor M3 is used to provide a signal of a third reference voltage signal terminal VREF3 to the gate of the sixth transistor M6 under the control of the second control signal terminal PW 2;
the fourth transistor M4 is for providing a signal of a second reference voltage signal terminal VREF2 to the gate of the fifth transistor M5 under the control of the second control signal terminal PW 2;
the fifth transistor M5 is used to provide a signal of the third reference voltage signal terminal VREF3 to the second signal OUTPUT terminal OUTPUT2 under the control of the voltage of the second pole of the first transistor M1 or the voltage of the second pole of the fourth transistor M4;
the sixth transistor M6 is used to provide the signal of the second reference voltage signal terminal VREF2 to the second signal OUTPUT terminal OUTPUT2 under the control of the voltage of the second pole of the second transistor M2 or the voltage of the second pole of the third transistor M3.
The shift register provided by the embodiment of the invention comprises: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; through the mutual matching of the shift register module and each transistor, the second signal output end outputs a grid scanning signal or outputs a grid closing signal under the control of the first control signal end and the second control signal end. When the second signal output end outputs a grid scanning signal to the grid line on the array substrate, the display area corresponding to the grid line is refreshed normally; when the second signal output end outputs a grid electrode closing signal to the grid line on the array substrate, the display area corresponding to the grid line is not refreshed. The display panel can perform local display through the arrangement, so that the purpose of reducing the power consumption of the display panel is achieved.
Specifically, in the shift register according to the embodiment of the invention, as shown in fig. 2, all the transistors are P-type transistors, the second reference voltage signal terminal VREF2 is a low-level signal, and the third reference voltage signal terminal VREF3 is a high-level signal, for example, when the signal provided by the first control signal terminal PW1 is a low-level signal and the signal provided by the second control signal terminal PW2 is a high-level signal, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 and the fourth transistor M4 are turned off, at this time, the gate potential of the sixth transistor M6 is consistent with the potential of the first signal OUTPUT terminal OUTPUT1, and the gate potential of the fifth transistor M5 is consistent with the potential of the second node N2, that is, the potential of the second node N2 is consistent with the potential of the fourth node N4. When the potential of the first signal OUTPUT terminal OUTPUT1 is at a low level, the potential of the second node N2 is at a high level, the sixth transistor M6 is turned on, the fifth transistor M5 is turned off, and at this time, the potential of the second reference voltage signal terminal VREF2 is supplied to the second signal OUTPUT terminal OUTPUT2 through the turned-on sixth transistor M2; when the potential of the first signal OUTPUT terminal OUTPUT1 is at a high level, the potential of the second node N2 is at a low level, the sixth transistor M6 is turned off, the fifth transistor M5 is turned on, and at this time, the potential of the third reference voltage signal terminal VRFE3 is provided to the second signal OUTPUT terminal OUTPUT2 through the turned-on fifth transistor M5, that is, the second signal OUTPUT terminal OUTPUT2 can OUTPUT a normal gate scan signal to its corresponding gate line.
When the signal provided by the first control signal terminal PW1 is a high-level signal and the signal provided by the second control signal terminal PW2 is a low-level signal, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 and the fourth transistor M4 are turned on, the third transistor M3 is turned on to provide the third reference voltage signal VREF3 to the third node N3, and the sixth transistor M6 is turned off; the fourth transistor M4 is turned on to supply the voltage of the second reference voltage signal terminal VREF2 to the fourth node N4, and the fifth transistor M5 is turned on to supply the voltage of the third reference voltage signal terminal VREF3 to the second signal OUTPUT terminal OUTPUT2, that is, the second signal OUTPUT terminal OUTPUT2 consistently OUTPUTs a high level, and the high level is a gate-off signal, so that the transistors connected to the gate lines in the array substrate cannot be turned on.
Specifically, in the shift register provided in the embodiment of the present invention, the gate of the first transistor M1 is connected to the first control signal terminal, the first pole of the first transistor M1 is connected to the shift register module, and the second pole of the first transistor M1 is connected to the gate of the fifth transistor M5.
Specifically, in the shift register provided in the embodiment of the present invention, the gate of the second transistor M2 is connected to the first control signal terminal, the first pole of the second transistor M2 is connected to the first signal output terminal, and the second pole of the second transistor M2 is connected to the gate of the sixth transistor M6.
Specifically, in the shift register according to the embodiment of the invention, the gate of the third transistor M3 is connected to the second control signal terminal, the first pole of the third transistor M3 is connected to the third reference voltage signal terminal, and the second pole of the third transistor M3 is connected to the gate of the sixth transistor M6.
Specifically, in the shift register provided in the embodiment of the present invention, the gate of the fourth transistor M4 is connected to the second control signal terminal, the first pole of the fourth transistor M4 is connected to the second reference voltage signal terminal, and the second pole of the fourth transistor M4 is connected to the gate of the fifth transistor M5.
Specifically, in the shift register provided in the embodiment of the present invention, the gates of the fifth transistor M5 are respectively connected to the second pole of the fourth transistor M4 and the second pole of the first transistor M1, the first pole of the fifth transistor M5 is connected to the third reference voltage signal terminal, and the second pole of the fifth transistor M5 is connected to the second signal output terminal.
Specifically, in the shift register provided in the embodiment of the present invention, the gates of the sixth transistor M6 are respectively connected to the second pole of the second transistor M2 and the second pole of the third transistor M3, the first pole of the sixth transistor M6 is connected to the second reference voltage signal terminal, and the second pole of the sixth transistor M6 is connected to the second signal output terminal.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the shift register module includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a first capacitor C1, and a second capacitor C2;
a gate of the seventh transistor M7 is connected to the first clock signal terminal CLK, a first pole of the seventh transistor M7 is connected to the INPUT signal terminal INPUT, and a second pole of the seventh transistor M7 is connected to a first pole of the eleventh transistor M11;
a gate of the eighth transistor M8 is connected to the first clock signal terminal CLK, a first pole of the eighth transistor M8 is connected to the first reference voltage signal terminal VREF1, and a second pole of the eighth transistor M8 is connected to gates of the twelfth transistor M12 and the fourteenth transistor M14, respectively;
a gate of the ninth transistor M9 is connected to the first reference voltage signal terminal VREF1, a first pole of the ninth transistor M9 is connected to the second pole of the seventh transistor M7, and a second pole of the ninth transistor M9 is connected to the gate of the thirteenth transistor M13;
a gate of the tenth transistor M10 is connected to a first pole of the ninth transistor M9, a first pole of the tenth transistor M10 is connected to the first clock signal terminal CLK, and a second pole of the tenth transistor M10 is connected to a gate of the twelfth transistor M12;
a gate of the eleventh transistor M11 is connected to the second clock signal terminal CLKB, and a second pole of the eleventh transistor M11 is connected to a first pole of the twelfth transistor M12;
a second pole of the twelfth transistor M12 is connected to the third reference voltage signal terminal VREF 3;
a first pole of the thirteenth transistor M13 is connected to the second clock signal terminal CLKB, and a second pole of the thirteenth transistor M13 is connected to the first signal OUTPUT terminal OUTPUT 1;
a first pole of the fourteenth transistor M14 is connected to the first signal OUTPUT terminal OUTPUT1, and a second pole of the fourteenth transistor M14 is connected to the third reference voltage signal terminal VREF 3;
one end of the first capacitor C1 is connected to the gate of the thirteenth transistor M13, and the other end of the first capacitor C1 is connected to the first signal OUTPUT terminal OUTPUT 1;
one end of the second capacitor C2 is connected to the gate of the fourteenth transistor M14, and the other end of the second capacitor C2 is connected to the first pole of the first transistor M1.
The above is merely an example of the specific structure of the shift register module in the shift register, and in the specific implementation, the specific structure of the shift register module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, which is not limited herein.
Specifically, in the shift register provided in the embodiment of the present invention, in order to simplify the manufacturing process, the transistors are generally made of the same material, and therefore, all the transistors are N-type transistors or P-type transistors. In specific implementation, when the electric potential of the required grid opening signal is high electric potential, all the transistors are N-type transistors; when the required grid opening signal is at low potential, all the transistors are P-type transistors.
Furthermore, in specific implementation, the N-type transistor is turned on under the action of high potential and is turned off under the action of low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.
It should be noted that the transistors mentioned in the above embodiments of the present invention are all Metal Oxide semiconductor field effect transistors (MOS). In an implementation, the first electrodes of the transistors are the source electrodes and the second electrodes are the drain electrodes, or the first electrodes are the drain electrodes and the second electrodes are the source electrodes, which are not specifically distinguished here.
The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.
Example one
Taking the shift register shown in fig. 3 as an example, the transistors in the shift register shown in fig. 3 are all P-type transistors, the first reference voltage signal terminal VREF1 is at a low potential, and the third reference voltage signal terminal VREF3 is at a high potential. A timing chart of a corresponding one of the shift registers is shown in fig. 4.
At stage t1, INPUT is 0, CLK is 0, CLKB is 1, PW1 is 1, and PW2 is 0.
The seventh transistor M7 is turned on by the signal of the first clock signal terminal CLK, the signal of the INPUT signal terminal INPUT is respectively provided to the first pole of the ninth transistor M9 and the gate of the tenth transistor M10, and since the voltage of the first reference voltage signal terminal VREF1 is low, the ninth transistor M9 is turned on, the potential of the first node N1 is low, and the tenth transistor M10 is turned on to provide the signal of the first clock signal terminal CLK to the second node N2, the fourteenth transistor M14 is turned on, and the signal of the third reference voltage terminal VREF3 is provided to the first signal OUTPUT terminal OUTPUT 1.
At this time, the potential of the first control signal terminal PW1 is at a high level, the potential of the second control signal terminal PW2 is at a low level, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 and the fourth transistor M4 are turned on, the low level of the first reference voltage signal terminal VREF1 is provided to the fourth node N4 through the turned-on fourth transistor M4, so that the fifth transistor M5 is turned on, and the voltage of the third reference voltage signal terminal VREF3 is provided to the second signal OUTPUT terminal OUTPUT2, that is, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a high level signal.
At stage t2, INPUT is 1, CLK is 1, CLKB is 0, PW1 is 0, and PW2 is 1.
Since the potential of the first clock signal terminal CLK is high, the potential of the second node N2 is high, the fourteenth transistor M14 is turned off, and since the potential of the second clock signal terminal CLKB is low, the first signal OUTPUT terminal OUTPUT1 OUTPUTs a low level signal by turning on the thirteenth transistor M13.
At this time, the potential of the first control signal terminal PW1 is at a low level, the potential of the second control signal terminal PW2 is at a high level, the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 and the fourth transistor M4 are turned off, the potential of the third node N3 is equal to the potential of the first signal OUTPUT terminal OUTPUT1, and both are at a low level, and the potential of the fourth node N4 is equal to the potential of the second node N2, and both are at a high level, so that the fifth transistor M5 is turned off, the sixth transistor M6 is turned on, and the turned-on sixth transistor M6 supplies the voltage of the first reference voltage signal terminal VREF1 to the second signal OUTPUT terminal OUTPUT2, and therefore the second signal OUTPUT terminal OUTPUT2 OUTPUTs a low level, which is equal to the signal OUTPUT by the first signal OUTPUT terminal OUTPUT 1.
Example two
Taking the shift register shown in fig. 3 as an example, the transistors in the shift register shown in fig. 3 are all P-type transistors, the first reference signal terminal is a low potential, the first reference voltage signal terminal and the second reference signal terminal are the same signal terminal, and the third reference signal terminal is a high potential. A timing diagram of another corresponding shift register is shown in fig. 5.
At stage t1, INPUT is 0, CLK is 0, CLKB is 1, PW1 is 0, and PW2 is 1.
The seventh transistor M7 is turned on by the signal of the first clock signal terminal CLK, the signal of the INPUT signal terminal INPUT is respectively provided to the first pole of the ninth transistor M9 and the gate of the tenth transistor M10, the ninth transistor M9 is turned on because the voltage of the first reference voltage signal terminal VRFE1 is low, the potential of the first node N1 is low, the tenth transistor M10 is turned on to provide the signal of the first clock signal terminal CLK to the second node N2, and therefore, the fourteenth transistor M14 is turned on to provide the signal of the three reference voltage terminal VREF3 to the first signal OUTPUT terminal OUTPUT1, that is, the first signal OUTPUT terminal OUTPUT1 OUTPUTs high level.
At this time, the potential of the first control signal terminal PW1 is at a low level, the potential of the second control signal terminal PW2 is at a high level, the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 and the fourth transistor M4 are turned off, the potential of the third node N3 is equal to the potential of the first signal OUTPUT terminal OUTPUT1 and is at a high level, the potential of the fourth node N4 is equal to the potential of the second node N2 and is at a low level, so that the sixth transistor M6 is turned off, the fifth transistor M5 is turned on, and the turned-on fifth transistor M5 supplies the voltage of the third reference voltage signal terminal VREF3 to the second signal OUTPUT terminal OUTPUT2, that is, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a high-level signal.
At stage t2, INPUT is 1, CLK is 1, CLKB is 0, PW1 is 1, and PW2 is 0.
Since the potential of the first clock signal terminal CLK is high, the potential of the second node N2 is high, the fourteenth transistor M14 is turned off, and since the potential of the second clock signal terminal CLKB is low, the first signal OUTPUT terminal OUTPUT1 OUTPUTs a low level signal by turning on the thirteenth transistor M13.
At this time, the potential of the first control signal terminal PW1 is at a high level, the potential of the second control signal terminal PW2 is at a low level, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 and the fourth transistor M4 are turned on, the low level of the first reference voltage signal terminal VREF1 is provided to the fourth node N4 through the turned-on fourth transistor M4, so that the fifth transistor M5 is turned on, the voltage of the third reference voltage signal terminal VREF3 is provided to the second signal OUTPUT terminal OUTPUT2, that is, the second signal OUTPUT terminal OUTPUT2 OUTPUTs a high level signal, that is, the second signal OUTPUT terminal OUTPUT2 always OUTPUTs a high level signal.
Based on the same inventive concept, an embodiment of the present invention further provides an array substrate, as shown in fig. 6, including a plurality of cascaded shift registers and gate lines in the foregoing embodiments;
except for the last stage of shift register SR (N), the first signal OUTPUT terminal OUTPUT1 of each stage of shift register is respectively connected with the INPUT signal terminal INPUT of the next stage of shift register adjacent to the first signal OUTPUT terminal OUTPUT 1;
the second signal OUTPUT terminal OUTPUT2 of the shift register is connected to the gate line.
Therefore, in the gate driving circuit, the first signal output end is used for cascading shift registers at different levels, the second signal output end is used for outputting gate driving signals to gate lines on the array substrate, the first signal output end always outputs the cascading signals output by the shift register module, and the second signal output end only outputs gate scanning signals when the region corresponding to the display panel needs to be refreshed.
Specifically, in the array substrate provided in the above embodiment of the present invention, further includes: a processing module for processing the received data,
the processing module is used for acquiring an image to be displayed within a frame time, identifying a refresh area and a non-refresh area of the image to be displayed, and determining the time sequence of the first control signal end and the second control signal end which need to send signals according to the scanning time required by the grid lines corresponding to the refresh area and the non-refresh area.
It should be noted that the refresh area refers to an area where the current frame image is different from the previous frame image, the non-refresh area refers to an area where the current frame image is the same as the previous frame image, the number n of the gate lines corresponding to the refresh area or the non-refresh area is determined according to the refresh area or the non-refresh area, and the time required for scanning n gate lines is determined, so that the time sequence from the first control new number end to the signal sending required when the refresh area or the non-refresh area is scanned is determined.
Based on the same inventive concept, as shown in fig. 7, the embodiment of the present invention further provides a driving method of an array substrate, including:
s701, acquiring an image to be displayed within one frame time;
s702, judging whether the image to be displayed in the current frame and the image in the previous frame have the same image or not;
s703, when the image to be displayed in the current frame is different from the image in the previous frame, determining the time for inputting the first signal to the first control signal terminal and the time for inputting the second signal to the second control signal terminal according to the time required for scanning the grid line in the region corresponding to the different image;
and S704, when the image to be displayed in the current frame and the image in the previous frame have the same image, determining the time for inputting the second signal to the first control signal terminal and the time for inputting the first signal to the second control signal terminal according to the time required by the grid line scanning of the region corresponding to the same image in the current frame.
Specifically, in the driving method of the array substrate according to the above embodiment of the present invention, as shown in fig. 8, for example, when a user reads a long article, the text area needs to be continuously refreshed to satisfy reading, but a reader always reads the article, and therefore the title area of the article does not need to be refreshed, so that, in a time of one frame other than the first frame, an image of the text area of the image of the current frame is different from an image of the text area of the image of the previous frame, that is, the text area of the display panel needs to be refreshed at any time in the time of the current frame, the number of gate lines corresponding to the text area is determined according to the image of the text area, so as to determine a time required for scanning the corresponding number of gate lines, and further determine a time for inputting the first signal to the first control signal terminal, and a time for inputting the second signal to the second control signal terminal, so that the second signal output terminal of the shift register connected to the gate line of the region outputs the gate scan signal during the time.
Similarly, the image of the header region is the same as the image of the header region of the previous frame, the header region does not need to be refreshed within the time of the current frame, the number of the gate lines corresponding to the header region is determined according to the image of the header region, so that the time required for scanning the corresponding number of the gate lines is determined, the time for inputting the second signal to the first control signal terminal is further determined, and the time for inputting the first signal to the second control signal terminal is further determined, so that the second signal output terminal of the shift register connected with the gate lines of the region within the time outputs the gate off signal.
How to enable the second signal output end to output different signals by controlling the first control signal end and the second control signal end is the same as the principle shown in the above embodiments, and is not described herein again.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the array substrate. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.
The embodiment of the invention provides a shift register, an array substrate, a driving method thereof and a display device, wherein the shift register comprises: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; through the mutual matching of the shift register module and each transistor, the second signal output end outputs a grid scanning signal or outputs a grid closing signal under the control of the first control signal end and the second control signal end. When the second signal output end outputs a grid scanning signal to the grid line on the array substrate, the display area corresponding to the grid line is refreshed normally; when the second signal output end outputs a grid electrode closing signal to the grid line on the array substrate, the display area corresponding to the grid line is not refreshed. The display panel can perform local display through the arrangement, so that the purpose of reducing the power consumption of the display panel is achieved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (12)

1. A shift register, comprising: the shift register module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the content of the first and second substances,
the shift register module is used for providing a signal of a first clock signal end to a first pole of the first transistor under the control of the first clock signal end, the second clock signal end, the input signal end and the first reference voltage signal end, and providing a signal of the second clock signal end to a first signal output end;
the first transistor is used for providing a signal of a first pole of the first transistor to a grid electrode of the fifth transistor under the control of a first control signal terminal;
the second transistor is used for providing a signal of the first signal output end to the grid electrode of the sixth transistor under the control of the first control signal end;
the third transistor is used for providing a signal of a third reference voltage signal end to a grid electrode of the sixth transistor under the control of a second control signal end;
the fourth transistor is used for providing a signal of a second reference voltage signal end to the grid electrode of the fifth transistor under the control of the second control signal end;
the fifth transistor is used for providing a signal of the third reference voltage signal end to a second signal output end under the control of the voltage of the second pole of the first transistor or the voltage of the second pole of the fourth transistor;
the sixth transistor is configured to provide a signal of the second reference voltage signal terminal to a second signal output terminal under control of a voltage of a second pole of the second transistor or a voltage of a second pole of the third transistor.
2. The shift register of claim 1, wherein a gate of the second transistor is connected to the first control signal terminal, a first pole of the second transistor is connected to the first signal output terminal, and a second pole of the second transistor is connected to a gate of the sixth transistor.
3. The shift register of claim 1, wherein a gate of the third transistor is connected to the second control signal terminal, a first pole of the third transistor is connected to the third reference voltage signal terminal, and a second pole of the third transistor is connected to a gate of the sixth transistor.
4. The shift register of claim 1, wherein a gate of the fourth transistor is connected to the second control signal terminal, a first pole of the fourth transistor is connected to the second reference voltage signal terminal, and a second pole of the fourth transistor is connected to a gate of the fifth transistor.
5. The shift register of claim 1, wherein gates of the fifth transistors are connected to a second pole of the fourth transistor and a second pole of the first transistor, respectively, a first pole of the fifth transistor is connected to the third reference voltage signal terminal, and a second pole of the fifth transistor is connected to the second signal output terminal.
6. The shift register of claim 1, wherein gates of the sixth transistors are connected to a second pole of the second transistor and a second pole of the third transistor, respectively, a first pole of the sixth transistor is connected to the second reference voltage signal terminal, and a second pole of the sixth transistor is connected to the second signal output terminal.
7. The shift register of claim 1, wherein the shift register module comprises: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, and a second capacitor;
a gate of the seventh transistor is connected to the first clock signal terminal, a first pole of the seventh transistor is connected to the input signal terminal, and a second pole of the seventh transistor is connected to the first pole of the eleventh transistor;
a gate of the eighth transistor is connected to the first clock signal terminal, a first pole of the eighth transistor is connected to the first reference voltage signal terminal, and a second pole of the eighth transistor is connected to gates of the twelfth transistor and the fourteenth transistor, respectively;
a gate of the ninth transistor is connected to the first reference voltage signal terminal, a first pole of the ninth transistor is connected to the second pole of the seventh transistor, and a second pole of the ninth transistor is connected to the gate of the thirteenth transistor;
a gate of the tenth transistor is connected to a first electrode of the ninth transistor, a first electrode of the tenth transistor is connected to the first clock signal terminal, and a second electrode of the tenth transistor is connected to a gate of the twelfth transistor;
a gate of the eleventh transistor is connected to the second clock signal terminal, and a second pole of the eleventh transistor is connected to the first pole of the twelfth transistor;
a second pole of the twelfth transistor is connected with a third reference voltage signal end;
a first pole of the thirteenth transistor is connected with the second clock signal end, and a second pole of the thirteenth transistor is connected with the first signal output end;
a first pole of the fourteenth transistor is connected with the first signal output end, and a second pole of the fourteenth transistor is connected with the third reference voltage signal end;
one end of the first capacitor is connected with the grid electrode of the thirteenth transistor, and the other end of the first capacitor is connected with the first signal output end;
one end of the second capacitor is connected to the gate of the fourteenth transistor, and the other end of the second capacitor is connected to the third reference voltage signal terminal.
8. A shift register as claimed in any one of claims 1 to 7, in which all the transistors are N-type transistors or P-type transistors.
9. An array substrate, comprising a plurality of shift registers and gate lines according to any one of claims 1 to 8 in cascade;
except the shift register of the last stage, the first signal output end of the shift register of each other stage is respectively connected with the input signal end of the next stage of the adjacent shift register;
and the second signal output end of the shift register is connected with the grid line.
10. The array substrate of claim 9, further comprising: a processing module for processing the received data,
the processing module is used for acquiring an image to be displayed within a frame time, identifying a refresh area and a non-refresh area of the image to be displayed, and determining the time sequence of a first control signal end and a second control signal end which need to send signals according to the scanning time required by grid lines corresponding to the refresh area and the non-refresh area.
11. A driving method of the array substrate according to claim 9 or 10, comprising:
acquiring an image to be displayed within a frame time;
judging whether the image to be displayed in the current frame and the image in the previous frame have the same image or not;
when the image to be displayed in the frame is different from the image in the previous frame, determining the time for inputting a first signal to the first control signal end and the time for inputting a second signal to the second control signal end according to the time required by the grid line scanning of the area corresponding to the different image;
when the image to be displayed in the current frame and the image in the previous frame have the same image, determining the time for inputting the second signal to the first control signal end and the time for inputting the first signal to the second control signal end according to the time required by the grid line scanning of the region corresponding to the same image in the current frame.
12. A display device comprising the array substrate according to claim 9 or 10.
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