CN108363650A - A kind of system and method that multi node server automatically controls JTAG topologys - Google Patents
A kind of system and method that multi node server automatically controls JTAG topologys Download PDFInfo
- Publication number
- CN108363650A CN108363650A CN201810015265.7A CN201810015265A CN108363650A CN 108363650 A CN108363650 A CN 108363650A CN 201810015265 A CN201810015265 A CN 201810015265A CN 108363650 A CN108363650 A CN 108363650A
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- China
- Prior art keywords
- jtag
- node
- chip
- node chip
- topologys
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3048—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the topology of the computing system or computing system component explicitly influences the monitoring activity, e.g. serial, hierarchical systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
Abstract
The present invention discloses a kind of system and method that multi node server automatically controls JTAG topologys, is related to server system design field, and obtaining each node chip automatically by the top layer monitoring management system of multi node server powers on or working condition；According to actual conditions adjust automatically JTAG topological structures；TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not power on node chip and be removed from JTAG topological structures so that JTAG link normally accesses.The present invention can ensure under each open state of multi node server, and each node chip can be normally accessed by JTAG link；And this automatically controls the system collocation hardware circuit design of JTAG topologys, realizes intelligent, controllable inhibition and generation, global design novelty, installation and deployment are simple, have preferable popularizing value.
Description
Technical field
The present invention relates to server system design field, specifically a kind of multi node server automatically controls JTAG and opens up
The system and method flutterred.
Background technology
JTAG(Joint Test Action Group；Joint test working group) it is a kind of international standard test protocol
（IEEE 1149.1 is compatible with）, tested for chip interior.Majority high-grade device all supports JTAG protocol at present, in device inside
Definition TAP tests access mouth, are tested internal node by special jtag test tool.Jtag test allows multiple devices
Part is cascaded by jtag interface, forms a JTAG chain, and each device is tested in realization respectively.
In multipath server or blade server, system can be divided into multiple design of node.In order to reduce design cost,
By multistage monitoring management system, the RAS characteristics of system are improved, you can by property (Reliability), availability
(Availability) and serviceability (Serviceability).According to EEE.1149 agreements, a JTAG topology has multiple
When equipment, using daisy topology as a result, multiple equipment is conspired to create ring, accessed by an interface.As shown in Fig. 1, with 4
For equipment, JTAG signal is generally by four signals：TCK, TMS, TDI, TDO are formed, respectively clock, model selection, data
Input and DOL Data Output Line.Wherein, TCK and tms signal use daisy topology, TDI and TDO signal to need to conspire to create ring use.
In multi node server, the power-up state of each node is uncertain, and it is standby that there are part of nodes, idle situation.If wherein
The chip of one or more nodes does not power on or when operation irregularity, and the equipment of entire chain road all will be unable to access.
Invention content
The present invention is directed to the demand and shortcoming of current technology development, provides and is automatically controlled in a kind of multi node server
The design method of JTAG topologys.
The method that a kind of multi node server of the present invention automatically controls JTAG topologys solves above-mentioned technical problem and uses
Technical solution it is as follows：The method that the multi node server automatically controls JTAG topologys, realization process include：
Step 1 obtains each node chip by the top layer monitoring management system of multi node server and powers on or work shape automatically
State；
Step 2, jtag interface connects jtag test tool, according to actual conditions adjust automatically JTAG topological structures；
TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not power on node chip from JTAG topological structures
Middle removal so that JTAG link normally accesses.
Specifically, the step 1,
The top layer monitoring management system of multi node server by monitoring nodes manage system obtain each node chip power on or
Working condition.
Specifically, the step 2,
If top layer monitoring management system knows that node chip powers on normal work, the corresponding SWITCH cores of the node chip are controlled
Piece so that the TDI signal of JTAG is connected to the node chip, and the TDO signal that node chip exports is transmitted to next
SWITCH chips.
Specifically, the step 2,
If top layer monitoring management system is known node chip and do not powered on or operation irregularity, it is corresponding to control the node chip
SWITCH chips so that the TDI signal of JTAG skips the node chip, the SWITCH being directly transferred to before next node chip
Chip waits for this SWITCH chip to continue to select；Until the last one node chip, topological from JTAG by all not upper electrical chips
It is removed in structure.
Specifically, the SWITCH chips concentrated setting of the jtag interface and each node chip is in a signal plate
On.
The invention also provides the system that a kind of multi node server automatically controls JTAG topologys, system architecture includes：
Top layer monitoring management system, be responsible for it is automatic obtain each node chip of multi node server power on or working condition；
Node chip is the operating die in each node, is connected in JTAG topology links；
Jtag interface is connect for connecting jtag test tool, and with each node chip in JTAG topologys chain road；
Each node chip is obtained automatically by the top layer monitoring management system of multi node server to power on or working condition, according to
Actual conditions adjust automatically JTAG topological structures；TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not
It powers on node chip to remove from JTAG topological structures so that JTAG link normally accesses.
Specifically, the system that the multi node server automatically controls JTAG topologys further includes monitoring nodes management system,
The top layer monitoring management system connects each monitoring nodes and manages system, while monitoring nodes management system connection monitors its section
Point chip, top layer monitoring management system is powered on by each node chip of monitoring nodes management system acquisition or working condition.
Specifically, the system that the multi node server automatically controls JTAG topologys, corresponding each node chip is provided with
SWITCH chips；If node chip is in and powers on normal operating conditions, its corresponding SWITCH chip is controlled so that JTAG's
TDI signal is connected to the node chip, and the TDO signal that the node chip exports is transmitted to next SWITCH chips；
Specifically, the system that the multi node server automatically controls JTAG topologys, corresponding each node chip is provided with
SWITCH chips；If node chip is in and does not power on or operation irregularity state, the corresponding SWITCH chips of controller so that
The TDI signal of JTAG skips the node chip, is directly transferred to the corresponding SWITCH chips of next node chip, and waiting for should
SWITCH chips continue to select；Until the last one node chip, all not upper electrical chips are removed from JTAG topological structures.
Specifically, the jtag interface and the corresponding SWITCH chips concentrated setting of each node chip are believed at one
On number plate.
The system and method that a kind of multi node server of the present invention automatically controls JTAG topologys, compared with prior art
It has an advantageous effect in that：The present invention can be used for multi node server signal backplane monitoring management scheme, pass through server top layer
Monitoring management system adjust automatically JTAG topology links, it is ensured that JTAG link positive frequentation under multi node server open state
It asks；And the system collocation hardware circuit design for automatically controlling JTAG topologys proposed, realize that intelligence, controllable inhibition and generation are integrally set
Meter is novel, and installation and deployment are simple, has preferable popularizing value.
Description of the drawings
Illustrate the embodiment of the present invention or technology contents in the prior art in order to clearer, below to the embodiment of the present invention
Or required attached drawing does simple introduction in the prior art.It will be apparent that attached drawing disclosed below is only the one of the present invention
Section Example to those skilled in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings, but within protection scope of the present invention.
Attached drawing 1 is current JTAG daisy topologies schematic diagram；
Attached drawing 2 is the schematic diagram for the system that 2 multi node server of embodiment automatically controls JTAG topologys.
Specific implementation mode
The technical issues of to make technical scheme of the present invention, solving and technique effect are more clearly understood, below in conjunction with tool
Body embodiment is checked technical scheme of the present invention, is completely described, it is clear that described embodiment is only this hair
Bright a part of the embodiment, instead of all the embodiments.Based on the embodiment of the present invention, those skilled in the art are not doing
All embodiments obtained under the premise of going out creative work, all within protection scope of the present invention.
Embodiment 1:
In multi node server, when part of nodes does not power on, in order to ensure the normal access of other chips on JTAG link, this
Embodiment proposes a kind of method that multi node server automatically controls JTAG topologys, is monitored first by the top layer of multi node server
The management each child node of system identification powers on or working condition, then adjust automatically JTAG topological structures, will not upper electrical nodes core
Piece is removed from topological structure, it is ensured that JTAG link normally accesses.
The method that the present embodiment multi node server automatically controls JTAG topologys, realization process include：
Step 1 obtains each node chip by the top layer monitoring management system of multi node server and powers on or work shape automatically
State；
Step 2, jtag interface connect jtag test tool, according to actual conditions adjust automatically JTAG topological structures, realize
JTAG link normally accesses；
Specifically, since TCK in JTAG signal and tms signal do not influence JTAG topologys because segment chip does not power on, only
It is handled for TDI and TDO signal, realizes the purpose for removing not upper electrical chip from JTAG topology links.JTAG signal
In TDI and TDO signal do corresponding BYPASS processing, node chip will not powered on and removed from JTAG topological structures, in turn
Ensuring that all chips are to power on normal operating conditions in JTAG link, it is ensured that the TDI and TDO signal link in JTAG are unimpeded,
The chip of each working node on JTAG link can be accessed at any time.
The present embodiment also proposed a kind of system that multi node server automatically controls JTAG topologys, technical solution and reality
Applying the method that 1 multi node server of example automatically controls JTAG topologys can mutually refer to, and system architecture includes：
Top layer monitoring management system is the top layer monitoring management system of multi node server, is responsible for obtaining each node core automatically
Piece power on or working condition；
Node chip is the operating die in each node, is connected in JTAG topology links；
Jtag interface is connect for connecting jtag test tool, and with each node chip in JTAG topologys chain road；
Each node chip is obtained automatically by the top layer monitoring management system of multi node server to power on or working condition, according to
Actual conditions adjust automatically JTAG topological structures realize that JTAG link normally accesses.
Specifically, the TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not power on node chip from
It is removed in JTAG topological structures so that all chips are to power on normal operating conditions in JTAG link, it is ensured that JTAG is visited at any time
Ask the chip of each node in link.
Embodiment 2：
A kind of multi node server method for automatically controlling JTAG topologys that the present embodiment proposes, be the present invention another specifically
Embodiment, it is each in JTAG link on the basis of 1 multi node server of embodiment automatically controls the method for JTAG topologys
SWITCH chips are set at node chip, and according to the state that works on power of node chip, JTAG is by the selection of SWITCH chips
It is no to be connected to the node chip, and then realize the purpose for removing not upper electrical chip from JTAG topological structures, increase this hair
The practicability and feasibility of bright technical solution.
The method that the present embodiment multi node server automatically controls JTAG topologys, specific implementation process include：
Step 1 obtains each node chip by the top layer monitoring management system of multi node server and powers on or work shape automatically
State；
Specifically, the top layer monitoring management system of multi node server, which connects each monitoring nodes, manages system, monitoring nodes pipe
System monitoring its node chip is managed, system is managed by monitoring nodes and obtains each node chip and power on or working condition；
Step 2, jtag interface connect jtag test tool, according to actual conditions adjust automatically JTAG topological structures, realize JTAG
Link normally accesses；
Specifically, if top layer monitoring management system knows that node chip powers on normal work, SWITCH chips are controlled so that
The TDI signal of JTAG is connected to the node chip, and the TDO signal that node chip exports is transmitted to next SWITCH cores
Piece；
If top layer monitoring management system is known node chip and do not powered on or operation irregularity, SWITCH chips are controlled so that JTAG
TDI signal skip the node chip, be directly transferred to the SWITCH chips before next node chip, wait for this SWITCH core
Piece continues to select；Until the last one node chip, all not upper electrical chips is removed from JTAG topological structures, it is ensured that every time
Under open state, each node chip can be normally accessed by JTAG link.
The method that the present embodiment multi node server automatically controls JTAG topologys, jtag interface and each node chip
SWITCH chips can be with concentrated setting on a signal plate, which is pcb board card, and whole convenient for this method is realized,
Convenient for design, development cost is reduced.
The present embodiment also proposed a kind of system that multi node server automatically controls JTAG topologys, technical solution and reality
Applying the method that 2 multi node server of example automatically controls JTAG topologys can mutually refer to, and correspond to each node chip in systems
Increase SWITCH chips, the selection to TDI signal is realized by SWITCH chips.
Attached drawing 2 is the schematic diagram for the system that 2 multi node server of embodiment automatically controls JTAG topologys, as shown in Fig. 2,
The system further includes monitoring nodes management system, and top layer monitoring management system connects each monitoring nodes and manages system, same to time
Point monitoring management system connection monitors its node chip, and top layer monitoring management system is obtained each by monitoring nodes management system
Node powers on or working condition；
SWITCH chips are arranged in corresponding each node chip, if node chip, which is in, powers on normal operating conditions, it is right to control its
The SWITCH chips answered so that the TDI signal of JTAG is connected to the node chip, and the TDO signal that the node chip is exported
It is transmitted to next SWITCH chips；
If node chip is in and does not power on or operation irregularity state, the corresponding SWITCH chips of controller so that the TDI of JTAG
Signal skips the node chip, is directly transferred to the corresponding SWITCH chips of next node chip, waits for the SWITCH chips
Continue to select；Until the last one node chip.By the above process, it is ensured that by it is all do not power on or abnormal nodes chip from
It is removed in JTAG link, it is ensured that under each open state, each node chip can be normally accessed by JTAG link.
Also, the system that the present embodiment multi node server automatically controls JTAG topologys, the jtag interface and each
The corresponding SWITCH chips of node chip can be with concentrated setting on a block signal plate, which is pcb board card.In this way,
JIAG interfaces and each node SWITCH chips are designed and developed on same board, greatly reduce design cost, while being convenient for
Installation is disposed in multi node server, is realized in multi node server and is automatically controlled JTAG topological structures.
Use above specific case elaborates the principle of the present invention and embodiment, these embodiments are
It is used to help understand core of the invention technology contents, the protection domain being not intended to restrict the invention, technical side of the invention
Case is not limited in above-mentioned specific implementation mode.Based on the above-mentioned specific embodiment of the present invention, those skilled in the art
Without departing from the principle of the present invention, any improvement and modification to made by the present invention should all fall into the special of the present invention
Sharp protection domain.
Claims (10)
1. a kind of method that multi node server automatically controls JTAG topologys, which is characterized in that realization process includes：
Step 1 obtains each node chip by the top layer monitoring management system of multi node server and powers on or work shape automatically
State；
Step 2, jtag interface connects jtag test tool, according to actual conditions adjust automatically JTAG topological structures；
TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not power on node chip from JTAG topological structures
Middle removal so that JTAG link normally accesses.
2. a kind of method that multi node server automatically controls JTAG topologys according to claim 1, which is characterized in that described
Step 1,
The top layer monitoring management system of multi node server by monitoring nodes manage system obtain each node chip power on or
Working condition.
3. a kind of method that multi node server automatically controls JTAG topologys according to claim 2, which is characterized in that described
Step 2,
If top layer monitoring management system knows that node chip powers on normal work, the corresponding SWITCH cores of the node chip are controlled
Piece so that the TDI signal of JTAG is connected to the node chip, and the TDO signal that node chip exports is transmitted to next
SWITCH chips.
4. a kind of method that multi node server automatically controls JTAG topologys according to claim 2, which is characterized in that described
Step 2,
If top layer monitoring management system is known node chip and do not powered on or operation irregularity, it is corresponding to control the node chip
SWITCH chips so that the TDI signal of JTAG skips the node chip, the SWITCH being directly transferred to before next node chip
Chip waits for this SWITCH chip to continue to select；Until the last one node chip, topological from JTAG by all not upper electrical chips
It is removed in structure.
5. stating a kind of method that multi node server automatically controls JTAG topologys according to claim 3 or 4, which is characterized in that institute
The SWITCH chips concentrated setting of jtag interface and each node chip is stated on a signal plate.
6. the system that a kind of multi node server automatically controls JTAG topologys, which is characterized in that its system architecture includes：
Top layer monitoring management system, be responsible for it is automatic obtain each node chip of multi node server power on or working condition；
Node chip is the operating die in each node, is connected in JTAG topology links；
Jtag interface is connect for connecting jtag test tool, and with each node chip in JTAG topologys chain road；
Each node chip is obtained automatically by the top layer monitoring management system of multi node server to power on or working condition, according to
Actual conditions adjust automatically JTAG topological structures；TDI and TDO signal in JTAG signal do corresponding BYPASS processing, will not
It powers on node chip to remove from JTAG topological structures so that JTAG link normally accesses.
7. the system that a kind of multi node server according to claim 6 automatically controls JTAG topologys, which is characterized in that institute
It further includes monitoring nodes management system, top layer monitoring management system to state the system that multi node server automatically controls JTAG topologys
System connects each monitoring nodes and manages system, while monitoring nodes management system connection monitors its node chip, top layer monitoring pipe
Reason system is powered on by each node chip of monitoring nodes management system acquisition or working condition.
8. the system that a kind of multi node server according to claim 7 automatically controls JTAG topologys, which is characterized in that right
Each node chip is answered to be provided with SWITCH chips；
If node chip is in and powers on normal operating conditions, its corresponding SWITCH chip is controlled so that the TDI signal of JTAG
It is connected to the node chip, and the TDO signal that the node chip exports is transmitted to next SWITCH chips.
9. the system that a kind of multi node server according to claim 7 automatically controls JTAG topologys, which is characterized in that right
Each node chip is answered to be provided with SWITCH chips；
If node chip is in and does not power on or operation irregularity state, the corresponding SWITCH chips of controller so that the TDI of JTAG
Signal skips the node chip, is directly transferred to the corresponding SWITCH chips of next node chip, waits for the SWITCH chips
Continue to select；Until the last one node chip, all not upper electrical chips are removed from JTAG topological structures.
10. the system that a kind of multi node server according to claim 8 or claim 9 automatically controls JTAG topologys, feature exist
In the jtag interface and the corresponding SWITCH chips concentrated setting of each node chip are on a signal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810015265.7A CN108363650A (en) | 2018-01-08 | 2018-01-08 | A kind of system and method that multi node server automatically controls JTAG topologys |
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| CN201810015265.7A CN108363650A (en) | 2018-01-08 | 2018-01-08 | A kind of system and method that multi node server automatically controls JTAG topologys |
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| CN108363650A true CN108363650A (en) | 2018-08-03 |
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ID=63011080
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| CN201810015265.7A Pending CN108363650A (en) | 2018-01-08 | 2018-01-08 | A kind of system and method that multi node server automatically controls JTAG topologys |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1219241A (en) * | 1995-12-19 | 1999-06-09 | 三星电子株式会社 | High impedance test mode for JTAG standard |
| CN101193326A (en) * | 2007-04-24 | 2008-06-04 | 中兴通讯股份有限公司 | Automatic testing device and method for multi-JTAG chain |
| CN102393824A (en) * | 2011-09-19 | 2012-03-28 | 浪潮电子信息产业股份有限公司 | Node asynchronous electrifying based hardware partitioning method |
| WO2012061561A2 (en) * | 2010-11-03 | 2012-05-10 | Apple Inc. | Methods and apparatus for access data recovery from a malfunctioning device |
-
2018
- 2018-01-08 CN CN201810015265.7A patent/CN108363650A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1219241A (en) * | 1995-12-19 | 1999-06-09 | 三星电子株式会社 | High impedance test mode for JTAG standard |
| CN101193326A (en) * | 2007-04-24 | 2008-06-04 | 中兴通讯股份有限公司 | Automatic testing device and method for multi-JTAG chain |
| WO2012061561A2 (en) * | 2010-11-03 | 2012-05-10 | Apple Inc. | Methods and apparatus for access data recovery from a malfunctioning device |
| CN102393824A (en) * | 2011-09-19 | 2012-03-28 | 浪潮电子信息产业股份有限公司 | Node asynchronous electrifying based hardware partitioning method |
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Application publication date: 20180803 |