CN108336042A - A kind of 3-D stacks chip SiP encapsulation - Google Patents
A kind of 3-D stacks chip SiP encapsulation Download PDFInfo
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- CN108336042A CN108336042A CN201711435614.2A CN201711435614A CN108336042A CN 108336042 A CN108336042 A CN 108336042A CN 201711435614 A CN201711435614 A CN 201711435614A CN 108336042 A CN108336042 A CN 108336042A
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- Prior art keywords
- hole
- substrate
- heat conduction
- chip
- stacks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of 3-D stacks chip SiP encapsulation, several heat conduction through-holes that regular hexagon is arranged by cellular topology are provided on the substrate each time or transition vector of the encapsulating structure.These heat conduction through-holes can cover every laminar substrate, and according to the contact of the metal of substrate and chip, lead terminal layout, the layout of interconnection traces, plan the layout of heat conduction through-hole, select which honeycomb through-hole that will fill metal thermal conductive material such as Cu or Al, and other through-holes then keep dielectric substrate material, or rationally increase the thickness of through-hole wall between through-hole and through-hole so that through-hole wall can be interconnected as insulator with cloth metal on it.It, can be in the case where avoiding chip short circuit since cellular arrangement can maximally utilize substrate area so that heat conductivility maximizes.
Description
Technical field
The present invention relates to chip package heat dissipation technology, more particularly to a kind of three-dimensional S iP package cooling technologies.
Background technology
In recent years, three-dimension packaging broke through the concept of traditional planar package, and packaging efficiency is up to 200% or more.It makes list
Multiple chips can be stacked in a packaging body, realize the multiplication of memory capacity, and industry is referred to as laminated type three-dimension packaging；Its
Secondary, it significantly shortens chip direct interconnection, interconnection length, and signal transmission obtains faster and be disturbed smaller；Moreover it will
Multiple and different functional chips are stacked, and single package body is made to realize more functions, new to form System on Chip/SoC encapsulation
Thinking；Finally, using the advantages that chip of three-dimension packaging is also low in energy consumption, speed is fast, this make electronics and IT products size and
Weight reduces decades of times.Possess unrivaled technical advantage just because of three-dimension packaging, in addition multimedia and wireless communication are set
Standby use demand just makes three-dimension packaging mode possess wide development space.
However, since three-dimension packaging is the stacked multilayer IC chip in a smaller packaging body, so three-dimension packaging
Heat dissipation problem is especially prominent.Currently, the main flow direction of IC package is towards more large chip, more ports I/O, higher circuit
Density and more preferably reliability, improving current densities means the power density of increase system.Using three-dimension packaging
The component of technology manufacture, high packing density will necessarily cause encapsulation single while the power density for making device improves
The heat that position volume accommodates increases.Under normal circumstances, the failure of device is often closely related with its operating temperature.Data shows
The operating temperature of device often increases 10 DEG C, and crash rate doubles.Unreasonable thermal design will induce a series of reliable
Such as there is hot-spot, temperature distributing disproportionation etc. in sex chromosome mosaicism.Therefore, component is manufactured using 3D encapsulation technologies, it just must be conscientious
Consider the radiating treatment problem of packaging body.
The heat dissipation problem that three-dimensional stacked chip SiP (System in Package) encapsulating structure generates is mainly chip stack
Poststack calorific value will increase, but heat dissipation area not relative increase, therefore heat generation density greatly improves, and mutual due to heat source
It is close, thermal coupling enhancing, to cause even more serious heat problem；3-D stacks SiP encapsulation according to substrate heat dissipation it is bad,
Also it will produce serious heat problem.Therefore 3-D stacks SiP encapsulation needs the heat dissipation design of higher efficiency.
3-D stacks SiP packaged types are different from conventional package mode, under Natural Convection Conditions, 3-D stacks chip envelope
The heat of dress mainly passes downwardly through PCB or ceramic substrate transmits road environment space, if 3-D stacks encapsulation only dissipates bottom
Heat can not obtain satisfactory effect, that layer of chip temperature by near-bottom can only be made even if bottom surface adds radiator
Degree declines, and undesirable to the reducing effect of inside chip especially top layer chip temperature, and heat analysis is the result shows that the SIP stacked
Its high-temperature temperature value concentrates near chip, and chip stacks that quantity is more, and hot arraign topic is more serious, more high-rise chip due to
Natural Heat Convection effect is poor, causes surface temperature height.
Since three-dimension packaging structural volume is limited, heat dissipation design is relatively difficult, therefore how to utilize encapsulation certainly
The characteristic of body structure improves heat-sinking capability, will directly determine the quality of SiP Stacked Die Packaging performances.
As shown in Figure 1, three-dimensional S iP laminated packaging structures are carrier laminates.Carrier laminate technology is drawn by multilager base plate
Line terminals carry out lamination and realize three-dimensional connection.Carrier material is typically resin, ceramics and silicon.It, be from interior for SiP encapsulation
Portion spreads out of the heat of high-rise chip, it is necessary to shorten heat-transfer path or reduce path thermal resistance.If multilayer laminated encapsulating structure
Substrate heat conductivity is low, then thermal resistance will be very big, and the heat dissipation design of substrate just seems relatively important.
Invention content
In order to solve the above technical problems, the embodiment of the present invention is designed to provide a kind of raising 3-D stacks chip SiP
The heat dissipation technology of package cooling performance.
An embodiment of the present invention provides a kind of 3-D stacks chip SiP encapsulation, and each layer of chip is all fixedly connected on substrate
Or on transition vector, several heat conduction through-holes are provided on the substrate or transition vector.
Further, the heat conduction through-hole is regular hexagon structure, from the upper surface trepanning of the substrate or transition vector
To lower surface, through the entire substrate or transition vector.
Further, the heat conduction through-hole is arranged on two dimensional surface by cellular topology.
Further, the heat conduction through-hole can fill Heat Conduction Material, and the Heat Conduction Material is Cu or Au.
Further, the area of the heat conduction through-hole by cellular topology arrangement is more than chip pedestal area.
Further, the heat conduction through-hole covers every layer of substrate or transition vector, is filled out in the heat conduction through-hole of part
Fill metal thermal conductive material.
Further, the through-hole wall between the heat conduction through-hole is substrate insulating materials, and thickness can be according to mutual on substrate
Connect the width of cabling to determine so that through-hole wall can be interconnected as insulator with cloth metal on it.
The present invention provides a kind of 3-D stacks chip SiP encapsulation, the substrates each time or transition vector of the encapsulating structure
On be provided with several heat conduction through-holes that regular hexagon is arranged by cellular topology.These heat conduction through-holes can cover every laminar substrate, and
According to the contact of the metal of substrate and chip, lead terminal layout, the layout of interconnection traces, the layout of heat conduction through-hole, selection are planned
Which honeycomb through-hole will fill metal thermal conductive material such as Cu or Al, and other through-holes then keep dielectric substrate material, or rationally
Increase the thickness of through-hole wall between through-hole and through-hole so that through-hole wall can be interconnected as insulator with cloth metal on it.Due to
Cellular arrangement can maximally utilize substrate area, therefore can be in the case where avoiding chip short circuit so that heat conductivility is maximum
Change.
Description of the drawings
Fig. 1 is existing three-dimensional S iP carrier laminates encapsulating structure schematic diagram；
Fig. 2 is the substrate heat conduction through-hole overhead view in the embodiment of the present invention；
Fig. 3 is the substrate heat conduction through-hole partial top view in the embodiment of the present invention；
Fig. 4 is the three-dimension packaging sectional view for being provided with heat conduction through-hole in the embodiment of the present invention；
Wherein：1- heat conduction through-holes.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
In order to improve the heat dissipation performance of laminated chips, and original encapsulation design will not be destroyed, increase additional cooling fin, this
Inventive embodiments propose to radiate to manufacture multiple hexahedrons to via holes of substrate in the way of honeycomb arrangement on every laminar substrate
The design method of through-hole, makes heat dissipation significantly improve.
Design such as Fig. 2 of cellular topology through-hole is carried out on each laminar substrate of 3-D stacks chip SiP encapsulating structures
It is shown.Heat conduction through-hole of the present invention is covered per laminar substrate or transition vector, and is contacted, drawn according to the metal of substrate and chip
Line terminals layout, the layout of interconnection traces, plan the layout of heat conduction through-hole, select which honeycomb through-hole that will fill metal heat-conducting material
Material such as Cu or Al, and it is the substrate heat conduction through-hole part in the embodiment of the present invention that other through-holes, which then keep dielectric substrate material, Fig. 3,
Vertical view carries out the selection of heat conduction through-hole according to actual chip and substrate connection mode, avoids short circuit metal.In wherein Fig. 3
The heat conduction through-hole of metal is filled in heat conduction through-hole marked as 1, remaining through-hole is substrate isolation material, there may be chip thereon
Metal contact with substrate or cabling.
In addition, the through-hole wall between through-hole and through-hole is substrate insulating materials, thickness can be according to interconnection traces on substrate
Width determine so that through-hole wall can interconnect as insulator with cloth metal on it so that adjacent through-holes are that heat conduction is logical
Hole maximally utilizes substrate area, and the encapsulation sectional view is as shown in Figure 4.
Heat dissipation technology provided by the invention is three be all fixedly connected on for each layer of chip on substrate or transition vector
Laminated chips SiP encapsulation is tieed up, several heat conduction through-holes are provided on the substrate or transition vector.
Heat conduction through-hole of the present invention is regular hexagon structure, from the upper surface trepanning of substrate or transition vector to following table
Entire substrate is run through in face, is arranged by cellular topology on the two dimensional surface of substrate.
Heat conduction through-hole of the present invention, the through-hole wall between through-hole and through-hole is substrate insulating materials, and thickness can root
It is determined according to the width of interconnection traces on substrate so that through-hole wall can be interconnected as insulator with cloth metal on it.
Using the heat dissipation technology of the embodiment of the present invention, by opened on substrate cellular topology through-hole in the way of maximum limit
Degree contacts and connects up additional area to carry out the heat dissipation of high-rise chip using substrate with chip metal, need not increase additional
Heat dissipation plug-in unit.It, can be in the feelings for avoiding chip short circuit since cellular topology arrangement can maximally utilize substrate area
Under condition so that heat conductivility maximizes.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of 3-D stacks chip SiP encapsulation, which is characterized in that each layer of chip is all fixedly connected on substrate or transition vector
On, several heat conduction through-holes are provided on the substrate or transition vector.
2. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 1, which is characterized in that the heat conduction through-hole is just
Hexgonal structure is carried from the upper surface trepanning of the substrate or transition vector to lower surface through the entire substrate or transition
Body.
3. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 1, which is characterized in that the heat conduction through-hole is two
It is arranged by cellular topology on dimensional plane.
4. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 1, which is characterized in that the heat conduction through-hole can be with
Heat Conduction Material is filled, the Heat Conduction Material is Cu or Au.
5. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 3, which is characterized in that described to press cellular topology knot
The area of the heat conduction through-hole of structure arrangement is more than chip pedestal area.
6. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 1, which is characterized in that the heat conduction through-hole covering
Every layer of substrate or transition vector, the part heat conduction through-hole is interior to fill metal thermal conductive material.
7. being encapsulated according to a kind of 3-D stacks chip SiP described in claim 1, which is characterized in that between the heat conduction through-hole
Through-hole wall be substrate insulating materials, thickness can determine according to the width of interconnection traces on substrate so that through-hole wall conduct
Insulator can be interconnected on it with cloth metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711435614.2A CN108336042A (en) | 2017-12-26 | 2017-12-26 | A kind of 3-D stacks chip SiP encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711435614.2A CN108336042A (en) | 2017-12-26 | 2017-12-26 | A kind of 3-D stacks chip SiP encapsulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108336042A true CN108336042A (en) | 2018-07-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711435614.2A Pending CN108336042A (en) | 2017-12-26 | 2017-12-26 | A kind of 3-D stacks chip SiP encapsulation |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523664A (en) * | 2003-02-21 | 2004-08-25 | ��ʽ���綫֥ | Packaging substrate and inversion type semiconductor device |
| CN103119703A (en) * | 2010-09-23 | 2013-05-22 | 高通Mems科技公司 | Integrated passives and power amplifier |
| CN205845951U (en) * | 2016-07-22 | 2016-12-28 | 肇庆市欧迪明科技有限公司 | A kind of baseplate material and chip three-dimensional electric heating attachment structure |
-
2017
- 2017-12-26 CN CN201711435614.2A patent/CN108336042A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523664A (en) * | 2003-02-21 | 2004-08-25 | ��ʽ���綫֥ | Packaging substrate and inversion type semiconductor device |
| CN103119703A (en) * | 2010-09-23 | 2013-05-22 | 高通Mems科技公司 | Integrated passives and power amplifier |
| CN205845951U (en) * | 2016-07-22 | 2016-12-28 | 肇庆市欧迪明科技有限公司 | A kind of baseplate material and chip three-dimensional electric heating attachment structure |
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Application publication date: 20180727 |
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