CN109860131A - A kind of system-in-package structure with interior radiator - Google Patents
A kind of system-in-package structure with interior radiator Download PDFInfo
- Publication number
- CN109860131A CN109860131A CN201910222099.2A CN201910222099A CN109860131A CN 109860131 A CN109860131 A CN 109860131A CN 201910222099 A CN201910222099 A CN 201910222099A CN 109860131 A CN109860131 A CN 109860131A
- Authority
- CN
- China
- Prior art keywords
- cover board
- heat sink
- substrate
- package structure
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention discloses a kind of system-in-package structures with interior radiator, it is heat sink by being arranged on chip, it is heat sink to be connected with cover board, and use same material, so that chip is from the original downward heat dissipation channel for passing through substrate package, and increase the heat sink heat dissipation channel for directly arriving cover board.Such encapsulating structure is taken, heat dissipation channel of the local heat source with upper and lower both direction in SiP module is made, thermal resistance can be reduced effectively by the heat derives on chip heat source, improve radiating condition.
Description
Technical field
The invention belongs to hybrid semiconductor integrated circuit fields, and in particular to a kind of system-level envelope with interior radiator
Assembling structure.
Background technique
With the development of SiP technology, the packing density of system in package product is higher and higher, large scale processing device class chip
Extensive use in SiP product, so that the power consumption on unit area dramatically increases.Reliable thermal design is carried out, power consumption is reduced
It is that SiP class product must solve the problems, such as.Current heat dissipating method is that local heat source is thermally conductive to shell by substrate and shell.By
In will by two different materials could by heat derives, thermal resistance reduce it is limited, especially to the biggish chip of some power consumptions,
This mode not can effectively solve heat dissipation problem.
Summary of the invention
The purpose of the present invention is to overcome the above shortcomings and to provide a kind of system-in-package structure with interior radiator,
Make heat dissipation channel of the local heat source with upper and lower both direction in SiP module, thermal resistance is effectively reduced, improves radiating condition.
In order to achieve the above object, the present invention includes the encapsulating housing of shell and cover board composition, is fixed in encapsulating housing
Substrate, is connected with several chips on substrate, and chip upper surface is coated with hot interface coating, cover board lower part be connected with it is several heat sink,
The heat sink hot interface coating on corresponding chip contacts, heat sink identical as the material of cover board.
Heat sink and cover board material is AlSiC.
The material of substrate is LTCC low-temp ceramics, and the inside of substrate has several layers metal line, and upper surface of base plate has
Metal conduction band figure for component assembling.
The top sintering of shell has for cutting down metal frame with cover plate for sealing.
It is curved that position on cover board close to shell is provided with stress release.
Heat sink lateral cross-sectional dimension is identical as corresponding chip upper surface size.
Using laser sealing encapsulation between shell and cover board.
Compared with prior art, the present invention is heat sink by being arranged on chip, heat sink to connect with cover board, and using same
Material so that chip is from the original downward heat dissipation channel for passing through substrate package, and increases heat sink directly logical to the heat dissipation of cover board
Road.Such encapsulating structure is taken, heat dissipation channel of the local heat source with upper and lower both direction in SiP module is made, it can be effective
By the heat derives on chip heat source, reduce thermal resistance, improve radiating condition.
Further, it is curved that it is provided with stress release on cover board of the invention, each site location mismatch can be reduced and brought
Stress.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention；
Fig. 2 is the structural schematic diagram of the embodiment of the present invention；
Wherein, 1, shell；2, cover board；3, chip；4, heat sink；5, hot interface coating；6, substrate；7, stress release is curved.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.
Referring to Fig. 1, the present invention includes the encapsulating housing that shell 1 and cover board 2 form, the top sintering of shell 1 have for
What cover board 2 sealed cuts down metal frame, and the position of close shell 1 is provided with stress release curved 7 on cover board 2, fixes in encapsulating housing
There is substrate 6, several chips 3 is connected on substrate 6,3 upper surface of chip is coated with hot interface coating 5, if 2 lower part of cover board is connected with
Xeothermic heavy 4, heat sink 4 contact with the hot interface coating 5 on correspondence chip 3, heat sink 4 lateral cross-sectional dimension and table on corresponding chip 3
Face size is identical, and heat sink 4 is identical as the material of cover board 2.The material of substrate 6 is LTCC low-temp ceramics, if the inside of substrate 6 has
Dried layer metal line, 6 upper surface of substrate has the metal conduction band figure for component assembling, for SiP system-level blocks
The multilager base plate number of plies can be from several layers of to 40 layers.
The encapsulating structure of SiP generally uses multilager base plate to be assembled in package casing, and cover board 2 can generally be cut down or metal
Material, shape are flat rectangular or square, and cover board 2 can be encapsulated on shell using forms such as laser sealings.The present invention
The encapsulating structure of proposition fits together heat sink 4 and the cover board 2 that are used to radiate in inside modules local heat source, and junction is adopted
It is connected with the hot interface coating 7 of high thermal conductivity, encapsulation is using laser sealing encapsulation.
1 basis material of shell is refractory ceramics, can be Custom Prosthesis shell, have multi-layer metal wiring in 1 substrate of shell
With the metal conduction band figure assembled for component；It may be universal external case, there is no metal conduction band figure, substrate in substrate
It is made of the ceramics with multi-layer metal wiring, the leading wire bonding being connected with outer pin can be reserved in substrate and is referred to.Both
The surrounding of the envelope substrate of form is the frame of ceramic material, and the top of frame, which is sintered to have, can cut down metal frame for cover plate for sealing.Shell
Leading-out form it is unlimited, can be the forms such as pin grid array, ball grid array or column gate array.
Can there are the biggish chip 3 of one or more power consumptions, the heat source as inside modules inside SiP system-level blocks.
For this kind of chip 3 due to process performance height, power consumption is larger, and leading foot is also relatively more, and majority is designed to that the mode of flip chip bonding assembles.For
Convenient for the heat dissipation of this chip 3, increases heat dissipation channel, special heat sink 4, this heat sink 4 are designed above chip be different from
Traditional radiator selects the material with the expansion coefficient similar of Si due to being directly connected to chip 3 on material
Material.For the ease of heat sink and cover board 2 connection, the material selection of cover board 2 and heat sink 4 same material.Heat sink 4 size and every
The size of a chip 3 is related, big heat sink 4 design of 3 size of chip it is big, small heat sink 4 design of chip size it is small.It considers
Heat sink 4 thermally conductive requirement, the AlSiC of heat sink 4 material selection high thermal conductivity.
Hot interface coating 5, so that junction comes into full contact with, avoids making since gap is excessive for connecting chip 3 and heat sink 4
At heating conduction decline.
Cover board 2 is selected and heat sink 4 same materials, and cover board 2 uses laser sealing encapsulation.2 size of cover board and 1 four wall of shell
On can to cut down metal frame onesize.Due to increasing heat sink the 4 of 3 heat transmission of chip in encapsulating structure, and these heat sink 4 directly with
Cover board 2 is connected, and due to heat sink 4 presence, can generate deformation when 2 surface of cover board applies stress, each in module in order to reduce
A site location mismatch bring stress needs machining stress release is curved to solve the problems, such as this close to can cut down on cover board at frame.
Embodiment:
Referring to fig. 2, shell of the invention uses ceramic package, and substrate 6 is bonded in 1 intracavity bottom of shell, the big core of power consumption
Piece 3 is welded on substrate 6 after planting column, and there are also the elements such as remaining laminated chips, resistance, capacitor, magnetic bead inside SiP.On chip 3
Using hot interface coating 5 assemble heat sink 4, heat sink 4 and cover board 2 using same material.In cover board 2 close to design stress at frame can be cut down
Curved reduction position mismatch bring stress influence.
Claims (7)
1. a kind of system-in-package structure with interior radiator, which is characterized in that formed including shell (1) and cover board (2)
Encapsulating housing, be fixed with substrate (6) in encapsulating housing, be connected on substrate (6) several chips (3), chip (3) upper surface applies
It is covered with hot interface coating (5), cover board (2) lower part is connected with several heat sink (4), heat sink (4) and the hot interface on corresponding chip (3)
Coating (5) contact, heat sink (4) are identical as the material of cover board (2).
2. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that heat sink
It (4) is AlSiC with the material of cover board (2).
3. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that substrate
(6) material is LTCC low-temp ceramics, and the inside of substrate (6) has several layers metal line, and substrate (6) upper surface, which has, to be used for
The metal conduction band figure of component assembling.
4. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that shell
(1) top sintering has for cutting down metal frame with what cover board (2) sealed.
5. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that cover board
(2) it is curved (7) that the position on close to shell (1) is provided with stress release.
6. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that heat sink
(4) lateral cross-sectional dimension is identical as corresponding chip (3) upper surface size.
7. a kind of system-in-package structure with interior radiator according to claim 1, which is characterized in that shell
(1) using laser sealing encapsulation between cover board (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910222099.2A CN109860131A (en) | 2019-03-22 | 2019-03-22 | A kind of system-in-package structure with interior radiator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910222099.2A CN109860131A (en) | 2019-03-22 | 2019-03-22 | A kind of system-in-package structure with interior radiator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109860131A true CN109860131A (en) | 2019-06-07 |
Family
ID=66901630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910222099.2A Pending CN109860131A (en) | 2019-03-22 | 2019-03-22 | A kind of system-in-package structure with interior radiator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109860131A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110412700A (en) * | 2019-07-26 | 2019-11-05 | 西安微电子技术研究所 | A kind of integrated electronics high-speed optical interconnection module integrated morphology and integrated approach |
| CN110957288A (en) * | 2019-11-25 | 2020-04-03 | 北京遥测技术研究所 | Heat dissipation device and method for high-power device |
| CN111564430A (en) * | 2020-06-19 | 2020-08-21 | 青岛歌尔智能传感器有限公司 | System-in-package structure and electronic device |
| CN112071814A (en) * | 2020-09-09 | 2020-12-11 | 深圳市明锐信息科技有限公司 | Chip packaging system and chip packaging process thereof |
| CN112185916A (en) * | 2020-09-29 | 2021-01-05 | 西安微电子技术研究所 | Double-channel air tightness packaging structure of flip chip and technology thereof |
| WO2021195903A1 (en) * | 2020-03-31 | 2021-10-07 | 华为技术有限公司 | System in package and electronic device |
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| JPS6161449A (en) * | 1984-09-03 | 1986-03-29 | Nec Corp | Multichip ic package |
| CN1290961A (en) * | 1999-09-30 | 2001-04-11 | 国际商业机器公司 | Custum made lid for improving heat property of module by inverse mounting |
| CN1941364A (en) * | 2005-09-28 | 2007-04-04 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN102144290A (en) * | 2008-07-02 | 2011-08-03 | 阿尔特拉公司 | Flip chip overmold package |
| CN103456699A (en) * | 2013-09-29 | 2013-12-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | Integrated circuit packaging structure and packaging method thereof |
-
2019
- 2019-03-22 CN CN201910222099.2A patent/CN109860131A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6161449A (en) * | 1984-09-03 | 1986-03-29 | Nec Corp | Multichip ic package |
| CN1290961A (en) * | 1999-09-30 | 2001-04-11 | 国际商业机器公司 | Custum made lid for improving heat property of module by inverse mounting |
| CN1941364A (en) * | 2005-09-28 | 2007-04-04 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN102144290A (en) * | 2008-07-02 | 2011-08-03 | 阿尔特拉公司 | Flip chip overmold package |
| CN103456699A (en) * | 2013-09-29 | 2013-12-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | Integrated circuit packaging structure and packaging method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110412700A (en) * | 2019-07-26 | 2019-11-05 | 西安微电子技术研究所 | A kind of integrated electronics high-speed optical interconnection module integrated morphology and integrated approach |
| CN110412700B (en) * | 2019-07-26 | 2022-05-17 | 西安微电子技术研究所 | Integrated structure and integrated method of integrated electronic high-speed optical interconnection module |
| CN110957288A (en) * | 2019-11-25 | 2020-04-03 | 北京遥测技术研究所 | Heat dissipation device and method for high-power device |
| WO2021195903A1 (en) * | 2020-03-31 | 2021-10-07 | 华为技术有限公司 | System in package and electronic device |
| CN111564430A (en) * | 2020-06-19 | 2020-08-21 | 青岛歌尔智能传感器有限公司 | System-in-package structure and electronic device |
| CN112071814A (en) * | 2020-09-09 | 2020-12-11 | 深圳市明锐信息科技有限公司 | Chip packaging system and chip packaging process thereof |
| CN112185916A (en) * | 2020-09-29 | 2021-01-05 | 西安微电子技术研究所 | Double-channel air tightness packaging structure of flip chip and technology thereof |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190607 |
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| RJ01 | Rejection of invention patent application after publication |