CN108288590A - Convex block packaging method - Google Patents
Convex block packaging method Download PDFInfo
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- CN108288590A CN108288590A CN201710015091.XA CN201710015091A CN108288590A CN 108288590 A CN108288590 A CN 108288590A CN 201710015091 A CN201710015091 A CN 201710015091A CN 108288590 A CN108288590 A CN 108288590A
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- convex block
- opening
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- packaging method
- underbump metallization
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1451—Function
- H01L2224/14515—Bump connectors having different functions
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The present invention provides a kind of convex block packaging method comprising：Front-end devices are provided, underbump metallization layer is formed on the front-end devices surface；It is formed for the convex block of encapsulation on the underbump metallization layer and the virtual convex block for improving the convex block uniformity, the virtual convex block is less than the sectional area of the virtual convex block with the contact area of the underbump metallization layer；The part that the underbump metallization layer is located at except the convex block and virtual convex block bottom is removed, while the virtual convex block being made to peel off.The convex block packaging method can improve the coplanarity and uniformity of bump height.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of convex block packaging method.
Background technology
As portable and high-performance microelectronics product develops to short, small, light, thinning direction, traditional routing mode (Wire
Bonding) encapsulation technology combined with various base material as chip has been unable to meet the demand of present consumption electronic product, take and
Convex block encapsulation (bumping) instead of becomes the key technology of wafer-level packaging.In convex block packaging technology, it is mostly used the side of plating
Method is connected up or is formed again convex block.However, with the development of semiconductor technology, the critical size of semiconductor devices is constantly contracting
Small, correspondingly package dimension also constantly reduces.It is corresponding to be, inner I/O (input and output) number of lugs of a chip (die)
Mesh is also more and more, therefore the requirement for plated bumps height coplanarity and uniformity is also higher and higher.According to electroplating process
Characteristic, the uniformity (the plating area in unit area) of convex block distribution can influence the uniformity of plated bumps height.Therefore,
It is not well-proportioned design for the distribution of some convex blocks, the coplanarity and uniformity of bump height can be greatly affected, example
As in one example, bumpless region is closed on (for example, imperfect chip region (ugly die area), laser labelling area (laser
Mark area)) bump height can 12 micron (um) bigger than normal value or design value.
Currently in order to improving the coplanarity and uniformity of bump height, industry is mainly by the following method：1) in design rank
Duan Jinliang by convex block distribution does uniformly, such as by way of adding virtual convex block improve convex block distribution uniformity；However by
It can not be removed in final virtual convex block, therefore have prodigious limitation in design.2) by improving the processing procedure being electroplated and equipment
Hardware capabilities improve bump height coplanarity and uniformity.These methods all cannot simply and effectively improve being total to for bump height
Face property and uniformity are of high cost, and difficulty is big or existing defects influence subsequent technique.
Therefore, it is necessary to a kind of new convex block packaging method be proposed, to overcome the above problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of convex block packaging method, can improve being total to for bump height
Face property and uniformity.
First aspect present invention provides a kind of convex block packaging method, including：Front-end devices are provided, in the front-end devices table
Face forms underbump metallization layer；The convex block and described convex for improving for encapsulation is formed on the underbump metallization layer
The contact area of the virtual convex block of block uniformity, the virtual convex block and the underbump metallization layer is less than the virtual convex block
Sectional area；The part that the underbump metallization layer is located at except the convex block and virtual convex block bottom is removed, while making institute
Virtual convex block is stated to peel off.
Illustratively, the radial dimension of the virtual convex block is less than 10 microns.
Illustratively, the virtual convex block is formed in the laser labelling area of the front-end devices and/or imperfect chip region.
Illustratively, the virtual convex block is formed in around the convex block for encapsulation, for improving the convex block
Uniformity and coplanarity.
Illustratively, the convex block packaging method further includes；Photoresist layer is formed on the underbump metallization layer；It is logical
Overexposure is developed in the first opening of formation in the photoresist layer, for exposing the bump region to be formed；By exposing,
It is developed in the photoresist layer and forms the second opening, for exposing the virtual bump region to be formed；Electroplating technology is carried out,
To form convex block in first opening simultaneously, virtual convex block is formed in second opening；The photoresist layer is removed,
Wherein, second open bottom is formed with extension so that the bottom area of the opening is less than the upper side of the opening
Product.
Illustratively, the extension is inclined on the side wall of second opening.
Illustratively, when the photoresist layer is positivity photoresist, the exposure energy for being used to form second opening is small
In the exposure energy for being used to form first opening；When the photoresist layer is negativity photoresist, it is used to form described second
The exposure energy of opening is more than the exposure energy for being used to form first opening.
Illustratively, when the photoresist layer is positivity photoresist, the focal length for being used to form second opening is more than use
In the focal length for forming first opening；When the photoresist layer is negativity photoresist, it is used to form the coke of second opening
Away from less than the focal length for being used to form first opening.
Illustratively, the convex block packaging method further includes：Cleaning step, with the remaining virtual convex block of removal.
Illustratively, the convex block and virtual convex block are soldered ball convex block..
Convex block packaging method according to the present invention, by around normal convex block or bumpless region increases virtual convex block,
To improve the uniformity of convex block distribution, and then plated bumps height coplanarity and uniformity are improved, and since these are virtual
Size of lug is smaller, and the contact area of bottom can be significantly smaller than actual size of lug, thus with underbump metallization layer
(UBM) adhesion is very weak, can be automatically moved in underbump metallization layer etching process.That is, this virtual convex block exists
Improve plated bumps high homogeneity and while coplanarity, due to that can be removed easily, final convex block will not be distributed and
Assembly has any impact, therefore can be arranged in wafer any position.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A is the step flow chart according to the convex block packaging method of an embodiment of the present invention；
Figure 1B is to be flowed according to the step of forming convex block and virtual convex block in the convex block packaging method of an embodiment of the present invention
Cheng Tu；
Fig. 2A~Fig. 2 D show virtual convex block forming process schematic diagram according to an embodiment of the present invention；
Fig. 3 shows the imperfect chip region that virtual convex block is arranged and laser labelling area；
Fig. 4 shows virtual convex block provided around the convex block for encapsulation.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with reference numeral.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Below with reference to Figure 1A, Figure 1B and Fig. 2A~Fig. 2 D to convex block packaging method according to an embodiment of the present invention
It is described in detail.
First, as shown in Figure 1A, the convex block packaging method of the present embodiment includes：
Step 101, front-end devices are provided, underbump metallization layer is formed on the front-end devices surface.
The front-end devices are the device for being formed with various circuit structures and function element.Typically, front-end devices are general
Including semiconductor substrate/wafer, active device is formed in semiconductor substrate/wafer, is formed on semiconductor substrate/wafer mutual
Even layer, is formed with passivation layer and pad at the top of interconnection layer.
Underbump metallization layer is used to make seed layer or electrode layer in follow-up convex block electroplating technology, and underbump metallization layer can
Using various suitable metal materials, such as Cu (copper), TiW (tungsten-titanium alloy), Au (gold), Ti (titanium) etc., may include
One or more layers different metal material can select suitable underbump metallization layer in concrete operations according to convex block type
(UBM, under bump meal).
Step 102, the convex block and equal for improving the convex block for encapsulation is formed on the underbump metallization layer
The virtual convex block of even property.
Convex block with package substrate for subsequently realizing fixed and being electrically connected, however the distribution of convex block is generally basede on preceding end-apparatus
The distribution of pad is designed on part, however, as previously described, because chip (die) is unevenly distributed on wafer, it is close that there are die
The region of collection, there is also centreless panel region or the imperfect region of chip (ugly die), normal convex block distribution corresponding in this way
There is also homogeneity questions, therefore when plating makes convex block, bump height uniformity and coplanarity can be caused bad, Jin Erying
Ring package quality.For this purpose, in the present embodiment, we are in bumpless region or normal convex block (convex block for being used for encapsulation) setting
Virtual convex block, with improve convex block distribution uniformity, and then plating make convex block when, can improve bump height uniformity and
Coplanarity.
In the present embodiment, virtual convex block can be formed in the laser labelling area of the front-end devices and/or imperfect core
Section can also either be formed in around the convex block for encapsulation or be formed in any position of front-end devices,
Design principle is that convex block and virtual convex block is made integrally to be evenly distributed, to plating when can improve bump height uniformity and
Coplanarity.
Illustratively, as shown in figure 3, virtual convex block is formed in the laser labelling area of the front-end devices and/or imperfect
Chip region, or as shown in Figure 4.Virtual convex block is formed in around the convex block for encapsulation, i.e., when part is for encapsulating
When being unevenly distributed of convex block, virtual convex block can be set around these convex blocks, as shown in figure 4, solid line circle table in figure
Show that the convex block for encapsulation, distribution are not that very uniformly, convex block is not arranged for right area, therefore virtual convex block is arranged on right side
(dashed circle) improves the uniformity in this region.
Further, the pad of front-end devices/connect up again (RDL) is generally formed for the convex block of encapsulation, and it is virtual convex
Block is then generally formed directly on underbump metallization layer, and there is no corresponding pads/connect up (RDL) again for same layer below, i.e.,
Virtual convex block is not used in realization and is electrically connected, and can be removed in the subsequent process.
Further, in the present embodiment, virtual convex block is generally miniature convex block, relative to the convex block for encapsulation compared with
It is small, for example, virtual convex block radial dimension be less than 10 microns.And the contact area of virtual convex block and underbump metallization layer is small
In the sectional area of the virtual convex block.Herein, the contact area of virtual convex block and underbump metallization layer refers to virtual convex
The area of block and the direct contact surface of underbump metallization layer, and the sectional area of virtual convex block refers to virtual convex block main part
Cross-sectional area or virtual convex block maximum secting area.
Step 103, the part that the underbump metallization layer is located at except the convex block and virtual convex block bottom is removed, together
When so that the virtual convex block is peeled off,
That is, underbump metallization layer etching is carried out, to remove the part except the convex block and virtual convex block bottom.Example
Property, the etching of the underbump metallization layer uses wet processing, that is, passes through suitable etching liquid, such as HF (hydrofluoric acid)
Deng.
As previously described, because in the present embodiment, virtual size of lug is smaller, and virtual convex block and underbump metallization layer
Contact area be less than the area of the virtual convex block, therefore the adhesion strength of virtual convex block and underbump metallization layer is very weak, because
This is when carrying out underbump metallization layer etching, as the underbump metallization layer around virtual convex block is removed, virtual convex block
Since adhesion strength is weaker, also occur to peel off and be removed simultaneously.
The making of convex block and virtual convex block in the convex block packaging method of the present embodiment is done further in detail with reference to Figure 1B
Thin description.
As shown in Figure 1B, in the present embodiment, the convex block and virtual convex block are formed by following step.
First, step 1020 is executed, photoresist layer is formed on the underbump metallization layer.
Positivity photoresist (such as TOK P-CA100) or negativity photoresist (for example, HD4100) may be used in photoresist layer, and leads to
The common methods such as coating are crossed to be formed on underbump metallization layer.The thickness of photoresist layer is designed as needed, herein not
It is specifically limited.
Then, step 1021 is executed, the first opening is formed in the photoresist layer by exposing, being developed in, for exposing
The bump region to be formed.
Exposure imaging use method commonly used in the art, for example, by using 193nm ArF photoetching processes expose, and by with photoetching
The corresponding developer solution of glue-line develops, that is, uses developing liquid developing corresponding with positivity photoresist or negativity photoresist (for example, positive photoresist
Developer solution TOK P7-G, developer for negative photoresist AZ-A515), photoresist layer is graphical.
Further, it is however generally that, the region of pad is formed on the first opening exposure front-end devices, these
Region is used to form the convex block for encapsulation.
Then, step 1022 is executed, the second opening is formed in the photoresist layer by exposing, being developed in, for exposing
The virtual bump region to be formed.
Exposure imaging use method commonly used in the art, for example, by using 193nm ArF photoetching processes expose, and by with photoetching
The corresponding developer solution of glue-line develops.Developing liquid developing corresponding with positivity photoresist or negativity photoresist is used, by photoetching
Glue-line is graphical.
Further, the virtual bump region, these regions are formed on the second opening exposure front-end devices
It is generally not present pad, and neighbouring convex block density is smaller or bumpless.
In the present embodiment, second open bottom is formed with extension so that the bottom area of the opening is less than
The top area of the opening.Illustratively, the extension be inclined at it is described second opening side wall on, in this way when after
When continuing the virtual convex block of formation in the second opening, virtual convex block can be formed in bottom and be undercut so that virtual convex block base contact surface
Product is significantly smaller than the area of virtual convex block.
Further, in the present embodiment, the second opening shape can pass through control photoetching process parameter realize.Example
Such as, when the photoresist layer is positivity photoresist, the exposure energy for being used to form second opening is less than the exposure of normal exposure
Light energy is less than the exposure energy for being used to form first opening in other words；When the photoresist layer is negativity photoresist, use
It is more than the exposure energy of normal exposure in the exposure energy for forming second opening, or is opened more than being used to form described first
The exposure energy of mouth.When the photoresist layer is positivity photoresist, the focal length for being used to form second opening is more than normally
Focal length, or more than the focal length for being used to form first opening；When the photoresist layer is negativity photoresist, it is used to form described
The focal length of second opening is less than normal focal length, or is used to form the focal length of first opening.
That is, in the present embodiment, made in photoresist with by lithography process parameters, such as exposure energy, focal length etc.
The two corresponding regions of opening, expose insufficient in exposure, will form foot in the second open bottom in follow-up development in this way
Portion or extension so that the second open bottom area is less than top area.
Here, the exposure energy or focal length of so-called normal exposure refer to making not having foot in second opening or stretching
Go out used exposure energy or focal length when portion.
Further, it is to be understood that forming the development operation of the first opening and the second opening can be carried out in two steps,
Can also the exposure and the second opening for completing the first opening exposure and then carry out development operation together, be formed simultaneously the
One opening and the second opening.
Then, step 1023 is executed, electroplating technology is carried out, to form convex block in first opening simultaneously, described
Virtual convex block is formed in second opening.
Specifically, according to the type of convex block, for example, golden convex block, copper pillar bumps, the suitable electrolyte of the selections such as soldered ball convex block,
Plating forms convex block and virtual convex block respectively in first opening and the second opening.
Finally, step 1024 is executed, the photoresist layer is removed.
Illustratively, such as by suitably going glue (for example, AZ400T etc.) to remove photoresist layer.
It is understood that above-mentioned steps are only an examples of convex block and virtual method for producing lug, the present invention can be with
Make above-mentioned convex block and virtual convex block using other suitable methods as needed, as long as so that virtual convex block adhesion strength compared with
Difference is easy to peel off.
Shown in Fig. 2A~Fig. 2 D, formation and peeling to this virtual convex block according to an embodiment of the invention
Process illustrates, to more fully understand the present invention.
First, as shown in Figure 2 A, front-end devices are provided, underbump metallization layer are formed on the front-end devices, in institute
It states and forms patterned photoresist layer on underbump metallization layer.
Front-end devices 200 include semiconductor substrate/wafer, and are formed in the circuit structure of semiconductor substrate/wafer, device
Part, element etc..Semiconductor substrate/wafer can be following at least one of the material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or for silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS transistor or other semiconductor devices etc..It can also be formed with isolation structure, the isolation in the semiconductor substrate
Structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
The metal interconnection structure being electrically connected with transistor is formed on semiconductor substrate/wafer.At the top of interconnection structure
It is formed with passivation layer 201.Illustratively, passivation layer 201 is, for example, silicon nitride layer.Opening for exposure pad is formed in passivation layer 201
Mouth (not shown).For succinct, region corresponding with virtual convex block is only schematically shown in Fig. 2A to Fig. 2 D, and is not shown and to be formed
The region of convex block.It is understood that passivation layer can be single or multi-layer structure.
Underbump metallization layer (UBM) is used as the seed layer or electrode layer of plated bumps.Illustratively, in the present embodiment
In, it is illustrated for making soldered ball convex block (solder bump), thus underbump metallization layer includes the first convex block bottom
Metal layer 202 and the second underbump metallization layer 203, wherein illustratively Ti layers of the first underbump metallization layer 202, second
Underbump metallization layer 203 is illustratively Cu layers.First underbump metallization layer 202 and the second underbump metallization layer 203
It can be formed by sputtering technology, to obtain good uniformity.
Patterned photoresist layer 204 exposes the region of virtual convex block to be formed.In the present embodiment, patterned photoetching
Glue-line 204 is used to expose the opening 205 in the region of virtual convex block to be formed, and 205 bottoms of opening have foot or extension 205A,
In this way so that the bottom area S1 of opening 205 is less than the top area or opening area S2 of opening 205.Illustratively, in this reality
Shi Zhong, foot or extension 205A are oblique, are formed on the side wall of 205 bottoms of opening.Patterned photoresist layer 204 or
The forming process of opening 205 is as previously mentioned, details are not described herein.
Then, as shown in Figure 2 B, virtual convex block 206 is formed in opening 205.
Illustratively, virtual convex block 206 is formed in opening 205 by electroplating technology.Illustratively, in the present embodiment
In, it includes two parts, i.e. copper post part 206A and soldered ball part that convex block/virtual convex block, which uses soldered ball convex block, i.e., virtual convex block 206,
206B.Wherein copper post part 206A is formed by electro-coppering, and soldered ball part 206B is formed by electrotinning.
It is understood that copper post part 206A and soldered ball part 206B is profile graphics in figure, and it is only illustrative,
True shape is not indicated that, the true shape of copper post part 206A and soldered ball part 206B can be with copper post part 206A and welderings in figure
Ball portion 206B is identical, also can there is also differences.
Further include flowing back, so that soldered ball convex block forms stabilization it will also be appreciated that after forming virtual convex block
The operation of alloy.
Then, as shown in Figure 2 C, patterned photoresist layer 204 is removed.
As previously mentioned, by suitably going glue (for example, AZ400T etc.) to remove patterned photoresist layer 204.
After removing photoresist layer 204, virtual convex block 206 exposes, since 205 bottoms of opening have foot or extension
205A so that the 205 bottom area S1 of being open is less than the top area or opening area S2 of opening 205, therefore virtual convex block 206
It is less than the sectional area S4 of virtual convex block with the contact area S3 of underbump metallization layer, what the sectional area S4 of virtual convex block 206 referred to
It is the cross-sectional area of 206 main part of virtual convex block or the maximum secting area of virtual convex block 206.Therefore virtual 206 bottom of convex block
Undercutting is formed, convex block 206 virtual in this way and the adhesion strength of bottom metal layers are weaker, are easy to peel off.
Finally, as shown in Figure 2 D, underbump metallization layer etching is carried out.
Specifically, underbump metallization layer is etched using suitable etching liquid, is located at void to remove underbump metallization layer
Part other than quasi- 206 bottom of convex block.Illustratively, in the present embodiment, the removal of 85 etching liquids of micro etch may be used
Part other than second 203 virtual convex block of underbump metallization layer, 206 bottom removes the first convex block bottom gold by HF etching liquids
Belong to the part other than 202 virtual convex block of layer, 206 bottom.
It is understood that on the one hand due to carry out underbump metallization layer etching when, 206 bottom of virtual convex block it is convex
Block bottom metal layers can also be corroded, on the other hand, since virtual convex block 206 and the adhesion strength of underbump metallization layer are weaker,
When the underbump metallization layer of surrounding is removed, virtual convex block can peel off automatically.
It is understood that even if in the presence of the virtual convex block not automatically removed, cleaning operation can also be then carried out, such as
The remaining virtual convex block of high pressure Scrubber operation removals will not finally have any impact in convex block distribution and assembly.
The convex block packaging method that the present embodiment proposes, by around normal convex block or bumpless region increases virtual convex block
Uniformity to improve convex block distribution can improve the uniformity and coplanarity of bump height in this way when plating forms convex block,
For example, by using the convex block packaging method of the present embodiment, the convex block for closing on the chip in bumpless region is more bigger than normal value (for example, 2
~6 microns), and use conventional method as previously mentioned, then can be 12 microns bigger than normal value or more, it can be seen that, using this implementation
The convex block packaging method that example proposes greatly improves the uniformity and coplanarity of bump height.
Further, in the convex block packaging method of the present embodiment, these virtual size of lug are smaller, such as radial ruler
It is very little to be generally less than 10 microns, and it makes photoresist generate larger foot by using the etching condition different from normal convex block
Region has a prodigious undercutting after the completion of plating, and the contact area of convex block bottom virtual in this way can be significantly smaller than actual virtual
The adhesion of size of lug, this virtual convex block and lower layer is very weak, can quilt automatically in underbump metallization layer etching process
Removal, the sordid virtual convex block in fraction place to go can be by increasing additional high pressure scrubber removals.These are special
Virtual convex block is improving the uniform of plated bumps height coplanarity and uniformity simultaneously as can be removed easily, will not
It has any impact, therefore can be designed in any position of wafer to the distribution of final convex block and assembly, in use may be used
To be arranged this virtual convex block in any desired position as needed, convex block distribution when improving plated bumps significantly is equal
Even property so that plated bumps height uniformity and coplanarity greatly improve.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of convex block packaging method, which is characterized in that including：
Front-end devices are provided, underbump metallization layer is formed on the front-end devices surface；
It is formed for the convex block of encapsulation on the underbump metallization layer and for improving the virtual convex of the convex block uniformity
Block, the virtual convex block are less than the sectional area of the virtual convex block with the contact area of the underbump metallization layer；
The part that the underbump metallization layer is located at except the convex block and virtual convex block bottom is removed, while being made described virtual
Convex block peels off.
2. convex block packaging method according to claim 1, which is characterized in that the radial dimension of the virtual convex block is less than 10
Micron.
3. convex block packaging method according to claim 1, which is characterized in that the virtual convex block is formed in the preceding end-apparatus
The laser labelling area and/or imperfect chip region of part.
4. convex block packaging method according to claim 1, which is characterized in that the virtual convex block is formed in described for sealing
Around the convex block of dress, uniformity and coplanarity for improving the convex block.
5. the convex block packaging method according to any one in claim 1-4, which is characterized in that further include；
Photoresist layer is formed on the underbump metallization layer；
The first opening is formed in the photoresist layer by exposing, being developed in, for exposing the bump region to be formed；
The second opening is formed in the photoresist layer by exposing, being developed in, for exposing the virtual bump region to be formed；
Electroplating technology is carried out, to form convex block in first opening simultaneously, virtual convex block is formed in second opening；
The photoresist layer is removed,
Wherein, second open bottom is formed with extension so that the bottom area of the opening is less than the upper of the opening
Portion's area.
6. convex block packaging method according to claim 5, which is characterized in that the extension is inclined at described second
On the side wall of opening.
7. convex block packaging method according to claim 5, which is characterized in that when the photoresist layer is positivity photoresist,
The exposure energy for being used to form second opening is less than the exposure energy for being used to form first opening；
When the photoresist layer is negativity photoresist, the exposure energy for being used to form second opening is described more than being used to form
The exposure energy of first opening.
8. convex block packaging method according to claim 5, which is characterized in that when the photoresist layer is positivity photoresist,
The focal length for being used to form second opening is more than the focal length for being used to form first opening；
The photoresist layer be negativity photoresist when, be used to form it is described second opening focal length be less than be used to form described first
The focal length of opening.
9. convex block packaging method according to claim 1, which is characterized in that further include：
Cleaning step, with the remaining virtual convex block of removal.
10. convex block packaging method according to claim 1, which is characterized in that the convex block and virtual convex block are convex for soldered ball
Block.
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| CN201710015091.XA CN108288590B (en) | 2017-01-09 | 2017-01-09 | Bump packaging method |
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| CN201710015091.XA CN108288590B (en) | 2017-01-09 | 2017-01-09 | Bump packaging method |
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| CN108288590B CN108288590B (en) | 2020-03-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6500764B1 (en) * | 2001-10-29 | 2002-12-31 | Fairchild Semiconductor Corporation | Method for thinning a semiconductor substrate |
| CN101226909A (en) * | 2007-01-17 | 2008-07-23 | 南茂科技股份有限公司 | Thin membrane encapsulation structure of fingerprint identifying device |
| JP5157427B2 (en) * | 2007-12-27 | 2013-03-06 | 株式会社ニコン | Stacked semiconductor device, semiconductor substrate, and manufacturing method of stacked semiconductor device. |
| US20130207259A1 (en) * | 2012-02-14 | 2013-08-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device and wafer |
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2017
- 2017-01-09 CN CN201710015091.XA patent/CN108288590B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6500764B1 (en) * | 2001-10-29 | 2002-12-31 | Fairchild Semiconductor Corporation | Method for thinning a semiconductor substrate |
| CN101226909A (en) * | 2007-01-17 | 2008-07-23 | 南茂科技股份有限公司 | Thin membrane encapsulation structure of fingerprint identifying device |
| JP5157427B2 (en) * | 2007-12-27 | 2013-03-06 | 株式会社ニコン | Stacked semiconductor device, semiconductor substrate, and manufacturing method of stacked semiconductor device. |
| US20130207259A1 (en) * | 2012-02-14 | 2013-08-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device and wafer |
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