CN108288590B

CN108288590B - Bump packaging method

Info

Publication number: CN108288590B
Application number: CN201710015091.XA
Authority: CN
Inventors: 章国伟
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-09
Filing date: 2017-01-09
Publication date: 2020-03-10
Anticipated expiration: 2037-01-09
Also published as: CN108288590A

Abstract

The invention provides a bump packaging method, which comprises the following steps: providing a front-end device, and forming an under bump metal layer on the surface of the front-end device; forming a bump for packaging and a virtual bump for improving the uniformity of the bump on the under bump metal layer, wherein the contact area of the virtual bump and the under bump metal layer is smaller than the sectional area of the virtual bump; and removing the part of the under bump metal layer, which is positioned outside the bump and the bottom of the virtual bump, and simultaneously peeling off the virtual bump. The bump packaging method can improve the coplanarity and uniformity of the bump height.

Description

Bump packaging method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a bump packaging method.

Background

With the development of portable and high-performance microelectronic products toward short, small, light and thin products, the conventional wire bonding method (wire bonding) as a packaging technology for combining chips with various substrates cannot meet the requirements of the current consumer electronic products, and the replaced bump packaging (bumping) becomes a key technology of wafer-level packaging. In the bump package process, a plating method is used to perform redistribution or bump formation. However, as semiconductor technology advances, the critical dimension of semiconductor devices is shrinking, and the package size is also decreasing. Correspondingly, the number of I/O (input/output) bumps in one chip (die) is increasing, and thus the requirement for high coplanarity and uniformity of the plated bumps is also increasing. Depending on the characteristics of the plating process, the uniformity of the bump distribution (plating area per unit area) affects the uniformity of the height of the plated bumps. Thus, for some designs where the bump distribution is not very uniform, the coplanarity and uniformity of the bump height may be greatly affected, for example, in one example, the bump height adjacent to the bumpless area (e.g., incomplete die area, laser mark area) may be 12 microns (um) greater than the normal or design value.

At present, in order to improve the coplanarity and uniformity of bump height, the following methods are mainly used in the industry: 1) the bumps are distributed uniformly as much as possible in the design stage, for example, the uniformity of the bump distribution is improved by adding the dummy bumps; however, there is a great limitation in design because the final dummy bump cannot be removed. 2) The bump height coplanarity and uniformity are improved by improving the process and equipment hardware capabilities of the electroplating. These methods cannot simply and effectively improve the coplanarity and uniformity of the bump height, or have high cost and difficulty, or have defects to affect the subsequent process.

Therefore, it is necessary to provide a new bump packaging method to overcome the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the deficiencies of the prior art, the present invention provides a bump packaging method, which can improve the coplanarity and uniformity of the bump height.

The invention provides a bump packaging method in a first aspect, which comprises the following steps: providing a front-end device, and forming an under bump metal layer on the surface of the front-end device; forming a bump for packaging and a virtual bump for improving the uniformity of the bump on the under bump metal layer, wherein the contact area of the virtual bump and the under bump metal layer is smaller than the sectional area of the virtual bump; and removing the part of the under bump metal layer, which is positioned outside the bump and the bottom of the virtual bump, and simultaneously peeling off the virtual bump.

Illustratively, the dummy bumps have a radial dimension of less than 10 microns.

Illustratively, the dummy bumps are formed in a laser marking region and/or an incomplete chip region of the front-end device.

Illustratively, the dummy bumps are formed around the bumps for packaging for improving uniformity and coplanarity of the bumps.

Illustratively, the bump packaging method further comprises; forming a photoresist layer on the bump bottom metal layer; forming a first opening in the photoresist layer through exposure and development, wherein the first opening is used for exposing the bump area to be formed; forming a second opening in the photoresist layer through exposure and development, wherein the second opening is used for exposing the area of the virtual bump to be formed; carrying out an electroplating process to simultaneously form a bump in the first opening and a dummy bump in the second opening; and removing the photoresist layer, wherein a protrusion part is formed at the bottom of the second opening, so that the area of the bottom of the opening is smaller than the area of the upper part of the opening.

Illustratively, the protrusion is provided obliquely on a sidewall of the second opening.

Illustratively, when the photoresist layer is a positive photoresist, the exposure energy for forming the second opening is less than the exposure energy for forming the first opening; when the photoresist layer is a negative photoresist, the exposure energy for forming the second opening is greater than the exposure energy for forming the first opening.

Exemplarily, when the photoresist layer is a positive photoresist, a focal length for forming the second opening is greater than a focal length for forming the first opening; when the photoresist layer is a negative photoresist, the focal length for forming the second opening is smaller than the focal length for forming the first opening.

Exemplarily, the bump packaging method further includes: and a cleaning step to remove the residual dummy bumps.

Illustratively, the bumps and dummy bumps are solder ball bumps.

According to the bump packaging method, the virtual bumps are added around the normal bumps or in the bump-free area, so that the distribution uniformity of the bumps is improved, the high coplanarity and uniformity of the electroplated bumps are further improved, and the virtual bumps are small in size and the contact area of the bottom of the virtual bumps is greatly smaller than the size of the actual bumps, so that the virtual bumps are very weak in adhesion with a bump bottom metal layer (UBM) and can be automatically removed in the etching process of the bump bottom metal layer. That is, the dummy bumps can be easily removed without affecting the distribution and assembly of the final bumps while improving the uniformity and coplanarity of the height of the plated bumps, and thus can be disposed at any position of the wafer.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1A is a flowchart illustrating steps of a bump packaging method according to an embodiment of the invention;

FIG. 1B is a flowchart illustrating steps of forming bumps and dummy bumps according to a bump packaging method of an embodiment of the invention;

FIGS. 2A-2D are schematic diagrams illustrating a dummy bump forming process according to an embodiment of the invention;

FIG. 3 illustrates a partial chip area and a laser mark area where dummy bumps are provided;

fig. 4 shows dummy bumps disposed around the bumps for packaging.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

A bump packaging method according to an embodiment of the present invention will be described in detail with reference to fig. 1A, 1B, and 2A to 2D.

First, as shown in fig. 1A, the bump packaging method of the present embodiment includes:

step 101, providing a front-end device, and forming a metal layer under a bump on the surface of the front-end device.

The front-end device is a device formed with various circuit structures and functional devices. Typically, front-end devices generally include a semiconductor substrate/wafer in which active devices are formed, an interconnect layer formed on the semiconductor substrate/wafer, a passivation layer formed on top of the interconnect layer, and a pad.

The Under Bump Metallurgy (UBM) is used as a seed layer or an electrode layer in a subsequent bump electroplating process, and may be made of various suitable metal materials, such as Cu (copper), TiW (tungsten titanium alloy), Au (gold), Ti (titanium), and the like, and may include one or more layers of different metal materials.

And 102, forming a bump for packaging and a virtual bump for improving the uniformity of the bump on the under bump metal layer.

The bumps are used for realizing fixation and electrical connection with a package substrate subsequently, however, the distribution of the bumps is generally designed based on the distribution of the bonding pads on the front-end device, as described above, since the distribution of the chips (die) on the wafer is not uniform, a region with dense chips (die) exists, and a region without chips or an incomplete chip region (oughy die) also exists, the corresponding normal bump distribution also has a uniformity problem, and therefore, when the bumps are manufactured by electroplating, the bump height uniformity and coplanarity are not good, and the package quality is further affected. Therefore, in this embodiment, dummy bumps are disposed in the non-bump regions or normal bumps (i.e., bumps for packaging) to improve the uniformity of bump distribution, so that the bump height uniformity and coplanarity can be improved during the bump fabrication by electroplating.

In this embodiment, the dummy bumps may be formed in the laser mark area and/or the incomplete chip area of the front-end device, or may also be formed around the bumps for packaging, or may be formed at any position of the front-end device, and the design principle is to make the bumps and the dummy bumps be uniformly distributed as a whole, so that the uniformity and coplanarity of the bump height can be improved during electroplating.

Illustratively, dummy bumps are formed in the laser mark region and/or the incomplete chip region of the front-end device, as shown in fig. 3, or as shown in fig. 4. The dummy bumps are formed around the bumps for packaging, that is, when the distribution of the bumps for packaging is not uniform, the dummy bumps may be disposed around the bumps, as shown in fig. 4, in which a solid circle represents a bump for packaging, the distribution of which is not very uniform, and the right area is not provided with a bump, so that the dummy bumps (dotted circles) are disposed on the right side to improve the uniformity of this area.

Further, the bump for packaging is typically formed on a pad/Redistribution (RDL) of the front-end device, while the dummy bump is typically formed directly on the under-bump metal layer, and there is no corresponding pad/Redistribution (RDL) in the same layer below the dummy bump, i.e., the dummy bump is not used for electrical connection and is removed in the subsequent process.

Further, in the present embodiment, the dummy bumps are generally micro bumps, which are small relative to the bumps used for packaging, for example, the radial dimension of the dummy bumps is less than 10 microns. And the contact area of the virtual lug and the lug bottom metal layer is smaller than the sectional area of the virtual lug. Here, the contact area of the dummy bump with the under-bump metal layer refers to an area of a direct contact surface of the dummy bump with the under-bump metal layer, and the sectional area of the dummy bump refers to a sectional area of a body portion of the dummy bump or a maximum sectional area of the dummy bump.

Step 103, removing the part of the under bump metallurgy layer outside the bump and the dummy bump bottom, and peeling off the dummy bump,

namely, etching the under bump metal layer to remove the bump and the part except the bottom of the virtual bump. Illustratively, the etching of the under bump metal layer is performed by a wet process, i.e. by a suitable etching liquid, such as HF (hydrofluoric acid) or the like.

As described above, in the present embodiment, since the size of the dummy bump is smaller and the contact area between the dummy bump and the under bump metallurgy is smaller than the area of the dummy bump, the adhesion between the dummy bump and the under bump metallurgy is very weak, and thus when the under bump metallurgy is etched, the dummy bump is removed because the adhesion is weak and the dummy bump is peeled off at the same time as the under bump metallurgy around the dummy bump is removed.

The following describes the fabrication of the bumps and dummy bumps in the bump packaging method of the present embodiment in detail with reference to fig. 1B.

As shown in fig. 1B, in the present embodiment, the bumps and the dummy bumps are formed by the following steps.

First, step 1020 is performed to form a photoresist layer on the under bump metallurgy layer.

The photoresist layer may be a positive photoresist (e.g., TOK P-CA100) or a negative photoresist (e.g., HD4100), and is formed on the under bump metallurgy layer by a conventional method such as coating. The thickness of the photoresist layer is designed as required, and is not particularly limited herein.

Next, step 1021 is executed to form a first opening in the photoresist layer through exposure and development, so as to expose the bump region to be formed.

The exposure and development are performed by a method commonly used in the art, such as exposure by 193nm ArF lithography, and development is performed by a developer corresponding to the photoresist layer, i.e., a developer corresponding to the positive photoresist or the negative photoresist (e.g., positive photoresist developer TOK P7-G, negative photoresist developer AZ-a515) to pattern the photoresist layer.

Further, in general, the first opening exposes regions on the front-end device where pads are formed, and these regions are used for forming bumps for packaging.

Next, step 1022 is executed to form a second opening in the photoresist layer by exposure and development, so as to expose the region where the dummy bump is to be formed.

The exposure and development are carried out by a method commonly used in the art, for example, by exposure using 193nm ArF photolithography, and development is carried out by a developer corresponding to the photoresist layer. That is, a developing solution corresponding to the positive photoresist or the negative photoresist is used for developing to pattern the photoresist layer.

Further, the second opening exposes regions of the front-end device where the dummy bumps are formed, which are generally free of pads and have a lower bump density or no bumps nearby.

In this embodiment, the second opening bottom is formed with a protrusion so that the bottom area of the opening is smaller than the upper area of the opening. Illustratively, the protrusion is obliquely disposed on the sidewall of the second opening, so that when a dummy bump is subsequently formed in the second opening, the dummy bump forms an undercut at the bottom, so that the contact area of the bottom of the dummy bump is substantially smaller than the area of the dummy bump.

Further, in the present embodiment, the shape of the second opening can be realized by controlling parameters of the photolithography process. For example, when the photoresist layer is a positive photoresist, the exposure energy for forming the second opening is less than that of a normal exposure, or less than that for forming the first opening; when the photoresist layer is a negative photoresist, the exposure energy for forming the second opening is greater than the exposure energy for normal exposure, or greater than the exposure energy for forming the first opening. When the photoresist layer is a positive photoresist, the focal length for forming the second opening is larger than the normal focal length, or larger than the focal length for forming the first opening; when the photoresist layer is a negative photoresist, the focal length for forming the second opening is smaller than the normal focal length, or the focal length for forming the first opening.

That is, in the present embodiment, the area of the photoresist corresponding to the second opening is not sufficiently exposed during exposure by the photolithography process parameters, such as exposure energy, focus, etc., so that a foot or a protrusion is formed at the bottom of the second opening during subsequent development, so that the area of the bottom of the second opening is smaller than that of the upper portion.

Here, the exposure energy or focal length of the normal exposure refers to the exposure energy or focal length used when the second opening is made free of the foot or the protrusion.

Further, it is understood that the developing operation for forming the first opening and the second opening may be performed in two steps, or after the exposure of the first opening and the exposure of the second opening are completed, the developing operation may be performed together to form the first opening and the second opening at the same time.

Next, in step 1023, an electroplating process is performed to simultaneously form bumps in the first openings and dummy bumps in the second openings.

Specifically, a suitable electrolyte is selected according to the type of the bump, such as a gold bump, a copper pillar bump, a solder ball bump, and the like, and a bump and a dummy bump are formed in the first opening and the second opening by electroplating, respectively.

Finally, step 1024 is performed to remove the photoresist layer.

Illustratively, the photoresist layer is removed, for example, by a suitable photoresist stripper (e.g., AZ400T, etc.).

It is understood that the above steps are only one example of a bump and dummy bump manufacturing method, and the invention can adopt other suitable methods to manufacture the bump and dummy bump as required, as long as the dummy bump has poor adhesion and is easy to peel off.

The formation and peeling process of the dummy bumps according to an embodiment of the present invention will be described with reference to fig. 2A to 2D to better understand the present invention.

First, as shown in fig. 2A, a front-end device is provided, an under bump metallurgy layer is formed on the front-end device, and a patterned photoresist layer is formed on the under bump metallurgy layer.

The front-end device 200 includes a semiconductor substrate/wafer, and circuit structures, devices, elements, etc., formed on the semiconductor substrate/wafer. The semiconductor substrate/wafer may be at least one of the following mentioned materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS transistors or other semiconductor devices, may be formed on the semiconductor substrate. An isolation structure may also be formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure.

Metal interconnect structures electrically connected to the transistors are formed on the semiconductor substrate/wafer. A passivation layer 201 is formed on top of the interconnect structure. Illustratively, the passivation layer 201 is, for example, a silicon nitride layer. An opening (not shown) exposing the pad is formed in the passivation layer 201. For simplicity, only regions corresponding to the dummy bumps are schematically illustrated in fig. 2A to 2D, and regions where the bumps are formed are not illustrated. It is understood that the passivation layer may be a single layer or a multi-layer structure.

The Under Bump Metallurgy (UBM) is used as a seed layer or an electrode layer for electroplating the bump. In this embodiment, a solder bump (solder bump) is taken as an example for description, and thus the under bump metallurgy includes a first under bump metallurgy 202 and a second under bump metallurgy 203, where the first under bump metallurgy 202 is a Ti layer for example, and the second under bump metallurgy 203 is a Cu layer for example. The first and second under

bump metal layers

202 and 203 may be formed by a sputtering process to obtain good uniformity.

The patterned photoresist layer 204 exposes regions where dummy bumps are to be formed. In the present embodiment, the patterned photoresist layer 204 is used to expose the opening 205 of the region where the dummy bump is to be formed, and the bottom of the opening 205 has a foot or protrusion 205A, so that the bottom area S1 of the opening 205 is smaller than the upper area or opening area S2 of the opening 205. Illustratively, in this embodiment, the foot or protrusion 205A is formed in an inclined shape on a side wall of the bottom of the opening 205. The formation of the patterned photoresist layer 204 or the opening 205 is as described above and will not be described herein.

Next, as shown in fig. 2B, dummy bumps 206 are formed in the openings 205.

Illustratively, dummy bumps 206 are formed in the openings 205 by an electroplating process. Illustratively, in the present embodiment, the bump/dummy bump is a solder ball bump, i.e., the dummy bump 206 includes two portions, i.e., a copper pillar portion 206A and a solder ball portion 206B. Wherein the copper pillar portion 206A is formed by electroplating copper and the solder ball portion 206B is formed by electroplating tin.

It is understood that the copper pillar portion 206A and the solder ball portion 206B are illustrated in cross-sectional views and are only schematic and do not represent actual shapes, and the actual shapes of the copper pillar portion 206A and the solder ball portion 206B may be the same as or different from the copper pillar portion 206A and the solder ball portion 206B illustrated in the figures.

It is also understood that after the dummy bumps are formed, the operation of reflowing to form stable alloy of the solder ball bumps is also included.

Next, as shown in fig. 2C, the patterned photoresist layer 204 is removed.

Patterned photoresist layer 204 is removed by a suitable photoresist stripper (e.g., AZ400T, etc.), as previously described.

When the photoresist layer 204 is removed, the dummy bump 206 is exposed, and since the bottom of the opening 205 has a foot or protrusion 205A, such that the bottom area S1 of the opening 205 is smaller than the upper area of the opening 205 or the opening area S2, the contact area S3 between the dummy bump 206 and the under bump metallurgy is smaller than the cross-sectional area S4 of the dummy bump 206, and the cross-sectional area S4 of the dummy bump 206 refers to the cross-sectional area of the main portion of the dummy bump 206 or the maximum cross-sectional area of the dummy bump 206. Therefore, an undercut is formed at the bottom of the dummy bump 206, so that the dummy bump 206 has a weak adhesion to the bottom metal layer and is easily peeled off.

Finally, as shown in fig. 2D, the under bump metallurgy is etched.

Specifically, the under bump metallurgy layer is etched using a suitable etching solution to remove the portions of the under bump metallurgy layer outside the bottom of the dummy bump 206. For example, in the present embodiment, 85 micro etching liquid (micro etch85) may be used to remove the portion of the second ubm layer 203 except the bottom of the dummy bump 206, and HF etching liquid may be used to remove the portion of the first ubm layer 202 except the bottom of the dummy bump 206.

It is understood that, on one hand, the under bump metallurgy at the bottom of the dummy bump 206 is corroded when the under bump metallurgy etching is performed, and on the other hand, the dummy bump is peeled off automatically when the surrounding under bump metallurgy is removed because the adhesion between the dummy bump 206 and the under bump metallurgy is weak.

It will be appreciated that even if there are dummy bumps that are not automatically removed, a subsequent cleaning operation, such as a high pressure wash (high pressure Scrubber) operation, may be performed to remove the remaining dummy bumps without any effect on the final bump distribution and assembly.

The bump packaging method provided by the embodiment improves the uniformity of bump distribution by adding the dummy bumps around the normal bumps or in the bump-free area, so that the uniformity and the coplanarity of the bump height can be improved when the bumps are formed by electroplating, for example, by adopting the bump packaging method of the embodiment, the bumps of the chip adjacent to the bump-free area are slightly larger than the normal value (for example, 2 to 6 micrometers), and by adopting the conventional method, the bumps are larger than the normal value by more than 12 micrometers, so that the bump packaging method provided by the embodiment greatly improves the uniformity and the coplanarity of the bump height.

Further, in the bump packaging method of the present embodiment, the dummy bumps have a smaller size, for example, the radial size is generally smaller than 10 μm, and the photoresist generates a larger foot region by using the photolithography condition different from that of the normal bumps, and the plating process has a large undercut, so that the contact area of the bottom of the dummy bump is much smaller than the actual size of the dummy bump, the adhesion of the dummy bump to the lower layer is very weak, the dummy bump is automatically removed during the etching process of the metal layer at the bottom of the bump, and a small portion of the dummy bump with unclean section can be removed by adding an extra high pressure scrubber. The special virtual bumps can be easily removed while the uniformity of the height coplanarity and uniformity of the electroplated bumps is improved, and the distribution and assembly of the final bumps are not affected, so that the special virtual bumps can be designed at any position of a wafer, the virtual bumps can be arranged at any required position according to requirements during use, the distribution uniformity of the bumps during electroplating is greatly improved, and the height uniformity and the coplanarity of the electroplated bumps are greatly improved.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A bump packaging method is characterized by comprising the following steps:

providing a front-end device, and forming an under bump metal layer on the surface of the front-end device;

forming a bump for packaging and a virtual bump for improving the uniformity of the bump on the under bump metal layer, wherein the contact area of the virtual bump and the under bump metal layer is smaller than the sectional area of the virtual bump;

and removing the part of the under bump metal layer, which is positioned outside the bump and the bottom of the virtual bump, and simultaneously peeling off the virtual bump.

2. The bump packaging method according to claim 1, wherein the radial dimension of the dummy bumps is less than 10 μm.

3. The bump packaging method according to claim 1, wherein the dummy bumps are formed in a laser marking region and/or an incomplete chip region of the front-end device.

4. The bump packaging method according to claim 1, wherein the dummy bumps are formed around the bumps for packaging for improving uniformity and coplanarity of the bumps.

5. The bump packaging method according to any one of claims 1 to 4, further comprising;

forming a photoresist layer on the bump bottom metal layer;

forming a first opening in the photoresist layer through exposure and development, wherein the first opening is used for exposing the bump area to be formed;

forming a second opening in the photoresist layer through exposure and development, wherein the second opening is used for exposing the area of the virtual bump to be formed;

carrying out an electroplating process to simultaneously form a bump in the first opening and a dummy bump in the second opening;

the photoresist layer is removed to remove the photoresist layer,

wherein, the bottom of the second opening is formed with a protrusion, so that the bottom area of the second opening is smaller than the upper area of the second opening.

6. The bump packaging method according to claim 5, wherein the protruding portion is obliquely disposed on a side wall of the second opening.

7. The bump packaging method according to claim 5, wherein when the photoresist layer is a positive photoresist, an exposure energy for forming the second opening is smaller than an exposure energy for forming the first opening;

when the photoresist layer is a negative photoresist, the exposure energy for forming the second opening is greater than the exposure energy for forming the first opening.

8. The bump packaging method according to claim 5, wherein when the photoresist layer is a positive photoresist, a focal length for forming the second opening is greater than a focal length for forming the first opening;

when the photoresist layer is a negative photoresist, the focal length for forming the second opening is smaller than the focal length for forming the first opening.

9. The bump packaging method according to claim 1, further comprising:

and a cleaning step to remove the residual dummy bumps.

10. The bump packaging method according to claim 1, wherein the bumps and the dummy bumps are solder ball bumps.