CN106816394A - The manufacture method of test semiconductor wafer and projection, semiconductor devices and electronic installation - Google Patents
The manufacture method of test semiconductor wafer and projection, semiconductor devices and electronic installation Download PDFInfo
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- CN106816394A CN106816394A CN201510848629.6A CN201510848629A CN106816394A CN 106816394 A CN106816394 A CN 106816394A CN 201510848629 A CN201510848629 A CN 201510848629A CN 106816394 A CN106816394 A CN 106816394A
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- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000009434 installation Methods 0.000 title claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 32
- 239000000523 sample Substances 0.000 claims abstract description 22
- 238000002161 passivation Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000013459 approach Methods 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention provides manufacture method, semiconductor devices and the electronic installation of a kind of test semiconductor wafer method and wafer bumps, is related to technical field of semiconductors.The test semiconductor wafer method makes testing needle trace deviate the center of the pad when probe test is carried out.The manufacture method of the wafer bumps is included in when carrying out probe test, testing needle trace is deviateed the center of the pad, and is used in the bonding pad opening to form wafer bumps, positioned at the region not influenceed by the testing needle trace.Crystal round test approach of the invention and wafer bumps manufacture method, can thoroughly prevent from testing needle trace from preparing the ball bottom metal layer in bump technology to impact, the defect of such as projection missing is avoided the occurrence of, so as to improve the reliability of encapsulation and further improve the yield of encapsulation.The semiconductor devices and electronic installation are had the advantages that similar using above-mentioned crystal round test approach and the manufacture method of wafer bumps.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of test semiconductor wafer
Method, the manufacture method of wafer bumps, and using the test semiconductor wafer and the system of projection
Make the semiconductor devices and the electronic installation with the semiconductor devices of method formation.
Background technology
As portable and high-performance microelectronics product develops to short, small, light, thinning direction,
The encapsulation skill that traditional routing mode (Wire Bonding) is combined as chip with various base material
Art can not meet the demand of present consumption electronic product, and instead projection is encapsulated into
The key technology of wafer-level packaging.However, the manufacturing process of high-order chip is sufficiently complex, good
The more difficult control of rate, and bumping manufacturing process yield is stablized relatively, therefore in order to save packaging cost,
Generally need just to carry out chip probe test (CP, chip probing) after the completion of chip manufacturing,
Screened with to wafer, choose underproof chip.But when CP tests are carried out, visit
Pin can with the contact pads of wafer, this may cause the damage of pad (such as aluminum pad) or
Pollution.Meanwhile, testing needle trace causes that bond pad surface is uneven, and this in follow-up bump technology to making
Ball bottom metal layer is prepared with physical vapour deposition (PVD) bring difficulty.And ball bottom metal layer quality for
Follow-up bump technology influence is very acute, as shown in figure 1,100 region Lv Dian center sections are just in figure
It is defect that testing needle trace causes aluminium pad surface, makes bond pad surface uneven, enters so as to ball down payment
Category layer does not deposit the intact projection that in turn results in and lacks.
Therefore, in order to solve the above technical problems, be necessary to propose a kind of new semiconductor devices and
Its manufacture method.
The content of the invention
In view of the shortcomings of the prior art, the present invention proposes a kind of test semiconductor wafer method and crystalline substance
Circle bump manufacturing method, can prevent testing needle trace from being impacted to wafer bumps.
One embodiment of the present of invention provides a kind of test semiconductor wafer method, the semiconductor
The multiple chips comprising circuit are formed with wafer, are formed on the semiconductor crystal wafer and the crystalline substance
Circuit connection in circle, for the pad being connected with follow-up encapsulated circuit, methods described includes：
Probe test is carried out to the semiconductor crystal wafer, to select underproof chip, wherein, entering
During row probe test, testing needle trace is set to deviate the center of the pad.
Further, when carrying out probe test, testing needle trace is made to be partial to the side of the pad.
An alternative embodiment of the invention provides a kind of manufacture method of wafer bumps, and it includes：
Semiconductor crystal wafer is provided, pad is formed on the semiconductor crystal wafer and the semiconductor is covered
Wafer and expose the first passivation layer of the pad；Probe survey is carried out to the semiconductor crystal wafer
Examination, and when probe test is carried out, testing needle trace is deviateed the center of the pad；Shape
Into the second passivation layer for covering first passivation layer and pad；The shape on second passivation layer
Into the bonding pad opening for forming wafer bumps, the bonding pad opening is located at does not receive the testing needle
The region of trace influence.
Further, when probe test is carried out, testing needle trace is made to be partial to the side of the pad.
Further, the bonding pad opening is located on the pad and deviates the another of the testing needle trace
Side.
Further, second passivation layer is photosensitive material.
Further, the method also comprises the steps：Projection is formed in the bonding pad opening.
Yet another embodiment of the present invention provides a kind of semiconductor devices, the semiconductor devices bag
Include semiconductor element and package substrate with functional circuit, the semiconductor element and encapsulation base
Plate is connected by the projection being formed on the semiconductor element, wherein the projection is by this hair
The wafer bumps manufacture method of bright offer is formed.
Another embodiment of the invention provides a kind of electronic installation, including the present invention provide half
Conductor device and the electronic building brick being connected with the semiconductor devices.
Crystal round test approach of the invention and wafer bumps manufacture method, can thoroughly prevent from surveying
Test point trace is prepared to the ball bottom metal layer in bump technology and impacted, it is to avoid such as projection occur
The defect of missing, so as to improve the reliability of encapsulation and further improve the yield of encapsulation.
Brief description of the drawings
Drawings below of the invention is in this as a part of the invention for understanding the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining principle of the invention.
In accompanying drawing：
Fig. 1 shows the defect that testing needle trace causes projection to lack；
Fig. 2 and Fig. 3 show test semiconductor wafer of the invention and wafer bumps system
The principle schematic made；
Fig. 4 A~Fig. 4 D show each step institute of the manufacture method of wafer bumps of the invention
Obtain the generalized section of device；
Fig. 5 shows a kind of flow chart of the manufacture method of wafer bumps of the invention；
Fig. 6 shows the structural representation of semiconductor device according to the invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer and
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operating
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.When using herein, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When using herein, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram as desirable embodiment of the invention (and intermediate structure)
Sectional view describes inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle its edge generally there is circle or bending features and
/ or implantation concentration gradient, change rather than the binary from injection region to non-injection regions.Equally,
The surface passed through when by injecting the disposal area for being formed the disposal area and injection can be caused to carry out
Between area in some injection.Therefore, in figure show area be substantially it is schematical, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
As it was previously stated, when probe test is carried out to wafer, testing needle trace can be to follow-up projection
Making is impacted, and causes projection the defect of such as projection missing occur.In order to overcome this to ask
Topic, the present invention is improved the method for testing of wafer and the manufacture method of projection, to avoid
This defect.Specifically, as shown in Figures 2 and 3, it is formed with semiconductor crystal wafer 10
Multiple chips comprising circuit, and formed on semiconductor crystal wafer 10 and the circuit company in wafer 10
Connect, for the pad 11 being connected with follow-up encapsulated circuit, and cover wafer 10 and expose weldering
First passivation layer 12 of disk 11, probe test is being carried out to the wafer, underproof to select
During chip, test is set to be directed at the position for deviateing the center of pad 11, so that testing needle trace 20 deviates
The center of the pad 11, is so easy to the follow-up area in the not tested influence of test point trace 20
Domain forms projection, i.e., be positioned away from testing needle trace 20 for forming the bonding pad opening 14 of projection
Position.Such as, when probe test is carried out, testing needle trace is made to be partial to the side of the pad,
As shown in Fig. 2 making testing needle trace 20 be partial to the upper side of pad 11, and it is subsequently used for shape
Bonding pad opening 14 into projection is located at the lower section side of pad 11.Certainly top herein, under
Side is exemplary, and those skilled in the art can select suitable position according to specific situation.
At the same time, as shown in figure 3, the manufacture method of wafer bumps of the invention, is manufacturing
During wafer bumps, the second passivation layer 13 is formed on first passivation layer 12, and second
Formed on passivation layer 13 for forming the bonding pad opening 14 of projection, and make bonding pad opening 14 inclined
From testing needle trace 20, positioned at the region of the not tested influence of test point trace 20, it can be by adjusting shape
Alignment parameter into the mask plate of bonding pad opening 14 realizes that the projection being so subsequently formed will not
Also 20 influence of tested test point trace.
Using crystal round test approach of the invention and wafer bumps manufacture method, can thoroughly prevent
Only testing needle trace is prepared to the ball bottom metal layer in bump technology and impacted, it is to avoid occurred such as
The defect of projection missing, so as to improve the reliability of encapsulation and further improve the good of encapsulation
Rate.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, to explain technical scheme.Presently preferred embodiments of the present invention is retouched in detail
State it is as follows, but except these detailed description in addition to, the present invention can also have other embodiment.
Embodiment one
Below, reference picture 4A to 4D and Fig. 5 specifically describes one embodiment of the present of invention
A kind of wafer bumps manufacture method.Wherein, Fig. 4 A to Fig. 4 D are one of the invention
The sectional view of the structure that a kind of correlation step of the manufacture method of wafer bumps of embodiment is formed；
Fig. 3 is a kind of flow chart of the manufacture method of the wafer bumps of one embodiment of the present of invention.
The manufacture method of the wafer bumps of the embodiment of the present invention one, comprises the following steps：
Step S101, there is provided semiconductor crystal wafer, on the semiconductor crystal wafer formed pad with
And cover the semiconductor crystal wafer and expose the first passivation layer of the pad.
As shown in Figure 4 A, there is provided semiconductor crystal wafer 10, the shape on the semiconductor crystal wafer 10
Into pad 11 and cover the semiconductor crystal wafer 10 and expose the first of the pad 11
Passivation layer 12.
Wherein, semiconductor crystal wafer 10 can be at least one in the following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing semiconductor, the sandwich construction etc. for also being constituted including these semiconductors or be silicon-on-insulator
(SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
There are the multiple chips comprising circuit in semiconductor crystal wafer 10, these circuits can be such as
The semiconductor element of NMOS and/or PMOS etc. and the metal interconnection electrically connected with transistor
Structure is formed, and final these circuits by corresponding interconnection structure accordingly lead to pad
11, electrically connected with follow-up package substrate.Pad 11 can be by such as PVD, CVD
Metal level is initially formed etc. technique, and corresponding pad is prepared by the formation of the methods such as etching, pad
11 can be using the suitable conductive material such as aluminium.
First passivation layer 12 covers the semiconductor crystal wafer 10 and exposes the pad 11,
For protecting the device formed on semiconductor crystal wafer 10.First passivation layer 12 can be by such as
The common methods such as PECVD are formed, and it can use such as silicon nitride, silicon oxynitride, titanium dioxide
Silicon, BPSG, PSG and polyimides (Polyimid) etc., it is blunt by graphical first
Changing layer 12 can expose pad 11, specifically can be by photoetching commonly used in the art, lithographic method
Formed, will not be repeated here.
Step S102, probe test is carried out to the semiconductor crystal wafer, and carrying out probe survey
During examination, testing needle trace is set to deviate the center of the pad.
As shown in Figure 4 B, probe test is carried out to semiconductor crystal wafer 10, when alignment is tested,
Deviate the central area of pad 11, so that testing needle trace 20 deviates the central area of pad 11,
So it is easy to that subsequently projection can be formed in the region of the not tested influence of test point trace 20.
As an example, in the present embodiment, when probe test is carried out, making testing needle trace 20
The side of the pad is partial to, such as is partial to the leftward position of pad.
Step S103, forms the second passivation layer of covering first passivation layer and pad.
As shown in Figure 4 C, form covering first passivation layer 12 and pad 11 second is blunt
Change layer 13, for being the offer buffer protection function of semiconductor crystal wafer 10 in subsequent technique.Its
In the second passivation layer 13 and the first passivation layer 12 can use identical material, such as silicon nitride,
Silicon oxynitride, silica, BPSG, PSG and polyimides (Polyimid) etc. are closed
Suitable passivation material.
Preferably, in the present embodiment, second passivation layer 13 is photo-sensistive polyimide
Material, it can be the offer buffer protection function of semiconductor crystal wafer 10 in subsequent technique, and
And by being exposed to the second passivation layer 13 development by form pad for forming projection
Opening 14, simplifies processing step, improves process efficiency.
Step S104：The pad for forming wafer bumps is formed on second passivation layer
Opening, the bonding pad opening is located at the region not influenceed by the testing needle trace.
As shown in Figure 4 D, formed for forming wafer bumps on second passivation layer 13
Bonding pad opening 14, the bonding pad opening 14 is located at the region that is not influenceed by the testing needle trace.
Such as, bonding pad opening 14 is located on the pad 11 and deviates the another of the testing needle trace 20
Side.The step can form the alignment parameter realization of the mask plate of bonding pad opening 14 by adjustment,
Such as testing needle trace 14 is located at the leftward position of pad 11, by adjusting the alignment parameter of mask,
Make mask plate by pad right side alignment, the bonding pad opening 14 for so being formed will be positioned at by not described
The region of testing needle trace influence.
Exemplary, in the present embodiment, bonding pad opening 14 is partial to institute with foregoing testing needle trace 20
It is partial to the leftward position of pad accordingly, bonding pad opening 14 is located at the right positions of pad 14.
Additionally, bonding pad opening 14 is formed by photoetching commonly used in the art and lithographic method, and
And preferably, second passivation layer 13 is photo-sensistive polyimide material as previously described, its
Can be the offer buffer protection function of semiconductor crystal wafer 10 in subsequent technique, and by right
Second passivation layer 13 forms the bonding pad opening 14 for forming projection by being exposed development.
Certainly, the second passivation layer 13 also can use nonphotosensitive material, now by coat photoresist,
Exposure, development and suitable wet method, dry etch process can also be formed.
Step S105：Projection is formed in the bonding pad opening.
Wherein the preparation method of projection use method commonly used in the art, it is exemplary can be in this implementation
In projection is formed by following step：
Step S1051, forms ball bottom metal layer (UBM) on second passivation layer 13,
Ball bottom metal layer can be formed by methods such as PVD, material can using such as Ti,
The suitable materials such as Cu.
Step S1052, fills the bonding pad opening 14, to form projection.The projection can be with
It is Solder Bumps, tin-silver convex block and copper pillar bumps.
Exemplary, in this embodiment, projection is copper pillar bumps, and it passes through plating and is formed.
Step S1053, the ball bottom metal layer on the outside of removal projection.By such as wet method or dry method
Method removal ball bottom metal layer is located at the part on the outside of projection, only retains and is located at projection bottom and weldering
The part of the side wall of dish opening 14.
So far all steps of this implementation semiconductor devices are completed, it is to be understood that upper
Before stating step, among or afterwards can also include other steps, it is all covered in the present invention.
The wafer bumps manufacture method of the present embodiment, can thoroughly prevent testing needle trace to projection work
Ball bottom metal layer in skill is prepared and impacted, it is to avoid the defect of such as projection missing occur, from
And improve the reliability of encapsulation and further improve the yield of encapsulation.
Embodiment two
An alternative embodiment of the invention provides a kind of semiconductor devices, and it can be using as above institute
It is prepared by the method stated.
As shown in fig. 6, the semiconductor devices 100 of the present embodiment includes with functional circuit half
Conductor element 101 and package substrate 103, the semiconductor element 101 and package substrate 103
Connected by the projection 102 being formed on the semiconductor element 101, wherein the projection
The 102 wafer bumps manufacture methods provided by the present invention are formed.
Wherein, semiconductor element 101 can be the device for realizing the integrated circuit of various functions
The various processor chips such as part, such as microprocessor, DSP or audio/video decoding chip etc..
The semiconductor devices of the present embodiment has package reliability higher.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and
The electronic building brick being connected with the semiconductor devices.Wherein, the semiconductor devices is as described above
Semiconductor devices.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, on
Net sheet, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, or it is any including
The intermediate products of the semiconductor devices.
The electronic installation of the embodiment of the present invention, due to having used above-mentioned semiconductor devices, thus
Equally there is above-mentioned advantage.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also make more kinds of modifications and repair
Change, these variants and modifications are all fallen within scope of the present invention.It is of the invention
Protection domain is defined by the appended claims and its equivalent scope.
Claims (9)
1. a kind of test semiconductor wafer method, is formed with comprising electricity in the semiconductor crystal wafer
Multiple chips on road, form on the semiconductor crystal wafer and are connected with the circuit in the wafer, use
In the pad being connected with follow-up encapsulated circuit, it is characterised in that the method for testing includes：
Probe test is carried out to the semiconductor crystal wafer, to select underproof chip, wherein,
When probe test is carried out, testing needle trace is set to deviate the center of the pad.
2. test semiconductor wafer method as claimed in claim 1, it is characterised in that
When carrying out probe test, testing needle trace is set to be partial to the side of the pad.
3. a kind of manufacture method of wafer bumps, it is characterised in that comprise the steps：
Semiconductor crystal wafer is provided, pad and covering described half are formed on the semiconductor crystal wafer
Semiconductor wafer and expose the first passivation layer of the pad；
Probe test is carried out to the semiconductor crystal wafer, and when probe test is carried out, makes test
Pin trace deviates the center of the pad；
Form the second passivation layer of covering first passivation layer and pad；
The bonding pad opening for forming wafer bumps, the weldering are formed on second passivation layer
Dish opening is located at the region not influenceed by the testing needle trace.
4. the manufacture method of wafer bumps as claimed in claim 3, it is characterised in that
When carrying out probe test, testing needle trace is set to be partial to the side of the pad.
5. the manufacture method of wafer bumps as claimed in claim 4, it is characterised in that institute
State the opposite side that bonding pad opening deviates the testing needle trace on the pad.
6. the manufacture method of wafer bumps as claimed in claim 3, it is characterised in that institute
The second passivation layer is stated for photosensitive material.
7. the manufacture method of the wafer bumps as described in one of claim 3-6, its feature exists
In also comprising the steps：
Projection is formed in the bonding pad opening.
8. a kind of semiconductor devices, it is characterised in that including：Partly leading with functional circuit
Volume elements part and package substrate, the semiconductor element and package substrate described are partly led by being formed in
Projection connection on volume elements part, wherein the projection passes through as described in one of claim 3-7
The manufacture method of wafer bumps is formed.
9. a kind of electronic installation, it is characterised in that including partly leading as claimed in claim 8
Body device and the electronic building brick being connected with the semiconductor devices.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510848629.6A CN106816394A (en) | 2015-11-27 | 2015-11-27 | The manufacture method of test semiconductor wafer and projection, semiconductor devices and electronic installation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510848629.6A CN106816394A (en) | 2015-11-27 | 2015-11-27 | The manufacture method of test semiconductor wafer and projection, semiconductor devices and electronic installation |
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| CN106816394A true CN106816394A (en) | 2017-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110187259A (en) * | 2019-06-10 | 2019-08-30 | 德淮半导体有限公司 | A kind of adjustment system and method for adjustment preventing probe mark shift in wafer test |
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| US20020016070A1 (en) * | 2000-04-05 | 2002-02-07 | Gerald Friese | Power pads for application of high current per bond pad in silicon technology |
| CN1790694A (en) * | 2004-10-12 | 2006-06-21 | 国际商业机器公司 | Contour structures to highlight inspection regions |
| US20060164110A1 (en) * | 2005-01-25 | 2006-07-27 | Nec Electronics Corporation | Semiconductor device and method of fabricating the same |
| US20080042275A1 (en) * | 2006-08-15 | 2008-02-21 | Francis Heap Hoe Kuan | Structure for bumped wafer test |
| US20100167432A1 (en) * | 2008-12-26 | 2010-07-01 | Nec Electronics Corporation | Method of manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020016070A1 (en) * | 2000-04-05 | 2002-02-07 | Gerald Friese | Power pads for application of high current per bond pad in silicon technology |
| CN1790694A (en) * | 2004-10-12 | 2006-06-21 | 国际商业机器公司 | Contour structures to highlight inspection regions |
| US20060164110A1 (en) * | 2005-01-25 | 2006-07-27 | Nec Electronics Corporation | Semiconductor device and method of fabricating the same |
| US20080042275A1 (en) * | 2006-08-15 | 2008-02-21 | Francis Heap Hoe Kuan | Structure for bumped wafer test |
| US20100167432A1 (en) * | 2008-12-26 | 2010-07-01 | Nec Electronics Corporation | Method of manufacturing semiconductor device |
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| CN110187259A (en) * | 2019-06-10 | 2019-08-30 | 德淮半导体有限公司 | A kind of adjustment system and method for adjustment preventing probe mark shift in wafer test |
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