CN108346618B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

Info

Publication number
CN108346618B
CN108346618B CN201710060662.1A CN201710060662A CN108346618B CN 108346618 B CN108346618 B CN 108346618B CN 201710060662 A CN201710060662 A CN 201710060662A CN 108346618 B CN108346618 B CN 108346618B
Authority
CN
China
Prior art keywords
pad
passivation layer
area
semiconductor device
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710060662.1A
Other languages
Chinese (zh)
Other versions
CN108346618A (en
Inventor
殷原梓
李日鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710060662.1A priority Critical patent/CN108346618B/en
Publication of CN108346618A publication Critical patent/CN108346618A/en
Application granted granted Critical
Publication of CN108346618B publication Critical patent/CN108346618B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the steps of providing a semiconductor substrate, forming an interconnection structure on the semiconductor substrate, and forming a first passivation layer on the interconnection structure, wherein the first passivation layer is provided with a first opening for exposing a part of interconnection lines in the interconnection structure; forming a metal layer filling the first opening and covering the first passivation layer; patterning the metal layer to form a pad; the bonding pad comprises a first area located in the center and a second area located on the periphery of the first area, and the surface of the second area is higher than that of the first area. According to the manufacturing method, the bonding pad with the step structure with thick periphery and thin center is formed, the defect that the bonding pad is easy to break after the existing lead bonding can be overcome, and the yield of the device is improved. The semiconductor device and the electronic apparatus have similar advantages.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In a semiconductor manufacturing process, when a chip is packaged, a bonding pad on the top layer of the chip needs to be butted with a corresponding bonding pad or a corresponding lead on a lead frame, so that the chip can be connected with an external circuit through the lead frame. Fig. 1A shows a schematic diagram of wire bonding of a device formed with a pad, as shown in fig. 1A, wherein a semiconductor device includes a substrate 100, a device structure, such as PMOS or NMOS, is formed on the substrate 100, and then a metal interconnection structure, illustratively including metal layers M1, M2, M3, UTM, is formed thereon, the metal layers are separated by an interlayer dielectric layer 101, a first passivation layer 102 is formed on the top metal layer UTM, a redistribution line 104 and a pad 105 (dashed line region in the figure) are formed on the first passivation layer 102, the redistribution line 104 and the pad 105 are electrically connected with the underlying metal layer through a contact plug 103 formed in the first passivation layer 102, a second passivation layer 106 is further formed on the first passivation layer 102, an opening exposing the pad 105 is formed in the second passivation layer 106, and a solder ball 107 is bonded to the pad under a bonding force.
It has been recently found that the problem of aluminum pad breakage often occurs after wire bonding of 28nm products, and as shown in fig. 1B, the aluminum pad (dashed area in the figure) is broken after wire bonding, which has a great influence on the product performance and yield.
Therefore, it is desirable to provide a new semiconductor device, a method of manufacturing the same, and an electronic apparatus to at least partially solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can overcome the problem that the bonding pad of the conventional semiconductor device is easy to break after being bonded by a lead.
To overcome the problems presented, one aspect of the present invention provides a method of forming a redistribution pad, comprising: providing a semiconductor substrate, forming an interconnection structure on the semiconductor substrate, and forming a first passivation layer on the interconnection structure, wherein the first passivation layer is provided with a first opening exposing a part of an interconnection line in the interconnection structure; forming a metal layer filling the first opening and covering the first passivation layer; patterning the metal layer to form a pad; the bonding pad comprises a first area located in the center and a second area located on the periphery of the first area, and the surface of the second area is higher than that of the first area.
Further, the shape of the first region corresponds to the shape of a lead solder ball to be bonded with the pad.
Further, the first region is circular in shape.
Further, a redistribution line is also formed while patterning the metal layer to form the pad, a surface of the redistribution line being flush with a surface of the first area.
Further, the thickness in first region is 3um ~ 5um, regional second thickness is 4um ~ 7 um.
Further, the step of patterning the metal layer to form the redistribution line and the pad may include: patterning the metal layer for the first time to form the bonding pad, and enabling the area of the metal layer except the second area of the bonding pad to be flush with the first area of the bonding pad; and patterning the metal layer for a second time to form the redistribution line.
Further, the method of forming a redistribution pad further comprises:
forming a second passivation layer on the first passivation layer, the second passivation layer covering the redistribution line and having a second opening exposing the pad.
According to the manufacturing method of the semiconductor device, the bonding pad with the thick periphery and the thin center and the step structure is formed, so that bonding force acts on the peripheral high steps firstly in the lead bonding process, most of the bonding force can be buffered due to the fact that the periphery of the bonding pad is thick, and when a solder ball really contacts the central low step of the bonding pad, the residual bonding force is not enough to damage an aluminum bonding pad. According to the manufacturing method of the semiconductor device, the thickness of the aluminum in the local area is only increased, and the structure and the thickness of the whole re-wiring aluminum are not changed, so that extra film stress is not introduced, the manufacturing method is easy to realize in the manufacturing process, and the effect is obvious.
Yet another aspect of the present invention provides a semiconductor device, including: a semiconductor substrate on which an interconnect structure is formed, a first passivation layer formed on the interconnect structure, the first passivation layer having a first opening exposing a portion of an interconnect line in the interconnect structure; and the bonding pad is positioned on the first passivation layer and fills the first opening, wherein the bonding pad comprises a first area positioned in the center and a second area positioned at the periphery of the first area, and the surface of the second area is higher than that of the first area.
Further, the shape of the first region corresponds to the shape of a lead solder ball to be bonded with the pad.
Further, the first region is circular in shape.
Further, a redistribution line is included on the first passivation layer and filling the first opening, a surface of the redistribution line being flush with a surface of the first region.
Further, the thickness in first region is 3um ~ 5um, the thickness in second region is 4um ~ 7 um.
Further, the semiconductor device may further include a second passivation layer over the first passivation layer, the second passivation layer covering the redistribution line and having a second opening exposing the pad.
According to the semiconductor device, the bonding pad is of the step structure with thick periphery and thin center, so that the bonding force can be prevented from damaging the bonding pad in the lead bonding process, and the yield and the reliability of the device are improved.
A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the improvement of the performance and yield of the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A illustrates a cross-sectional schematic view of a present semiconductor device with redistribution pads;
FIG. 1B shows a partial photograph of a semiconductor device with broken aluminum pads;
FIG. 2 illustrates a flow chart of steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 3A to 3G are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a plan view illustrating a pad of a semiconductor device formed according to a method of fabricating a semiconductor device according to an embodiment of the present invention;
FIGS. 5A-5C are schematic diagrams illustrating a wire bonding process of a semiconductor device formed in accordance with a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 6 shows a cross-sectional view of a semiconductor device according to an embodiment of the invention;
fig. 7 shows a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As described above, in the conventional semiconductor device, the problem of breaking the aluminum pad after wire bonding is completed is analyzed and considered to be mainly due to the following two reasons:
1) in order to realize more functions of the current semiconductor device, more aluminum PADs (Al PADs) need to be designed per unit area, so that the size of the aluminum PADs is smaller than that of other process products, and the space for releasing bonding force is reduced.
2) The semiconductor device structure of the 28nm technical node is denser, and low-K materials are mostly adopted as interlayer dielectric layers of the interconnection layers, so that the sensitivity of the whole structure of the device to film stress is greatly increased, the thickness of an aluminum bonding pad can not be very thick, generally 3-5 um, and the thickness of the aluminum bonding pad is small, so that the bonding force born by the aluminum bonding pad is reduced, and the lead bonding process is easy to break.
Based on the above analysis, the present invention provides a method for manufacturing a semiconductor device, so as to overcome the problem that an aluminum pad is easily broken after wire bonding. As shown in fig. 2, the manufacturing method includes: step 201, providing a semiconductor substrate, forming an interconnection structure on the semiconductor substrate, and forming a first passivation layer on the interconnection structure, wherein the first passivation layer has a first opening exposing a part of an interconnection line in the interconnection structure; step 202, forming a metal layer which fills the opening and covers the first passivation layer; step 203, patterning the metal layer to form a bonding pad; the pad comprises a first area with a first thickness in the center and a second area with a second thickness on the periphery, wherein the second thickness is larger than the first thickness.
According to the manufacturing method of the semiconductor device, the bonding pad with the thick periphery and the thin center and the step structure is formed, so that bonding force acts on the peripheral high steps firstly in the lead bonding process, most of the bonding force can be buffered due to the fact that the periphery of the bonding pad is thick, and when a solder ball really contacts the central low step of the bonding pad, the residual bonding force is not enough to damage an aluminum bonding pad. According to the manufacturing method of the semiconductor device, the thickness of the aluminum in the local area is only increased, and the structure and the thickness of the whole re-wiring aluminum are not changed, so that extra film stress is not introduced, the manufacturing method is easy to realize in the manufacturing process, and the effect is obvious.
It will be appreciated that although the present invention is presented in terms of the 28nm semiconductor device pad fracture problem, the method is equally applicable to semiconductor devices of other technology nodes.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3G, fig. 4, and fig. 5A to 5C.
First, a semiconductor substrate 300 is provided, an interconnect structure is formed on the semiconductor substrate 300, and a first passivation layer 302 is formed over the interconnect structure, the structure being as shown in fig. 3A.
Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
A device layer, which may include various circuit structures such as NMOS and PMOS transistors, and an interconnection structure are formed on the semiconductor substrate 300, and in this embodiment, the device or the device layer are not shown for the sake of brevity. The interconnect structure may be any of various interconnect structures for electrically connecting to the underlying device layer, and may have any number of metal layers, such as 6 or 7 metal layers, as desired. Illustratively, in this embodiment, the interconnect structure includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a top metal layer UTM, the metal layers are separated by an interlayer dielectric layer 301, and the interconnect layers are connected by a via hole formed in the interlayer dielectric layer 301 and filled with a conductive material, such as copper. The interconnection layer is formed by a method commonly used in the art, such as a dual damascene process, and will not be described herein.
After the interconnect structure is formed, a first passivation layer 302 is formed over the interconnect structure. The first passivation layer 302 may be formed using various suitable passivation layer materials, such as oxide, nitride, oxynitride, or the like, by commonly used PVD, CVD, ALD, or the like processes.
Next, a first opening 303 exposing an underlying metal layer (UTM) is formed in the first passivation layer 302, resulting in the structure shown in fig. 3B.
Illustratively, the first passivation layer 302 is patterned by a suitable photolithography, etching process to form a first opening 303 exposing the underlying metal layer (UTM). The location and number of the first openings 303 are determined according to the design of the interconnect layer and the subsequent redistribution layer, which is not limited by the present invention.
Next, as shown in fig. 3C, a metal layer 305 is formed to fill the first opening 303 and cover the surface of the first passivation layer 302, and the structure is shown in fig. 3C.
The metal layer 305 may be made of various suitable metal materials, and in this embodiment, the metal layer 305 is made of metal aluminum, which may be formed by various deposition processes such as sputtering, PVD, CVD, and the like.
The metal layer 305 is used to fill the first opening 303 to form contact plugs 304 for connecting the top metal layer UTM and subsequently forming pads and redistribution lines, and for making pads and redistribution lines.
The thickness of the metal layer 305 in this embodiment is thicker than the pads and redistribution lines in a conventional process, for example if the thickness of the pads and redistribution lines in a conventional process is 3um to 5um, the thickness of the metal layer 305 here is 4um to 7 um.
Next, the metal layer 305 is patterned for the first time to form a pad, and an area 305A of the metal layer except for the pad is flush with the first area 306A of the pad, and the structure is as shown in fig. 3D.
Specifically, the metal layer 305 is patterned by a patterning process such as photolithography and etching to form a pad, and a region 305A of the metal layer other than the pad is flush with the first region 306A of the pad. That is, after the metal layer 305 is patterned for the first time, a first region 306A of the pad is formed, the center of which is recessed relative to the periphery, and a second region 306B of the pad is formed, the periphery of which is protruded relative to the first region, so that the pad is in a step structure, and a part of the metal layer in other regions is removed, so that the metal layer 305A in the region except the pad is flush with the first region 306A of the pad, for example, the thickness of the metal layer 305A in the region except the pad is 3um to 5um, which is the thickness of a conventional pad.
Wherein the etching process comprises various suitable wet etching processes or dry etching processes. The wet process may use a mixture of phosphoric acid, acetic acid, nitric acid and water in a certain ratio, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The dry etching may use Cl2 or a halogen element gas as an etching gas.
In this embodiment, the pad includes a first region 306A located at the center and a second region 306B located around the first region 306A, and the surface of the second region is higher than the surface of the first region. Illustratively, the thickness of the second region may be the thickness of the metal layer 305, for example, 4um to 7um, and the thickness of the first region may be the thickness of the pad in the conventional process, for example, 3um to 5 um.
Further, as shown in fig. 4, in the present embodiment, it is preferable that the first region 306A of the pad has a circular shape because the solder ball of the wire bonding with the pad has a spherical shape, so that the periphery of the pad can buffer and release the bonding force according to the stress distribution completely consistent with the solder ball of the wire. Of course, it is understood that when the solder balls are in other shapes, the shape of the first region 306A may be in other shapes corresponding to the shape of the solder balls to be bonded to the pads.
Next, the metal layer 305A is patterned a second time to form the redistribution line 307, the surface of the redistribution line 307 being flush with the surface of the first region 306A, resulting in the structure shown in fig. 3E.
Specifically, the metal layer 305A is patterned by a patterning process such as photolithography and etching to form the redistribution line 307, and a surface of the redistribution line 307 is flush with a surface of the first region 306A. The shape of the redistribution lines is determined by the specific layout design and is not limited herein. Wherein the etching process comprises various suitable wet etching processes or dry etching processes. The wet process may use a mixture of phosphoric acid, acetic acid, nitric acid and water in a certain ratio, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The dry etching may use Cl2Or a halogen element gas as an etching gas.
Next, a second passivation layer 308 is formed on the first passivation layer 302, the second passivation layer 308 covering the pads and the redistribution lines 307, and the resulting structure is shown in fig. 3F.
The second passivation layer 308 may be formed by a conventional PVD (material vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), spin coating, or the like, using various suitable passivation layer materials such as oxide, nitride, oxynitride, or the like.
Finally, a second opening 309 is formed in the second passivation layer 308 exposing the pad, resulting in the structure shown in fig. 3G.
Specifically, the second passivation layer 308 is patterned by a common photolithography, etching, or the like process to form a second opening 309 in the second passivation layer 308 to expose the pad, so that the pad can be subsequently bonded for connection with a wire.
Now that the process steps performed by the method according to the embodiment of the present invention are completed, it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps but also other necessary steps before, during or after the above steps.
The wire bonding process of the pad formed by the method for manufacturing a semiconductor device of the present embodiment is described below with reference to fig. 5A to 5C. First, as shown in fig. 5A, when the solder ball 310 is bonded to the pad, there is a bonding force in each orientation of the solder ball 310, and when bonding is performed, as shown in fig. 5B, the solder ball 310 first contacts the second region 306B with a larger thickness (i.e., a higher region) around the pad, and since the second region 306B has a larger thickness, most of the bonding force can be buffered, and the pad itself is not easily damaged. When the ball of wirebonds 310 actually contacts the first region 306A, the residual bonding force is not sufficient to break the bonding force.
According to the manufacturing method of the semiconductor device, the bonding pad with the thick periphery and the thin center and the step structure is formed, so that bonding force acts on the peripheral high steps firstly in the lead bonding process, most of the bonding force can be buffered due to the fact that the periphery of the bonding pad is thick, and when a solder ball really contacts the central low step of the bonding pad, the residual bonding force is not enough to damage the aluminum bonding pad. According to the manufacturing method of the semiconductor device, the thickness of the aluminum in the local area is only increased, and the structure and the thickness of the whole re-wiring aluminum are not changed, so that extra film stress is not introduced, the manufacturing method is easy to realize in the manufacturing process, and the effect is obvious.
Example two
The present invention also provides a semiconductor device, as shown in fig. 6, including: a semiconductor substrate 600 having an interconnect structure formed on the semiconductor substrate 600, the interconnect structure having a first passivation layer 602 formed thereon, the first passivation layer having a first opening 603 exposing an interconnect line in an underlying interconnect structure; the first opening 603 in the first passivation layer is filled with a conductive material, a redistribution line 604 and a pad 605 being formed on the first passivation layer 602; a second passivation layer 606 is formed on the first passivation layer 602, the second passivation layer 606 covers the redistribution line 604 and has a second opening 607 exposing the pad 605, wherein the pad 605 includes a central first region 6050 and a second region 6051 surrounding the first region, and a surface of the second region 6051 is higher than a surface of the first region 6050.
The semiconductor substrate 600 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate 600 is single crystal silicon.
The device layer may include various circuit structures such as NMOS, PMOS transistors, and in this embodiment, the device or device layer is not shown for the sake of brevity.
The interconnect structure may be any of various interconnect structures for electrically connecting to the underlying device layer, and may have any number of metal layers, such as 6 or 7 metal layers, as desired. Illustratively, in the present embodiment, the interconnect layers include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a top metal layer UTM, the metal layers are separated by an interlayer dielectric layer 601, and the interconnect layers are connected by a via hole formed in the interlayer dielectric layer 601 and filled with a conductive material, such as copper. Dielectric layer 601 can be various low K materials such as porous SiCOH or ultra low K materials based on porous SiCOH.
The first passivation layer 602 may be formed of any suitable passivation layer material, such as an oxide, nitride, oxynitride, or the like. The first passivation layer has a first opening 603 exposing the underlying interconnect layer, and a contact plug connecting the top metal layer UTM and the redistribution line 604 to the pad 605 may be formed by filling a conductive material into the first opening 603.
The re-wiring 604 and the pad 605 are formed on the surface of the first passivation layer 602, which may be formed by depositing a conductive material and patterning. The re-wiring 604 and the pad 605 may be made of a suitable metal material, and in this embodiment, the re-wiring 604 and the pad 605 are made of a metal aluminum material, for example.
In this embodiment, the pad 605 includes a first region 6050 located at the center and a second region 6051 located around the first region 6050, and the surface of the second region 6051 is higher than the surface of the first region 6050. For example, the thickness of the first region 6050 may be the thickness of a bonding pad in a conventional process, for example, 3um to 5 um; the thickness of the second region 6051 may be, for example, 4um to 7 um. The redistribution line 604 has the same thickness as the first region. The shape of the first region 6050 corresponds to the shape of a solder ball to be bonded to the pad, and when the solder ball is spherical, the shape of the first region 6050 is circular.
Various suitable passivation layer materials may be used for the second passivation layer 308, such as oxide, nitride, oxynitride, or the like. A second opening 309 is formed in the second passivation layer 308 exposing the pad 605 so that the pad 605 can be subsequently bonded for wire connection.
The pad of the semiconductor device of the embodiment has a step structure with thick periphery and thin center, so that the pad can be prevented from being damaged by bonding force in the lead bonding process, and the yield and the reliability of the device are improved.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: a semiconductor substrate on which an interconnect structure is formed, a first passivation layer formed on the interconnect structure, the first passivation layer having a first opening exposing a portion of an interconnect line in the interconnect structure; and the bonding pad is positioned on the first passivation layer and fills the first opening, wherein the bonding pad comprises a first area positioned in the center and a second area positioned at the periphery of the first area, and the surface of the second area is higher than that of the first area.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Fig. 7 shows an example of a cellular phone. The exterior of the cellular phone 700 is provided with a display portion 702, operation buttons 703, an external connection port 704, a speaker 705, a microphone 706, and the like, which are included in a housing 701.
According to the electronic device provided by the embodiment of the invention, the bonding pad of the semiconductor device is of the step structure with thick periphery and thin center, so that the bonding force can be prevented from damaging the bonding pad in the lead bonding process, and the yield and reliability of the device are improved, so that the electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (12)

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, forming an interconnection structure on the semiconductor substrate, and forming a first passivation layer on the interconnection structure, wherein the first passivation layer is provided with a first opening exposing a part of an interconnection line in the interconnection structure;
forming a metal layer filling the first opening and covering the first passivation layer;
patterning the metal layer to form a pad;
the bonding pad comprises a first area positioned in the center and a second area positioned at the periphery of the first area, wherein the surface of the second area is higher than that of the first area;
forming a redistribution line while patterning the metal layer to form the pad, a surface of the redistribution line being flush with a surface of the first area.
2. The method of manufacturing according to claim 1, wherein a shape of the first region corresponds to a shape of a solder ball of a wire to be bonded to the pad.
3. The method of manufacturing of claim 2, wherein the first region is circular in shape.
4. The method of claim 1, wherein the first region has a thickness of 3um to 5um, and the second region has a thickness of 4um to 7 um.
5. The method of manufacturing of claim 1, wherein patterning the metal layer to form the redistribution line and the pad comprises:
patterning the metal layer for the first time to form the bonding pad, and enabling the area of the metal layer except the second area of the bonding pad to be flush with the first area of the bonding pad;
and patterning the metal layer for a second time to form the redistribution line.
6. The method of manufacturing according to claim 1, further comprising:
forming a second passivation layer on the first passivation layer, the second passivation layer covering the redistribution line and having a second opening exposing the pad.
7. A semiconductor device, comprising:
a semiconductor substrate on which an interconnect structure is formed, a first passivation layer formed on the interconnect structure, the first passivation layer having a first opening exposing a portion of an interconnect line in the interconnect structure;
a pad on the first passivation layer and filling the first opening;
the bonding pad comprises a first area positioned in the center and a second area positioned at the periphery of the first area, wherein the surface of the second area is higher than that of the first area;
a redistribution line on the first passivation layer and filling the first opening, a surface of the redistribution line being flush with a surface of the first region.
8. The semiconductor device according to claim 7, wherein a shape of the first region corresponds to a shape of a wire solder ball to be bonded to the pad.
9. The semiconductor device according to claim 8, wherein the first region is circular in shape.
10. The semiconductor device of claim 7, further comprising a second passivation layer over the first passivation layer, the second passivation layer covering the redistribution line and having a second opening exposing the pad.
11. A semiconductor device according to any of claims 7-10, wherein the first region has a thickness of 3um to 5um and the second region has a thickness of 4um to 7 um.
12. An electronic device comprising a semiconductor device according to any one of claims 7 to 11 and an electronic component connected to the semiconductor device.
CN201710060662.1A 2017-01-25 2017-01-25 Semiconductor device, manufacturing method thereof and electronic device Active CN108346618B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710060662.1A CN108346618B (en) 2017-01-25 2017-01-25 Semiconductor device, manufacturing method thereof and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710060662.1A CN108346618B (en) 2017-01-25 2017-01-25 Semiconductor device, manufacturing method thereof and electronic device

Publications (2)

Publication Number Publication Date
CN108346618A CN108346618A (en) 2018-07-31
CN108346618B true CN108346618B (en) 2021-09-21

Family

ID=62962925

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710060662.1A Active CN108346618B (en) 2017-01-25 2017-01-25 Semiconductor device, manufacturing method thereof and electronic device

Country Status (1)

Country Link
CN (1) CN108346618B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346618B (en) * 2017-01-25 2021-09-21 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method thereof and electronic device
CN117080163B (en) * 2023-10-11 2024-02-23 芯耀辉科技有限公司 Chip structure and forming method thereof, chip packaging structure and forming method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278551A (en) * 1990-03-28 1991-12-10 Nec Corp Semiconductor device
JPH0590327A (en) * 1991-09-27 1993-04-09 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
CN105609423A (en) * 2014-11-19 2016-05-25 英飞凌科技股份有限公司 Method of forming a bondpad and bondpad
CN108346618A (en) * 2017-01-25 2018-07-31 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and preparation method thereof, electronic device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3863161B2 (en) * 2004-01-20 2006-12-27 松下電器産業株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278551A (en) * 1990-03-28 1991-12-10 Nec Corp Semiconductor device
JPH0590327A (en) * 1991-09-27 1993-04-09 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
CN105609423A (en) * 2014-11-19 2016-05-25 英飞凌科技股份有限公司 Method of forming a bondpad and bondpad
CN108346618A (en) * 2017-01-25 2018-07-31 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and preparation method thereof, electronic device

Also Published As

Publication number Publication date
CN108346618A (en) 2018-07-31

Similar Documents

Publication Publication Date Title
US10199273B2 (en) Method for forming semiconductor device with through silicon via
US10867969B2 (en) Multi-wafer stacking structure and fabrication method thereof
US20100164062A1 (en) Method of manufacturing through-silicon-via and through-silicon-via structure
US9478463B2 (en) Device and method for improving RF performance
US9418949B2 (en) Semiconductor device having voids between top metal layers of metal interconnects
US11600552B2 (en) Semiconductor device having a through silicon via and methods of manufacturing the same
US11043481B2 (en) Method of manufacturing semiconductor package structure
US11043469B1 (en) Method of forming three dimensional semiconductor structure
KR20130023865A (en) Semiconductor devices having through electrodes and method for fabricating the same
US20130140688A1 (en) Through Silicon Via and Method of Manufacturing the Same
US20180366540A1 (en) Semiconductor devices comprising vias and capacitors
CN107919342B (en) Method for forming redistribution bonding pad, semiconductor device and electronic device
CN108346618B (en) Semiconductor device, manufacturing method thereof and electronic device
CN107305840B (en) Semiconductor device, manufacturing method thereof and electronic device
US7375397B2 (en) Semiconductor device having an SOI structure and method for manufacturing the same
TWI749847B (en) Semiconductor device structure with air gap and method for forming the same
US20070123021A1 (en) Circuit under pad structure and bonding pad process
US20150017798A1 (en) Method of manufacturing through-silicon-via
CN109712953B (en) Manufacturing method of semiconductor device and semiconductor device
CN109285822B (en) Bonding pad, semiconductor device, manufacturing method of semiconductor device and electronic device
US20200185345A1 (en) Semiconductor device
KR102572413B1 (en) 3D memory device and manufacturing method thereof
CN108206140B (en) Semiconductor device, manufacturing method thereof and electronic device
CN109727865B (en) Semiconductor device, manufacturing method thereof and electronic device
US20140264833A1 (en) Semiconductor package and method for fabricating the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant