CN108257868B - 采用非选择性外延的自对准锗硅hbt器件的工艺方法 - Google Patents
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Abstract
本发明公开了一种采用非选择性外延的自对准锗硅HBT器件的工艺方法,在形成集电极后,淀积第一层SiO2层,非选择性生长锗硅外延层;淀积SiO2/多晶硅/SiO2叠层;光刻和干法刻蚀所述SiO2/多晶硅/SiO2叠层;淀积第四层SiO2层,回刻形成侧墙;在有源区选择性生长单晶或多晶硅层,再淀积第五层SiO2层;淀积平坦化的有机介质层;多晶硅顶端的有机介质层和第五层SiO2层去除;将发射极窗口打开;回刻形成内侧墙;在发射极窗口内淀积重掺杂砷多晶硅,然后刻蚀发射极和基极多晶硅形成发射极和基极。本发明能够很简单地和现有的CMOS工艺集成,容易形成适合大规模量产的工艺流程。
Description
技术领域
本发明涉及本导体集成电路领域,特别是涉及一种采用非选择性外延的自对准锗硅HBT(锗硅异质结双极型三极管)器件的工艺方法。
背景技术
采用P型多晶硅抬高外基区,发射极和外基区之间采用内侧墙的自对准器件结构,可以同时降低基极电阻和基极-集电极电容,这样的锗硅异质结双极型三极管(HBT)器件可以得到大于300GHz的最高振荡频率fmax,其性能可以和III-V器件相当,被广泛用于光通信和毫米波应用。
SiGe HBT器件采用较小能带宽度的掺有杂质硼的锗硅碳合金为基极,由于发射极和基极有能带差,可以在保证同样的直流电流放大倍数HFE时采用较高的基区掺杂,从而得到较高的fmax。
基极电阻包括外基区电阻和本征基区电阻(发射极下的电阻),是提升fmax的重要的参数,要降低基极电阻,要尽可能提高基区的掺杂浓度,及降低发射极窗口和侧墙的宽度。
锗硅HBT的截止频率fT和最高振荡频率由以下公式表征:
现有技术中有两种方案来形成自对准的锗硅HBT器件,一是选择性锗硅外延方案,结合图1-3所示,工艺流程如下:
在形成集电极后,淀积SiO2(二氧化硅)/重掺硼多晶硅/SiO2/SiN(氮化硅)/SiO2叠层,然后打开发射极窗口,干法刻蚀停在底层SiO2上。
湿法刻蚀和清洗后,选择性外延(只在有源区和多晶硅区)生长锗硅,然后淀积介质和反刻形成内侧墙。
湿法刻蚀和清洗后,淀积重掺砷多晶硅,然后刻蚀发射极和基极多晶硅形成发射极和基极。
另一种方案采用非选择性锗硅外延,结合图4-6所示,工艺流程如下:
在形成集电极后,采用非选择性外延方法生长锗硅层,然后淀积SiO2/SiN/SiO2叠层。
打开发射极窗口,干法刻蚀SiO2/SiN停在底层氧化硅上。
淀积SiO2,回刻形成内侧墙。
湿法刻蚀和清洗后,淀积重掺砷多晶硅和SiO2叠层,光刻和刻蚀形成发射极多晶硅。
淀积SiO2,回刻形成内侧墙,并去除EP(发射极多晶硅)外SiN上的氧化硅。
用热磷酸去除SiN,选择性高硼掺杂Si(硅)外延形成外基区。
光刻和刻蚀形成基极。
第一种工艺实现方法比较简单,但需要做选择性锗硅外延,在器件横向尺寸逐步降低的情况下,要得到无缺陷的外延层有挑战;而第二种方案采用锗硅非选择性外延工艺,但最后要在EP和侧墙下的区域,其横向尺寸大于高度的区域,选择性的生长高掺杂的多晶硅,掺杂浓度达到满足器件要求的1020cm-3是非常困难的,很难在硅片制造厂得到稳定量产的工艺。
发明内容
本发明要解决的技术问题是提供一种采用非选择性外延的自对准锗硅HBT器件的工艺方法,能够很简单地和现有的CMOS工艺集成,容易形成适合大规模量产的工艺流程。
为解决上述技术问题,本发明的采用非选择性外延的自对准锗硅HBT器件的工艺方法,包括如下步骤:
步骤1、在形成集电极后,淀积第一层SiO2层,打开锗硅单晶外延窗口,在去除所述锗硅单晶外延窗口内的SiO2层和清洗后,非选择性生长锗硅外延层;
步骤2、在所述锗硅外延层上端,依次淀积第二层SiO2层、多晶硅层、第三层SiO2层,即淀积SiO2/多晶硅/SiO2叠层;
步骤3、用牺牲发射极窗口光刻和干法刻蚀所述SiO2/多晶硅/SiO2叠层,停在第三层SiO2层,除发射极区域外其余区域全部刻除;
步骤4、淀积第四层SiO2层,回刻形成侧墙,同时要保证多晶硅上有SiO2留存;
步骤5、在有源区二氧化硅去除后,侧墙和多晶硅顶部留存SiO2,在有源区选择性生长单晶或多晶硅层,再淀积第五层SiO2层,所述第五层SiO2层覆盖器件的全部上端面;
步骤6、在所述第五层SiO2层的上端,淀积平坦化的有机介质层;
步骤7、用回刻方法把多晶硅顶端的有机介质层和第五层SiO2层去除;
步骤8、干法刻蚀多晶硅,干刻将发射极窗口打开;
步骤9、在所述发射极窗口10内淀积SiN/SiO2叠层或无定型硅,回刻形成内侧墙;
步骤10、湿法刻蚀和清洗所述发射极窗口后,在该发射极窗口内淀积重掺杂砷多晶硅,然后刻蚀发射极和基极多晶硅形成发射极和基极。
本发明的方法是一种采用非选择性锗硅外延方案,通过牺牲层的淀积和反刻、形成侧墙及有机介质回刻等技术,来实现锗硅自对准器件。
本发明的方法采用量产的生产线上的成熟工艺的整合,可保证整个工艺流程的稳定性。
本发明的有益效果为,为得到较高的器件性能,自对准的锗硅HBT需要对基区的横向和纵向尺寸进行缩小,由于采用了成熟的低温锗硅非选择性外延工艺方法,只需缩小纵向尺寸就可以达到要求,而选择性外延则需要对横向和纵向同时缩小。相比采用非选择性外延的已有工艺方法,其采用的选择性氮化硅去除工艺方法,对工艺的控制要求高,而选择性的多晶填充,要达到较高的掺杂浓度需要特殊设备;而本发明的单项工艺方法,都是芯片制造厂的标准工艺,其外基区的选择性外延对工艺只有基本要求,掺杂采用离子注入,简单易行,适合量产。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明:
图1-3是现有的采用选择性锗硅外延形成自对准的锗硅HBT器件示意图;
图4-6是现有的采用非选择性锗硅外延形成自对准的锗硅HBT器件示意图;
图7是非选择性生长锗硅外延层示意图;
图8是淀积SiO2/多晶硅/SiO2叠层示意图;
图9是回刻形成侧墙示意图;
图10是生长硅、再淀积SiO2层示意图;
图11是淀积平坦化的有机介质层示意图;
图12是去除多晶硅顶端的有机介质和SiO2层示意图;
图13是打开发射极窗口示意图;
图14是形成内侧墙示意图;
图15是形成发射极和基极示意图;
图16是所述采用非选择性外延的自对准锗硅HBT器件的工艺方法一实施例流程图。
具体实施方式
参见图16所示,所述采用非选择性外延的自对准锗硅HBT器件的工艺方法在下面的实施例中具体实施方式如下:
结合图8所示,在所述锗硅外延层2上端,依次淀积第二层SiO2层3、多晶硅层4、第三层SiO2层5,即淀积SiO2/多晶硅/SiO2叠层。第二层SiO2层3的厚度为多晶硅层4的厚度为第三层SiO2层5的厚度为
结合图9所示,用牺牲发射极窗口(反版)光刻和干法刻蚀所述SiO2/多晶硅/SiO2叠层,停在第三层SiO2层5,除发射极区域外其余区域都刻除,牺牲发射极窗口的尺寸在0.2~0.3微米。
结合图12所示,用回刻方法把多晶硅顶端的有机介质层9和第五层SiO2层8去除,有源区需要有部分有机介质层9存留以保证氧化硅完整,然后去除有机介质层。
结合图13所示,干法刻蚀多晶硅,由于除多晶硅顶部外,其他区域有氧化硅保护,干刻把发射极窗口10打开。
本发明的方法可很简单地和现有的CMOS工艺集成,并且所用的单项工艺都是半导体制造厂成熟工艺,如非选择性锗硅低温外延,有机介质淀积和回刻等,很容易形成适合大规模量产的工艺流程。其中低温锗硅非选择性外延,可以在很大的范围内形成所需的锗浓度,掺杂硼百分比,和碳浓度,而选择性外延,由于不同的掺杂比会影响外延生长的选择性,这样在器件研发时多次实验才能得到所需的杂质分布,对研发进度造成压力。同时,本发明的方法在外基区采用选择性外延,淀积层可以是单晶或多晶,工艺复杂度较低,器件性能优越。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员可做出许多变形和改进,这些也应视为本发明的保护范围。
Claims (9)
1.一种采用非选择性外延的自对准锗硅HBT器件的工艺方法,其特征在于,包括如下步骤:
步骤1、在形成集电极后,淀积第一层二氧化硅SiO2层,打开锗硅单晶外延窗口,在去除所述锗硅单晶外延窗口内的二氧化硅SiO2层和清洗后,非选择性生长锗硅外延层;
步骤2、在所述锗硅外延层上端,依次淀积第二层二氧化硅SiO2层、多晶硅层、第三层二氧化硅SiO2层,即淀积二氧化硅SiO2/多晶硅/二氧化硅SiO2叠层;
步骤3、用牺牲发射极窗口光刻和干法刻蚀所述二氧化硅SiO2/多晶硅/二氧化硅SiO2叠层,停在第三层二氧化硅SiO2层,除发射极区域外其余区域全部刻除;
步骤4、淀积第四层二氧化硅SiO2层,回刻形成侧墙,同时要保证多晶硅上有二氧化硅SiO2留存;
步骤5、在有源区二氧化硅去除后,侧墙和多晶硅顶部留存二氧化硅SiO2,在有源区选择性生长单晶或多晶硅层,再淀积第五层二氧化硅SiO2层,所述第五层二氧化硅SiO2层覆盖器件的全部上端面;
步骤6、在所述第五层二氧化硅SiO2层的上端,淀积平坦化的有机介质层;
步骤7、用回刻方法把多晶硅顶端的有机介质层和第五层二氧化硅SiO2层去除;
步骤8、干法刻蚀多晶硅,将发射极窗口打开;
步骤9、在所述发射极窗口10内淀积氮化硅SiN/二氧化硅SiO2叠层或无定型硅,回刻形成内侧墙;
步骤10、湿法刻蚀和清洗所述发射极窗口后,在该发射极窗口内淀积重掺杂砷多晶硅,然后刻蚀发射极和基极多晶硅形成发射极和基极。
4.如权利要求1所述的方法,其特征在于:步骤3所述牺牲发射极窗口的尺寸为0.2~0.3微米。
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US8823140B2 (en) * | 2012-11-13 | 2014-09-02 | Avogy, Inc. | GaN vertical bipolar transistor |
US9159822B2 (en) * | 2014-02-24 | 2015-10-13 | International Business Machines Corporation | III-V semiconductor device having self-aligned contacts |
US9356097B2 (en) * | 2013-06-25 | 2016-05-31 | Globalfoundries Inc. | Method of forming a bipolar transistor with maskless self-aligned emitter |
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US8823140B2 (en) * | 2012-11-13 | 2014-09-02 | Avogy, Inc. | GaN vertical bipolar transistor |
US9356097B2 (en) * | 2013-06-25 | 2016-05-31 | Globalfoundries Inc. | Method of forming a bipolar transistor with maskless self-aligned emitter |
US9159822B2 (en) * | 2014-02-24 | 2015-10-13 | International Business Machines Corporation | III-V semiconductor device having self-aligned contacts |
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