CN108230995B - 显示元件、有机发光显示装置和数据驱动器 - Google Patents

显示元件、有机发光显示装置和数据驱动器 Download PDF

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CN108230995B
CN108230995B CN201711206946.3A CN201711206946A CN108230995B CN 108230995 B CN108230995 B CN 108230995B CN 201711206946 A CN201711206946 A CN 201711206946A CN 108230995 B CN108230995 B CN 108230995B
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transistor
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CN108230995A (zh
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金宰成
吴民友
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LG Display Co Ltd
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Abstract

本发明涉及一种显示元件、有机发光显示装置和数据驱动器。所述显示元件包括：包括第一电极和第二电极的有机发光二极管；驱动晶体管，所述驱动晶体管包括被提供数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；第一晶体管，所述第一晶体管电连接在用于提供所述数据电压的数据线与所述驱动晶体管的第一节点之间；第二晶体管，所述第二晶体管电连接在用于提供初始化电压的初始化电压线与所述驱动晶体管的第二节点之间；和电容器，所述电容器电连接在所述驱动晶体管的第一节点与第二节点之间。

Description

显示元件、有机发光显示装置和数据驱动器
相关申请的交叉引用
本申请要求2016年12月22日提交的韩国专利申请No.10-2016-0177001的优先权，为了所有目的通过参考将该专利申请结合在此，如同在此完全阐述一样。
技术领域
本发明涉及一种显示元件和显示图像的显示装置。
背景技术
近来作为显示装置吸引大量关注的有机发光显示装置使用自发光的有机发光二极管(OLED)，因而具有高响应速度和增加的发光效率、亮度和视角的优点。
在有机发光显示装置中，包括OLED的像素以矩阵形式设置并且控制响应于栅极信号而被选择的子像素的亮度。显示装置的每个像素包括OLED和用于驱动OLED的驱动电路。每个像素内的用于OLED的驱动电路包括晶体管和存储电容器。
显示装置的每个像素中的驱动电路尺寸增加，这导致较低的开口率并且使得难以执行高速操作。此外，驱动显示装置的每个像素中的驱动电路的驱动器的面积增加，使得难以实现窄边框。
发明内容
因此，本发明的实施方式旨在提供一种基本上克服了由于相关技术的限制和缺点而导致的一个或多个问题的显示元件、有机发光显示装置和数据驱动器。
本发明的一个方面是提供一种能够增加开口率并且能够执行高速操作的显示元件和显示装置。
本发明的另一个方面是提供一种能够减小驱动器的面积，从而实现窄边框的显示元件和显示装置。
在下面的描述中将列出附加特征和方面，这些特征和方面的一部分从下面的描述将是显而易见的，或者可从本文提供的发明构思的实施领会到。通过在说明书或其导出物、权利要求书以及附图中具体指出的结构可实现和获得本发明构思的其他特征和方面。
为了实现本发明构思的这些和其他方面，如在此具体化和概括描述的，根据本发明的一个方面，提供了一种显示元件，包括：包括第一电极和第二电极的有机发光二极管；驱动晶体管，所述驱动晶体管包括被提供数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；第一晶体管，所述第一晶体管电连接在用于提供所述数据电压的数据线与所述驱动晶体管的第一节点之间；第二晶体管，所述第二晶体管电连接在用于提供初始化电压的初始化电压线与所述驱动晶体管的第二节点之间；和电容器，所述电容器电连接在所述驱动晶体管的第一节点与第二节点之间。
根据本发明的另一个方面，提供了一种显示装置，包括：位于多条数据线和多条栅极线的交叉部分处的多个像素；向所述多个像素提供公共栅极信号的多条公共栅极线；共同地连接至所述多条公共栅极线的公共栅极连线；向所述多个像素提供初始化电压的多条初始化电压线；和共同地连接至所述多条初始化电压线的初始化电压连线，其中所述多个像素的每一个包括：包括第一电极和第二电极的有机发光二极管；驱动晶体管，所述驱动晶体管包括被提供来自所述多条数据线中的一条数据线的数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；第一晶体管，所述第一晶体管电连接在所述一条数据线与所述驱动晶体管的第一节点之间，并且通过经由所述多条栅极线中的一条栅极线提供的栅极信号切换；第二晶体管，所述第二晶体管电连接在所述多条初始化电压线中的一条初始化电压线与所述驱动晶体管的第二节点之间，并且通过经由所述多条公共栅极线中的一条公共栅极线提供的公共栅极信号切换；和电容器，所述电容器电连接在所述驱动晶体管的第一节点与第二节点之间。
根据本发明的再一个方面，提供了一种数据驱动器，包括：数据单元，所述数据单元连接至数据线并且配置成通过所述数据线向像素提供数据电压；公共栅极信号供给单元，所述公共栅极信号供给单元连接至公共栅极连线并且配置成通过所述公共栅极连线向所述像素提供公共栅极信号；和初始化电压供给单元，所述初始化电压供给单元连接至初始化电压连线并且配置成通过所述初始化电压连线向所述像素提供初始化电压。
应当理解，本发明前面的大体性描述和下面的详细描述都是示例性的和解释性的，意在对要求保护的本发明提供进一步的解释。
附图说明
被包括用来给本发明提供进一步理解并且并入本申请组成本申请一部分的附图图解了本发明的实施方式，并与说明书一起用于解释各原理。在附图中：
图1是根据示例性实施方式的显示装置的构造图；
图2是图1中所示的数据驱动器的构造图；
图3图解了设置在图1所示的显示装置中的第X数据线与第Y栅极线之间的交叉部分处的像素的示例性等效电路图；
图4图解了在图1所示的显示装置中，在一个帧周期期间公共栅极信号和栅极线上的栅极信号的信号波形；
图5图解了在图1所示的显示装置中，在一个帧周期期间单个像素的驱动电路中的信号波形；
图6图解了在图1所示的显示装置中，在一个帧周期期间单个像素的驱动电路中的信号波形的另一示例；
图7到图9图解了在图1所示的显示装置中，在一个帧周期期间各个像素之一的等效电路图；以及
图10图解了根据另一示例性实施方式，在图1所示的显示装置中，在一个帧周期期间单个像素的驱动电路中的信号波形。
具体实施方式
下文中，将参照附图详细描述一些实施方式。当参考标记指代每幅图的组件时，尽管相同的组件显示在不同的图中时，但仍尽可能由相同的参考标记指代相同的组件。此外，当认为对相关已知构造或功能的描述会使本发明的主旨不清楚时，将省略其描述。
此外，在描述本发明的组件时，可使用诸如“第一”、“第二”、“A”、“B”、“(a)”、“(b)”等之类的术语。这些术语仅用于彼此区分组件。因此，相应组件的本质、等级、次序或编号不被相应术语限制。应当理解，当称一元件“连接至”或“接合至”另一元件时，其可直接连接至或直接接合至另一元件，可在之间“插入”再一元件的情况下连接至或接合至另一元件，或者经由再一元件“连接至”或“接合至”另一元件。
图1是根据示例性实施方式的显示装置的构造图。
参照图1，根据本发明示例性实施方式的显示装置100包括显示面板110、数据驱动器120、栅极驱动器130、控制器140等。
在显示面板110中，多条数据线DL1、DL2、DL3、…、DLm沿第一方向设置，多条栅极线GL1、GL2、…、GLn沿与第一方向交叉的第二方向设置，并且多个像素P以矩阵形式设置。多个像素的每一个对应于在显示面板110中发光的显示元件。
当具体栅极线GL开启时，数据驱动器120将从控制器140接收的图像数据Data’转换为模拟形式的数据电压Vdata并将数据电压Vdata提供至数据线DL1、DL2、DL3、…、DLm，以驱动数据线DL1、DL2、DL3、…、DLm。将参照图2详细描述数据驱动器120。
栅极驱动器130通过在控制器140的控制下按顺序给栅极线GL1、GL2、…、GLn提供ON(开)电压或OFF(关)电压栅极信号，按顺序驱动栅极线GL1、GL2、…、GLn。根据驱动方法，栅极驱动器130可位于显示面板110的仅一侧或两侧上。
此外，栅极驱动器130可包括多个栅极驱动器集成电路，多个栅极驱动器集成电路可通过带式自动焊接(TAB)方法或玻上芯片(COG)方法连接至显示面板110的接合焊盘，或者以面板内栅极(GIP)型实现并直接设置在显示面板110中，或者必要的话可集成设置在显示面板110中。
多个栅极驱动器集成电路的每一个可包括移位寄存器、电平移位器等。
控制器140给数据驱动器120和栅极驱动器130提供控制信号，以控制数据驱动器120和栅极驱动器130。
控制器140根据每帧中实现的时序开始扫描，将从主机系统输入的图像数据Data转换为在数据驱动器120中使用的数据信号格式，输出转换后的图像数据Data’，并且根据扫描在适当的时间处控制数据驱动。
除了将从主机系统输入的图像数据Data转换为在数据驱动器120中使用的数据信号格式并输出转换后的图像数据Data’以外，控制器140还接收诸如垂直同步信号Vsync、水平同步信号Hsync、输入数据使能信号、时钟信号等之类的时序信号，产生各种控制信号，并且将控制信号输出至数据驱动器120和栅极驱动器130，以便控制数据驱动器120和栅极驱动器130。
例如，为了控制栅极驱动器130，控制器140输出包括栅极起始脉冲(GSP)、栅极移位时钟(GSC)、栅极输出使能(GOE)信号等的栅极控制信号GCS。
为了控制数据驱动器120，控制器140输出包括源极起始脉冲(SSP)、源极采样时钟(SSC)、源极输出使能(SOE)信号等的数据控制信号DCS。
参照图1，显示装置100可进一步包括电源控制器150，电源控制器150配置成给显示面板110、数据驱动器120和栅极驱动器130提供各种电压或电流，或者控制要提供给它们的各种电压或电流。电源控制器150还可称为电源管理集成电路(PMIC)。
显示装置100包括给多个像素提供公共栅极信号的多条公共栅极线CGL1、CGL2、…、CGLn；共同地连接至多条公共栅极线CGL1、CGL2、…、CGLn的公共栅极连线160；给多个像素提供初始化电压Vini的多条初始化电压线VIL1、VIL2、VIL3、…、VILm；以及共同地连接至多条初始化电压线VIL1、VIL2、VIL3、…、VILm的初始化电压连线170。公共栅极信号通过多条公共栅极线CGL1、CGL2、…、CGLn和公共栅极连线160提供至每个像素，并且初始化电压Vini通过多条初始化电压线VIL1、VIL2、VIL3、…、VILm和初始化电压连线170提供至每个像素，这将在后面参照图3到图8进行描述。
图2是图1中所示的数据驱动器的构造图。参照图2，数据驱动器120可包括多个源极驱动器集成电路，多个源极驱动器集成电路可通过带式自动焊接(TAB)方法或玻上芯片(COG)方法连接至显示面板110的接合焊盘，或者可直接设置在显示面板110上，或者必要的话可集成设置在显示面板110中。
多个源极驱动器集成电路可以以膜上芯片(COF)型实现。在多个源极驱动器集成电路的每一个中，一端接合至至少一个源极印刷电路板，另一端接合至显示面板110。
数据驱动器120可包括数据单元122、公共栅极信号供给单元124和初始化电压供给单元126。
数据单元122连接至数据线DL1、DL2、DL3、…、DLm并通过数据线DL1、DL2、DL3、…、DLm给像素提供数据电压。数据单元122包括移位寄存器单元、锁存单元、伽马电压产生单元、数字-模拟转换器(下文中简称为DA转换器)和输出电路单元。
公共栅极信号供给单元124连接至用于进行输出(CGL)的公共栅极连线160并通过多条公共栅极线CGL1、CGL2、…、CGLn和公共栅极连线160给多个像素提供公共栅极信号CGS。
如将在后面描述的，所有像素的公共栅极信号CGS是统一的。因而，如图10中所示，不是按顺序驱动多个分离的栅极信号，而是施加单个公共栅极信号，因而不需要用于产生栅极信号的单独栅极集成电路。因此，因为栅极驱动器130不需要用于产生额外栅极信号的单独栅极集成电路，所以能够减小栅极驱动器130的面积，从而实现窄边框。
初始化电压供给单元126连接至用于进行输出(VIL)的初始化电压连线170并通过多条初始化电压线VIL1、VIL2、VIL3、…、VILm和初始化电压连线170给多个像素提供初始化电压Vini。
图3图解了设置在图1所示的显示装置中的第X数据线与第Y栅极线之间的交叉部分处的像素的示例性等效电路图。
参照图3，显示装置100的每个像素可包括有机发光二极管OLED和配置成驱动有机发光二极管OLED的驱动电路。驱动电路包括驱动晶体管DT，驱动晶体管DT配置成通过给有机发光二极管OLED提供电流来驱动有机发光二极管OLED。
驱动晶体管DT的第一节点是栅极节点G并且第一节点被施加电压V1。驱动晶体管DT的第二节点是源极节点和漏极节点之一，例如源极节点S，第二节点被施加电压V2。驱动晶体管DT的第三节点是漏极节点和源极节点中的另一个，例如漏极节点D，第三节点被施加驱动电压VDD。在此，电压V1可以是对应于像素的数据电压Vdata。第二电压V2例如可以是初始化电压Vini。
驱动电路可包括连接在驱动晶体管DT的第一节点G与第二节点S之间的电容器，例如存储电容器Cst。电容器Cst在一帧周期期间保持恒定电压。
在每个像素中，除驱动晶体管DT和电容器Cst以外，配置成驱动有机发光二极管OLED的驱动电路可进一步包括一个或多个附加的晶体管和一个或多个附加的电容器。
参照图3，有机发光二极管OLED包括第一电极和第二电极。有机层可夹在第一电极与第二电极之间。有机发光二极管OLED的第一电极连接至驱动晶体管DT。有机发光二极管OLED的第二电极连接至基电压(base voltage)VSS。基电压VSS可在控制器140和/或电源控制器150的控制下变为低电压和高电压。
驱动晶体管DT包括被施加数据电压Vdata的第一节点G、连接至有机发光二极管OLED的第一电极的第二节点S、以及连接至驱动电压VDD的第三节点D。
显示装置100的每个像素包括：第一晶体管T1，第一晶体管T1电连接在提供数据电压Vdata的数据线DL与驱动晶体管DT的第一节点G之间；和第二晶体管T2，第二晶体管T2电连接在提供初始化电压Vini的初始化电压线VIL与驱动晶体管DT的第二节点S之间。
第一晶体管T1通过经由栅极线GL施加的栅极信号GS导通和截止或者切换。当第一晶体管T1响应于栅极信号GS导通时，第一晶体管T1将数据电压Vdata施加至驱动晶体管DT的第一节点G。
第二晶体管T2通过经由公共栅极线CGL施加的公共栅极信号CGS导通和截止或者切换。当第二晶体管T2响应于公共栅极信号CGS导通时，第二晶体管T2将初始化电压Vini提供至驱动晶体管DT的第二节点S。
电容器Cst电连接在驱动晶体管DT的第一节点G与第二节点S之间。电容器Cst在一帧周期期间保持数据信息VGS，数据信息VGS是施加至驱动晶体管DT的第一节点G的数据电压Vdata(＝VG)与施加至第二节点S的初始化电压Vini(＝Vs)之间的差。
因此，可不存在连接至第二节点S的寄生电容器的影响。因此，电容器Cst的尺寸可减小那么多，因而能够增加开口率。此外，能够减小所有像素的电容器Cst的负载，这对于高速操作是有利的。
图4图解了在图1所示的显示装置中，在一个帧周期期间公共栅极信号和栅极线上的栅极信号的信号波形。图5图解了在图1所示的显示装置中，在一个帧周期期间单个像素的驱动电路中的信号波形。
参照图4和图5，一个帧周期包括其中数据写入每个像素中并且被保持预定时间段的数据写入&保持时段Data write&hold、以及其中根据保持的数据实际发光的发光时段Emission。
数据写入&保持时段Data write&hold可划分为其中数据写入每个像素中的数据写入时段Data write、以及其中写入的数据被保持预定时间段的数据保持时段Data hold。
因为栅极信号依次地施加至栅极线GL1、GL2、…、GLn，所以各个像素的数据写入时段Data write可按照栅极线GL1、GL2、…、GLn的顺序被依次定位。结果，对于每个像素，数据写入时段Data write之后的数据写入&保持时段Data write&hold的其余部分对应于数据保持时段Data hold。因此，每个像素的数据保持时段Data hold的长度可不同。
在数据写入&保持时段Data write&hold中的给驱动晶体管DT施加数据电压Vdata的数据写入时段Data write期间，第一晶体管T1导通。
换句话说，施加至具体像素的栅极信号GS在数据写入时段Data write期间保持高状态并且在其余时段期间保持低状态。因此，当在数据写入时段Data write期间第一晶体管T1通过栅极信号GS导通时，数据电压Vdata施加至驱动晶体管DT的第一节点G。
在数据写入时段和数据保持时段Data write&hold期间第二晶体管T2导通。当在数据写入时段和数据保持时段Data write&hold期间第二晶体管T2通过公共栅极信号CGS导通时，初始化电压Vini施加至驱动晶体管DT的第二节点S。
结果，在每个像素中第一晶体管T1和第二晶体管T2不同时截止，而是第二晶体管T2在数据保持时段Data hold期间保持导通状态。因此，初始化电压Vini通过第二晶体管T2持续施加至驱动晶体管DT的第二节点S。
参照图5，连接至有机发光二极管OLED的第二电极的基电压VSS在发光时段Emission期间保持低状态并且在其他时段期间保持高状态。因为基电压VSS在发光时段Emission期间保持低状态，所以驱动晶体管DT输出与电容器Cst中保持的数据信息VGS1(＝VGS2)对应的电流，然后将电流提供至有机发光二极管OLED。
同时，一个帧周期可包括位于数据写入&保持时段Data write&hold与发光时段Emission之间的浮置时段Floating。在此，浮置时段Floating长度上可比数据写入时段Data write短，以便减小或最小化帧时间。第二晶体管T2在浮置时段Floating期间处于截止状态并且基电压VSS保持高状态。
因而，即使驱动晶体管DT的第一节点G浮置，仍通过驱动晶体管DT的第二节点S的初始化电压Vini和电容器Cst保持驱动晶体管DT的第一节点G的电压VGS1(＝VGS2)。
同时，一个帧周期可包括位于发光时段Emission与随后帧周期的数据写入&保持时段Data write&hold之间的偏移时段offset。可设置偏移时段来利用一个帧周期与随后帧周期之间的预定间隔抑制由于时间偏移导致的误差的产生。然而，一个帧周期可不包括偏移时段offset，如图6中所示。
第一晶体管T1和第二晶体管T2在偏移时段offset期间可处于截止状态并且基电压VSS可保持高状态。
图7到图9图解了在图1所示的显示装置中，在一个帧周期期间各个像素的等效电路图。
如图5和图7中所示，在显示装置的像素结构中，在数据写入时段Data write期间，数据电压Vdata(＝VG)和初始化电压Vini(＝VS)同时施加至驱动晶体管DT的第一节点G和第二节点S，从而写入数据信息VGS。
如图5和图8中所示，在数据保持时段Data hold期间，写入的数据信息VGS在发光之前存储在电容器Cst中。在此，在位于数据保持时段Data hold与发光时段Emission之间的浮置时段Floating期间，存储的数据信息VGS被保持并且驱动晶体管DT的第一节点G和第二节点S处于浮置状态。
如图5和图9中所示，随着基电压VSS在发光时段Emission期间下降至低状态，有机发光二极管OLED根据存储的数据信息VGS发光。
在每个像素中，第一晶体管T1和第二晶体管T2不同时截止，而是第二晶体管T2在数据保持时段Data hold期间保持导通状态(见图8)。因此，驱动晶体管DT的第一节点G的第一节点电压VG在驱动晶体管DT的第一节点G和第二节点S的浮置时段Floating期间不降低，而是被保持。结果，数据信息VGS不降低，而是被保持。
图10图解了根据另一示例性实施方式，在图1所示的显示装置中，在一个帧周期期间单个像素的驱动电路中的信号波形。
参照图10，在显示装置的像素结构中，在数据写入时段Data write期间，电压同时施加至驱动晶体管DT的第一节点G和第二节点S，从而写入数据信息VGS。第一晶体管T1和第二晶体管T2在数据写入时段Data write期间导通然后同时截止。
因为不同像素的第二晶体管T2单独导通和截止，例如切换，所以栅极驱动器130可需要进一步包括配置成给每个像素施加不同公共栅极信号CGS的栅极集成电路。因而，可增加栅极驱动器130的尺寸。因此，为了实现窄边框，需要减小栅极驱动器130的面积。
然后，在数据保持时段Data hold期间，写入的数据信息VGS在发光之前可存储在电容器Cst中。
在数据保持时段Data hold期间，驱动晶体管DT的第一节点G和第二节点S处于浮置状态。
随着基电压VSS在发光时段Emission期间下降，有机发光二极管OLED根据存储的数据信息VGS发光。
如图10中所示，数据保持时段Data hold可相对长于数据写入时段Data write。在这种情形中，第一晶体管T1和第二晶体管T2可同时截止。因而，在驱动晶体管DT的第一节点G和第二节点S处于浮置状态时，驱动晶体管DT的第一节点G的第一节点电压VG可由于诸如漏电流之类的各种原因而降低(VG降低，VGS1>VGS2)。
因为驱动晶体管DT的第一节点G和第二节点S在数据保持时段Data hold期间处于浮置状态，数据信息VGS需要仅由存储器Cst保持，且存储器Cst受寄生电容器影响，所以存储器Cst的尺寸不能够减小。结果，为了高速操作，可需要减小每个像素的存储器Cst的负载。
因为每个像素的数据保持时段Data hold的长度可不同，所以根据由数据保持时段Data hold的长度差异导致的显示装置内的位置，可存在有机发光二极管OLED的灰度级的差异。
参照图4到图9，根据上述示例性实施方式的显示装置可抑制根据由数据保持时段Data hold的长度差异导致的显示装置内的位置，有机发光二极管OLED的灰度级的差异。
同时，在根据上述示例性实施方式的显示装置中，在每个像素中第一晶体管T1和第二晶体管T2不同时截止，而是第二晶体管T2在数据保持时段Data hold期间保持导通状态。
在根据示例性实施方式的上述显示装置中，电容器Cst和驱动晶体管DT的第二节点S的初始化电压Vini同时用于保持数据信息VGS。因此，如上面参照图10所述的，与第一晶体管T1和第二晶体管T2同时截止的情形相比，可减小电容器Cst的尺寸。
根据示例性实施方式的上述显示装置通过减小所有像素的电容器Cst的负载，对于高速操作来说是有利的。
尽管数据保持时段Data hold的长度存在差异，但根据示例性实施方式的上述显示装置可抑制取决于显示装置内的位置的有机发光二极管OLED的灰度级的差异。就是说，首先被写入数据的驱动晶体管DT的数据信息VGS在数据保持时段Data hold期间可不减小。因此，显示装置中的所有位置的像素可保持相同的数据信息VGS。
上面参照附图描述了示例性实施方式，但本发明不限于此。例如，描述了当高电压或高信号施加至驱动晶体管DT、第一晶体管T1和第二晶体管T2的栅极时，驱动晶体管DT、第一晶体管T1和第二晶体管T2导通，并且当低电压或低信号施加于此时，驱动晶体管DT、第一晶体管T1和第二晶体管T2截止。然而，当低电压或低信号施加至驱动晶体管DT、第一晶体管T1和第二晶体管T2的栅极时，驱动晶体管DT、第一晶体管T1和第二晶体管T2可导通，并且当高电压或高信号施加于此时，驱动晶体管DT、第一晶体管T1和第二晶体管T2可截止。
根据上述示例性实施方式，可提供一种能够增加开口率并且能够执行高速操作的显示元件和显示装置。
此外，根据本发明的示例性实施方式，可提供一种能够减小驱动器的面积，从而实现窄边框的显示元件和显示装置。
在不背离本发明的技术思想或范围的情况下，能够在本发明中进行各种修改和变化，这对于所属领域技术人员来说是显而易见的。因而，本发明的实施方式旨在覆盖落入所附权利要求书范围及其等同范围内的对本发明的修改和变化。

Claims (18)

1.一种显示元件，包括：
包括第一电极和第二电极的有机发光二极管；
驱动晶体管，所述驱动晶体管包括被提供数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；
第一晶体管，所述第一晶体管电连接在用于提供所述数据电压的数据线与所述驱动晶体管的第一节点之间；
第二晶体管，所述第二晶体管电连接在用于提供初始化电压的初始化电压线与所述驱动晶体管的第二节点之间；和
电容器，所述电容器电连接在所述驱动晶体管的第一节点与第二节点之间，
其中：
一个帧周期包括数据写入和保持时段、发光时段以及位于所述数据写入和保持时段与所述发光时段之间的浮置时段，并且
在所述浮置时段期间，所述第二晶体管处于截止状态并且连接至所述有机发光二极管的第二电极的基电压保持高状态。
2.根据权利要求1所述的显示元件，其中：
所述数据写入和保持时段包括数据写入时段和数据保持时段，
所述第一晶体管在所述数据写入和保持时段中的数据写入时段期间导通，在所述数据写入时段中向相应驱动晶体管提供所述数据电压，并且
所述第二晶体管在所述数据写入时段和所述数据保持时段期间导通。
3.根据权利要求2所述的显示元件，其中：
所述基电压在所述发光时段期间保持低状态并且在所述一个帧周期的其他时段期间保持高状态。
4.根据权利要求2所述的显示元件，其中：
所述浮置时段短于所述数据写入时段。
5.根据权利要求3所述的显示元件，其中：
所述一个帧周期还包括位于所述发光时段与随后帧周期的数据写入和保持时段之间的偏移时段，并且
在所述偏移时段期间，所述第一晶体管和所述第二晶体管处于截止状态并且所述基电压保持高状态。
6.根据权利要求1所述的显示元件，其中：
所述第一晶体管和所述第二晶体管不同时截止。
7.根据权利要求1所述的显示元件，其中：
所述初始化电压线通过初始化电压连线连接至数据驱动器中包括的初始化电压供给单元。
8.一种显示装置，包括：
位于多条数据线和多条栅极线的交叉部分处的多个像素；
向所述多个像素提供公共栅极信号的多条公共栅极线；
共同地连接至所述多条公共栅极线的公共栅极连线；
向所述多个像素提供初始化电压的多条初始化电压线；和
共同地连接至所述多条初始化电压线的初始化电压连线，
其中所述多个像素的每一个包括：
包括第一电极和第二电极的有机发光二极管；
驱动晶体管，所述驱动晶体管包括被提供来自所述多条数据线中的一条数据线的数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；
第一晶体管，所述第一晶体管电连接在所述一条数据线与所述驱动晶体管的第一节点之间，并且通过经由所述多条栅极线中的一条栅极线提供的栅极信号切换；
第二晶体管，所述第二晶体管电连接在所述多条初始化电压线中的一条初始化电压线与所述驱动晶体管的第二节点之间，并且通过经由所述多条公共栅极线中的一条公共栅极线提供的公共栅极信号切换；和
电容器，所述电容器电连接在所述驱动晶体管的第一节点与第二节点之间，并且
其中：
一个帧周期包括数据写入和保持时段、发光时段以及位于所述数据写入和保持时段与所述发光时段之间的浮置时段，并且
在所述浮置时段期间，所述第二晶体管处于截止状态并且连接至所述有机发光二极管的第二电极的基电压保持高状态。
9.根据权利要求8所述的显示装置，还包括：
数据驱动器，所述数据驱动器通过所述数据线向所述像素提供所述数据电压，并且通过所述公共栅极连线向所述像素提供所述公共栅极信号；和
栅极驱动器，所述栅极驱动器通过所述栅极线向所述像素提供所述栅极信号。
10.根据权利要求9所述的显示装置，其中：
所述数据驱动器通过所述初始化电压连线提供所述初始化电压。
11.根据权利要求10所述的显示装置，其中：
所述数据写入和保持时段包括数据写入时段和数据保持时段，
所述第一晶体管在所述数据写入和保持时段中的数据写入时段期间导通，在所述数据写入时段中向相应驱动晶体管提供所述数据电压，并且
所述第二晶体管在所述数据写入时段和所述数据保持时段期间导通。
12.根据权利要求11所述的显示装置，其中：
所述基电压在所述发光时段期间保持低状态并且在所述一个帧周期的其他时段期间保持高状态。
13.根据权利要求11所述的显示装置，其中：
所述浮置时段短于所述数据写入时段。
14.根据权利要求8所述的显示装置，其中：
所述一个帧周期还包括位于所述发光时段与随后帧周期的数据写入和保持时段之间的偏移时段，并且
在所述偏移时段期间，所述第一晶体管和所述第二晶体管处于截止状态并且所述基电压保持高状态。
15.根据权利要求8所述的显示装置，其中：
在每个像素，所述第一晶体管和所述第二晶体管不同时截止。
16.根据权利要求9所述的显示装置，其中：
所述初始化电压连线连接至所述数据驱动器中包括的初始化电压供给单元。
17.一种数据驱动器，包括：
数据单元，所述数据单元连接至数据线并且配置成通过所述数据线向像素提供数据电压；
公共栅极信号供给单元，所述公共栅极信号供给单元连接至公共栅极连线并且配置成通过所述公共栅极连线向所述像素提供公共栅极信号；和
初始化电压供给单元，所述初始化电压供给单元连接至初始化电压连线并且配置成通过所述初始化电压连线向所述像素提供初始化电压，
其中所述像素的每一个包括：
包括第一电极和第二电极的有机发光二极管；
驱动晶体管，所述驱动晶体管包括被提供来自所述数据线中的一条数据线的数据电压的第一节点、连接至所述有机发光二极管的第一电极的第二节点、以及电连接至驱动电压线的第三节点；
第一晶体管，所述第一晶体管电连接在所述一条数据线与所述驱动晶体管的第一节点之间，并且通过经由栅极线中的一条栅极线提供的栅极信号切换；
第二晶体管，所述第二晶体管电连接在所述初始化电压线中的一条初始化电压线与所述驱动晶体管的第二节点之间，并且通过经由所述公共栅极线中的一条公共栅极线提供的公共栅极信号切换；和
电容器，所述电容器电连接在所述驱动晶体管的第一节点与所述驱动晶体管的第二节点之间，并且
其中：
一个帧周期包括数据写入和保持时段、发光时段以及位于所述数据写入和保持时段与所述发光时段之间的浮置时段，并且
在所述浮置时段期间，所述第二晶体管处于截止状态并且连接至所述有机发光二极管的第二电极的基电压保持高状态。
18.根据权利要求17所述的数据驱动器，其中：
所述公共栅极信号供给单元在所述数据写入和保持时段期间提供所述公共栅极信号。
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