CN108206207A - Thyristor with semiconductor body - Google Patents
Thyristor with semiconductor body Download PDFInfo
- Publication number
- CN108206207A CN108206207A CN201711351368.2A CN201711351368A CN108206207A CN 108206207 A CN108206207 A CN 108206207A CN 201711351368 A CN201711351368 A CN 201711351368A CN 108206207 A CN108206207 A CN 108206207A
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- semiconductor
- semiconductor body
- region
- semiconductor region
- thyristor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 361
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 239000004642 Polyimide Substances 0.000 claims description 13
- 229920001721 polyimide Polymers 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 11
- 238000001465 metallisation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The present invention relates to a kind of thyristors with semiconductor body, thyristor has the first semiconductor body main side, the second semiconductor body main side and around the semiconductor body edge of semiconductor body and the first and second semiconductor body main sides of connection, and semiconductor body has：First semiconductor region, first semiconductor region extends up to the second semiconductor body main side in semiconductor body fringe region, second outer surface of the first semiconductor region forms semiconductor body edge, and the third outer surface of the adjacent semiconductor body edges of the first semiconductor region forms the first surface region of the second semiconductor body main side；It is arranged on the first semiconductor region and does not extend to second semiconductor region at semiconductor body edge；The third semiconductor region being arranged on the second semiconductor region and the 4th semiconductor region being arranged in third semiconductor region；Occur from the first surface of the second semiconductor body main side and be parallel to semiconductor body peripheral extension and reach the recess portion of the second semiconductor region.
Description
Technical field
The present invention relates to a kind of thyristors with semiconductor body.
Background technology
Particularly in the case of thyristor, to prevent electrical breakdown, it is often necessary to reduce the semiconductor body in thyristor
Fringe region generate electric field strength.
DE3832709A1 discloses the thyristor with semiconductor body, which has the first semiconductor body master
Side, with the second semiconductor body main side of the first semiconductor body main side opposed and around semiconductor body and company
The semiconductor body edge of the first semiconductor body main side and the second semiconductor body main side is connect, wherein the semiconductor body has
There is the first semiconductor region that p is adulterated, wherein the outer surface of the first semiconductor region forms the first semiconductor body main side, wherein first
Semiconductor region extends up to the second semiconductor body main side in semiconductor body marginal zone.Here, semiconductor body is disposed with p
The field ring of doping, to reduce the electric field strength generated at the fringe region of the semiconductor body of thyristor.However, due to field ring
It must in the semiconductor body be made by appropriate doping process, so the making of field ring needs to manufacture exerting in thyristor
Power.
Invention content
The object of the present invention is to provide a kind of thyristors with semiconductor body, do not need to any ring to reduce
The electric field strength generated at the fringe region of the semiconductor body of thyristor.
The purpose realizes that the thyristor has the first semiconductor sheet by a kind of thyristor with semiconductor body
Body main side, with the second semiconductor body main side of the first semiconductor body main side opposed and around semiconductor body simultaneously
And the semiconductor body edge of the first semiconductor body main side of connection and the second semiconductor body main side, wherein the semiconductor sheet
Body has the first semiconductor region of the first conduction type, wherein the first outer surface of the first semiconductor region forms the first semiconductor sheet
Body main side, wherein the first semiconductor region extends up to the second semiconductor body main side in semiconductor body marginal zone, the first half
Second outer surface of conductor region forms semiconductor body edge, and the of the adjacent semiconductor body edges of the first semiconductor region
Three outer surfaces form the first surface area of the second semiconductor body main side, and wherein semiconductor body has in semiconductor body
The second of second conduction type at semiconductor body edge is arranged on the first semiconductor region and not extended up in portion region
Semiconductor region, wherein semiconductor body have be arranged in the third semiconductor region of the first conduction type on the second semiconductor region with
And the 4th semiconductor region of the second conduction type in third semiconductor region is arranged in, wherein semiconductor body has recess portion, institute
Recess portion is stated from the first surface of the second semiconductor body main side to occur and be parallel to semiconductor body peripheral extension and reach the
In two semiconductor regions.
The favourable improvement of the present invention is displayed from dependent claims.
If it is that planar design is advantageous to demonstrate entire first semiconductor body main side.Therefore, semiconductor body is not
With occurring from the first semiconductor body main side and enter the other recess portion in semiconductor body.Therefore, thyristor can lead to
The means for being for example sintered connection are crossed, are easily connected with substrate (such as DCB substrates), because of the generation applied to thyristor
Pressure needed for sintering connection will not lead to the destruction towards the edge of semiconductor body.
In addition, if recess portion stretching, extension is demonstrated until semiconductor body edge is advantageous, because in semiconductor body
Therefore the electric field strength that fringe region generates significantly reduces.
In addition, it demonstrates advantageously, if semiconductor body has first step and second in the region of recess portion
Rank, first step have the first bottom surface of spill stretching, extension, and second step has the second bottom surface of spill stretching, extension, wherein first
Step be arranged in the vertical direction of the normal direction of the first outer surface of the first semiconductor region than second step closer to
The center of semiconductor body, wherein the first bottom surface is not to be formed by the outer surface of the second semiconductor region and the second bottom surface is
It is formed by the outer surface of first, second, and third semiconductor region.In the design of this semiconductor body, in semiconductor body
The electric field strength generated at fringe region particularly marked degree reduces.
In this regard, it was demonstrated that if the stretching, extension of the second bottom surface is until the one of semiconductor body edge and second bottom surface
The third outer surface that part forms the first semiconductor region is advantageous, because of the electricity generated at the fringe region of semiconductor body
Therefore field intensity particularly marked degree reduces.
In this regard, it was demonstrated that if the third outer surface of the first semiconductor region is that planar design is advantageous, because
Therefore three outer surfaces are particularly simple designs.
In addition, it demonstrates advantageously, if semiconductor body has first step, the First in the region of recess portion
Rank have spill stretching, extension the first bottom surface, first bottom surface is not formed by the outer surface of the second semiconductor region and have to
Groove up in the second semiconductor region.In the design of this semiconductor body, generated at the fringe region of semiconductor body
Electric field strength particularly marked degree reduce.
In this regard, it was demonstrated that if the first part surface of the third outer surface of the first semiconductor region forms the ditch of groove
A part for slot mating surface is advantageous, because the electric field strength generated at the fringe region of semiconductor body is therefore special
It significantly decreases.
In this regard, it was demonstrated that if the second part surface of the third outer surface of the first semiconductor region has planar design
It is advantageous, wherein the second part surface extends up to semiconductor body edge, because in the marginal zone of semiconductor body
Therefore the electric field strength generated at domain particularly marked degree reduces.
It further demonstrates advantageously, if the third outer surface of the first semiconductor region has recessed profile, wherein
In semiconductor body marginal zone, semiconductor body has the be arranged on the second semiconductor region the 5th half of the first conduction type the to lead
Body area, the geometry of center dant are designed so that the 5th semiconductor region is arranged to and the first semiconductor region and third half
Conductor region is physically isolated.In the design of this semiconductor body, the electricity of generation at the fringe region of semiconductor body
Field intensity particularly marked degree reduces.
If it further demonstrates recess portion to be advantageous from the outer surface of third semiconductor region or the 4th semiconductor region.
The recess portion can be from the preferred flat outer surface of third semiconductor region and from the 4th semiconductor region preferred flat outer surface occur.
If be advantageous in addition, demonstrating boundary and reaching recess portion from the second semiconductor region to third semiconductor region, because
Therefore the electric field strength generated at the fringe region of semiconductor body particularly marked degree reduces.
It is advantageous if further demonstrating boundary and reaching recess portion from the first semiconductor region to the second semiconductor region, because
Therefore the electric field strength generated at the fringe region of semiconductor body particularly marked degree reduces.
In addition, if semiconductor body sides aligned parallel is demonstrated in the normal direction of the first outer surface of the first semiconductor region
The second semiconductor body main side is stretched over from the first semiconductor body main side to be advantageous, because therefore semiconductor body edge is
Particularly simple design.
In addition, it demonstrates advantageously, if semiconductor body has the outer surface for limiting recess portion, wherein defining described recessed
At least part of the outer surface of the semiconductor body in portion be respectively formed as the silicon oxide layer of respective semiconductor regions outer surface or
Person's silicon oxide layer is arranged at least part of the outer surface for the semiconductor body for defining the recess portion.
In this regard, it was demonstrated that if arranging that polyimide layer is advantageous on silicon oxide layer.
In addition, it demonstrates advantageously, if semiconductor body has the outer surface for defining recess portion, wherein polyimide layer
It is disposed at least part of the outer surface for the semiconductor body for defining recess portion.
Optionally, the polyimide layer being applied in combination with silicon oxide layer is replaced such as glassivation conventional in thyristor field
Can prevent or at least significantly temporary delay from the first semiconductor region along semiconductor body peripheral extension to third semiconductor
The formation of the conductive inversion channel in area.
In this regard usually it should be noted that the semiconductor region of the first conduction type be preferably designed for p doping partly lead
Body area (p- conduction types), and the semiconductor region of the second conduction type is preferably designed for n doped semiconductor areas (n- conductive-types
Type).Alternatively, the semiconductor region of the first conduction type can be designed as n doped semiconductor areas (n- conduction types), and second leads
The semiconductor region of electric type can be designed as p doped semiconductor areas (p- conduction types).
Description of the drawings
Illustrate exemplary embodiment of the present invention with reference to the accompanying drawings, wherein：
Fig. 1 shows the sectional view of a design of thyristor according to the present invention,
Fig. 2 shows the plan view from above of thyristor shown in Fig. 1,
Fig. 3 show another design of thyristor according to the present invention sectional view and
Fig. 4 shows the sectional view of another design of thyristor according to the present invention.
It should be pointed out that these figures are schematic diagrames.In the accompanying drawings, identical element has identical reference numeral.
Specific embodiment
Fig. 1 shows a kind of sectional view of design of thyristor 1 according to the present invention, and Fig. 2 shows thyristors 1
Wherein compared to Figure 1, thyristor 1 is exemplified in fig. 2 with drawdown ratio, and the poly- of thyristor 1 is not shown in plan view from above
Imide layer 23.
Thyristor 1 according to the present invention has semiconductor body 2, and semiconductor body 2 has the first semiconductor body main side
3rd, with the second semiconductor body main side 4 of 3 opposed of the first semiconductor body main side and around semiconductor body 2 and even
Connect the semiconductor body edge 28 of the first and second semiconductor body main sides 3 and 4.The semi-conducting material of semiconductor body 2 is preferred
It is made of silicon or silicon carbide.
Semiconductor body 2 has the first semiconductor region 5 of the first conduction type, wherein outside the first of the first semiconductor region 5
Surface 10 forms the first semiconductor body main side 3.Entire first semiconductor body main side 3 is preferably planar design.In semiconductor
In the semiconductor body fringe region 25 of ontology 2, the first semiconductor region 5 extends up to the second semiconductor body main side 4.The first half
Second outer surface of conductor region 5 forms semiconductor body edge 28, and the adjacent semiconductor body edges of the first semiconductor region 5
28 third outer surface 40 forms the first surface region of the second semiconductor body main side 4.
Semiconductor body 2 has the second semiconductor region 6 of the second conduction type, in the interior zone of semiconductor body 2
It is arranged in IB on the first semiconductor region 5, and does not extend up to semiconductor body edge 28.Semiconductor body 2 has arrangement
The third semiconductor region 7 of the first conduction type on the second semiconductor region 6 and what is be arranged in third semiconductor region 7 second lead
4th semiconductor region 8 of electric type.The formation of 4th semiconductor region 8 is arranged in the groove in third semiconductor region 7.
In addition, semiconductor body 2 has recess portion 15, what it is from the second semiconductor body main side 4 is preferably the first of plane
Surface 16 occurs, and is parallel to semiconductor body edge 28 --- and it is preferably parallel to entire semiconductor body edge 28 and stretches, and
And it reaches in the second semiconductor region 6.The first surface 16 of second semiconductor body main side 4 is arranged in the second semiconductor body main side
In 4 interior zone 51.Recess portion 15 is stretched preferably in a manner of closure around the interior zone 51 of the second semiconductor body main side 4
Exhibition.
In the present invention, recess portion 15 is reduced during thyristor is run in the marginal zone of the semiconductor body 2 of thyristor
The electric field strength generated at domain.
For the purpose of electrical connection, thyristor 1 has the first metal being arranged on the outer surface 10 of the first semiconductor region 5
Change portion 12, the second metallization 14 being arranged on the 4th semiconductor region 8 and the third metal being arranged on third semiconductor region 7
Change portion 24.First metallization 12 preferably forms anode metallization portion, and the second metallization 14 preferably forms cathodic metal
Change portion, and third metallization 24 preferably forms gate metalized portion.It should be noted that third metallization 24 differs
Calmly semiconductor body edge 28 is must be close to as shown in figure to arrange, but can also be for example with the correspondence of the 4th semiconductor region 8
Design arrangement is in the region of the center M of semiconductor body 2.
The preferred stretching, extension of recess portion 15 is until semiconductor body edge 28.Recess portion 15 is preferably from the preferred of third semiconductor region 7
What it is for the outer surface 31 of plane or from the 4th semiconductor region 8 is preferably that the outer surface 32 of plane occurs.Therefore, the second semiconductor sheet
The first surface 16 of body main side 4 is preferably preferably being led for the form of the outer surface 31 of plane or the 4th half for third semiconductor region 7
The form preferably for the outer surface 32 of plane in body area 8.
Boundary G1 from the second semiconductor region 6 to third semiconductor region 7 preferably reaches recess portion 15.From the first semiconductor region
The boundary G2 of 5 to the second semiconductor region 6 preferably reaches recess portion 15.
Semiconductor body edge 28 is preferably parallel to the normal direction N of the first outer surface 10 of the first semiconductor region 5, from
First semiconductor body main side 3 extends to the second semiconductor body main side 4.However, semiconductor body edge 28 can also tilt
Ground extends to the second semiconductor body main side 4 from the first semiconductor body main side 3.
On the normal direction N of the first outer surface 10 of the first semiconductor region 5, the first semiconductor region 5 can have for example
10 μm to 120 μm --- particularly 10 μm to 60 μm --- of thickness.Normal in the first outer surface 10 of the first semiconductor region 5
The thickness that on the N of direction, third semiconductor region 7 can have for example from 10 μm to 120 μm --- particularly from 80 μm to 120 μm ---
Degree.In the situation of exemplary embodiment, the first semiconductor region 5 and third semiconductor region 7 are p doping, and wherein p doping can be with
Such as by being formed in the semi-conducting material (such as silicon or silicon carbide) by boron, aluminium and/or Gallium diffusion to semiconductor body 2.
Firstth, third and the 5th semiconductor region 5,7 and 9 (referring to Fig. 4) can be respectively provided with such as 1 × 1015cm-3To 1 × 1020cm-3's
Doping concentration, wherein first, third and the 5th semiconductor region 5,7 and 9 can have different doping concentrations.In the first semiconductor
On the normal direction N of first outer surface 10 in area 5, in the interior zone IB of semiconductor body 2, the second semiconductor region 6 can be with
The thickness of --- particularly 230 μm to 250 --- μm with such as 240 μm to 300 μm, the second semiconductor region 6 can have 1 ×
1013cm-3To 1 × 1014cm-3Doping concentration.On the normal direction N of the first outer surface 10 of the first semiconductor region 5, the 4th
Semiconductor region 8 can have 5 μm to 40 μm --- particularly 10 μm to 20 μm --- of thickness.4th semiconductor region 8 can have
Such as 1 × 1019cm-3To 1 × 1021cm-3Doping concentration.Since the doping concentration of the 4th semiconductor region 8 is preferably higher than the second half
The doping concentration of conductor region 6, thus second and the 4th semiconductor region 6 and 8 have n doping attached drawing and exemplary embodiment
In, the doping of the 4th semiconductor region 8 is represented as n+, and the doping of the second semiconductor region 6 is represented as n-.For example, n is adulterated
Semiconductor region can be by being formed in the semi-conducting material (such as silicon or silicon carbide) by phosphorus diffusion to semiconductor body 2.
Recess portion 15 is preferably more than third semiconductor relative to the second semiconductor body main side 4 for the thickness T of the first surface 16 of plane
The thickness in area 7 and can be, for example, 121 μm to 150 μm --- particularly such as 135 μm.It is it should be noted that specified above
Numerical value and numberical range be for example depend strongly on thyristor 1 the exemplary value for it is expected backward voltage and desired characteristic and
Numberical range, therefore it is also possible to deviate significantly from numerical value defined above and numberical range.Thyristor 1 can have for example
The backward voltage of 1600V.
In the case of the exemplary embodiment according to Fig. 1 and Fig. 2, semiconductor body 2 has in the region of recess portion 15 26
There are first step 20 and second step 20 ', first step 20 has the first bottom surface of spill stretching, extension, and second step 20 ' has
Second bottom surface of spill stretching, extension.First step 20 is arranged in the normal direction N's of the first outer surface 10 of the first semiconductor region 5
Than second step 20 ' closer at the center M of semiconductor body 2 in vertical direction, wherein the first bottom surface is not led by the second half
The outer surface in body area 6 is formed, and the second bottom surface is formed by the outer surface of first, second, and third semiconductor region 5,6 and 7.
Second step 20 ' is preferably arranged as adjacent with first step 20.The preferred stretching, extension of second bottom surface is until semiconductor body edge
28, and a part for the second bottom surface forms the third outer surface 40 of the first semiconductor region 5.The third of first semiconductor region 5
Outer surface 40 is preferably planar design.
Fig. 3 shows the sectional view of another design of thyristor 1 according to the present invention, in addition to difference described below,
Possible expedients, modification, size and doping concentration including the design for corresponding to the thyristor 1 according to Fig. 1 and 2.In root
In the case of exemplary embodiment according to Fig. 3, as in the exemplary embodiment according to Fig. 1 and Fig. 2, semiconductor body 2
There is first step 20 in the region of recess portion 15 26, it not is by the outer surface of the second semiconductor region 6 which, which has,
The first bottom surface formed, spill stretching, extension, wherein, with the exemplary embodiment according to Fig. 1 and Fig. 2 on the contrary, semiconductor body 2
In the region of recess portion 15 26, it is preferably the groove 41 of U-shaped to have in the second semiconductor region 6 of arrival.First semiconductor region 5
The first part surface 40 ' of third outer surface 40 preferably forms the part on the groove contact surface of groove 41 herein.First
The second part surface 40 " of the third outer surface 40 of semiconductor region 5 is preferably planar design, and the second part surface extension is straight
To semiconductor body edge 28.
Fig. 4 shows the sectional view of another design of thyristor 1 according to the present invention, in addition to difference described below,
Possible advantageous design, modification, size and doping concentration including the design for corresponding to the thyristor 1 according to Fig. 1 and 2.
In the case of the exemplary embodiment of Fig. 4, the third outer surface 40 of the first semiconductor region 5 has recessed profile, wherein with
According to the exemplary embodiment of Fig. 1 and Fig. 2 on the contrary, semiconductor body 2 in semiconductor body fringe region 25 have be arranged in
5th semiconductor region 9 of the first conduction type on the second semiconductor region 6, the geometry of center dant are designed so that
Five semiconductor regions 9 are arranged to and first and 5 and 7 physical separation of third semiconductor region.
In all exemplary embodiments, the semi-conducting material of semiconductor body 2 is preferably made of silicon or silicon carbide,
At least part of the outer surface 33,34,35 and 40 for defining recess portion 15 of middle semiconductor body 2 can be respectively designed to accordingly
The outer surface of the silicon oxide layer 22 of semiconductor region 5,6,7 and 9.The outer surface 33,34,35 for defining recess portion 15 of semiconductor body 2
With 40 whole surface can be respectively designed to corresponding semiconductor region 5,6,7 and 9 silicon oxide layer 22 outer surface.
In the exemplary embodiment, if the semi-conducting material of semiconductor body 2 is made of silicon or silicon carbide, accordingly
Silicon oxide layer 22 is generated by aoxidizing the corresponding exterior surface area of semiconductor body 2, as a result in the exemplary embodiment, phase
The silicon oxide layer 22 answered is the component part of semiconductor body 2 and corresponding semiconductor region, wherein in order to make silicon oxide layer
Purpose, corresponding semiconductor region outer surface is aoxidized.In addition it should be noted that under the context of the present invention, pass through
The layer that chemical reaction (such as oxidation) generates in the surface region of the semiconductor region of semiconductor body 2 --- it is particularly non-conductive
Floor --- it is the component part in related semiconductor area.The silica of each silicon oxide layer can be such as silicon monoxide or titanium dioxide
The form of the form or silicon monoxide of silicon and the mixture of silica.If the semi-conducting material of semiconductor body 2 by
Silicon carbide forms, then corresponding silicon oxide layer can also include carbon.
Corresponding silicon oxide layer can also be by painting method (such as plasma coating) by using appropriate silica
Layer coats corresponding semiconductor region to make.In this case, what silicon oxide layer was disposed in semiconductor body 2 defines recess portion
In at least part of 15 outer surface 33,34,35,40.Polyimide layer can be arranged on silicon oxide layer.
Polyimide layer 23 is preferably at least arranged in the outer surface 33,34,35 for defining the first recess portion 15 of semiconductor body 2
In 40 part.Polyimide layer 23 is preferably arranged in the outer surface 33,34 for defining recess portion 15 of semiconductor body 2,
In 35 and 40 whole surface.In all exemplary embodiments, the outer surface 33,34 for defining recess portion 15 of semiconductor body 2,
35 and 40 outer surfaces that can not also be designed to the silicon oxide layer 22 of each semiconductor region 5,6,7 or 9 (show not in the drawings
Go out).In all exemplary embodiments, in the region of recess portion 15 26, polyimide layer 23 can not also be disposed in non-lead
In electric layer, particularly it is not arranged on silicon oxide layer.
The outer surface 33,34,35 and 40 for defining recess portion 15 is respectively formed the outer surface of respective semiconductor regions.
If arranging polyimide layer on silicon oxide layer, Mechanical Contact is presented with silicon oxide layer in polyimide layer.
Polyimide layer and silicon oxide layer that may be present serve as passivation layer.Can be formed due to the presence of charge along
The conductive inversion channel that semiconductor body edge 28 stretches, the inversion channel lead to first and the third half of semiconductor body 2
Being conductively connected between conductor region 5 and 7.Using polyimide layer as described above, optionally combine with silicon oxide layer rather than
Such as glassivation conventional in thyristor field, can prevent or at least significantly temporary delay from the first semiconductor region 5 along
Semiconductor body edge 28 is stretched over the formation of the conductive inversion channel of third semiconductor region 7, and therefore increases the longevity of thyristor
Life.
It should be noted that in the present invention, the feature of different exemplary embodiments of the invention is not (assuming that feature is phase
Mutually repel) it is of course possible to being combined with each other in any desired way.
Claims (17)
1. one kind has the thyristor of semiconductor body (2), the semiconductor body (2) has the first semiconductor body main side
(3), with the second semiconductor body main side (4) of the first semiconductor body main side (3) opposed and around described half
Conductor main body (2) and connect partly leading for the first semiconductor body main side (3) and the second semiconductor body main side (4)
Body body edges (28), wherein the semiconductor body (2) has the first semiconductor region (5) of the first conduction type, wherein institute
The first outer surface (10) for stating the first semiconductor region (5) forms the first semiconductor body main side (3), wherein described the first half
Conductor region (5) extends up to the second semiconductor body main side (4) in semiconductor body fringe region (25), and described first
Second outer surface of semiconductor region (5) forms the semiconductor body edge (28), and the neighbour of first semiconductor region (5)
The third outer surface (40) for connecing the semiconductor body edge (28) forms the first table of the second semiconductor body main side (4)
Face region, wherein the semiconductor body (2) is described with being arranged in the interior zone (IB) of the semiconductor body (2)
Do not extend up on first semiconductor region (5) and the second conduction type of the semiconductor body edge (28) the second half lead
Body area (6), wherein the semiconductor body (2) is with the first conduction type being arranged on second semiconductor region (6)
4th semiconductor region (8) of third semiconductor region (7) and the second conduction type being arranged on the third semiconductor region (7),
Wherein described semiconductor body (2) has a recess portion (15), and the recess portion (15) is from the of the second semiconductor body main side (4)
One surface (16) occurs, and is parallel to the semiconductor body edge (28) and stretches and reach in second semiconductor region (6).
2. thyristor according to claim 1, which is characterized in that the entire first semiconductor body main side (3) is flat
Face design.
3. thyristor according to claim 1, which is characterized in that recess portion (15) stretching, extension is until the semiconductor body
Edge (28).
4. according to the thyristor described in any one of claim 1-3, which is characterized in that the semiconductor body (2) is in institute
Stating has first step (20) and second step (20 ') in the region (26) of recess portion (15), the first step is stretched with spill
First bottom surface of exhibition, the second step (20 ') has the second bottom surface of spill stretching, extension, wherein the first step (20)
It is arranged in the vertical direction of the normal direction (N) of first outer surface (10) of first semiconductor region (5) and compares
The second step (20 ') closer to the semiconductor body (2) center (M), wherein first bottom surface is not by institute
The outer surface formation of the second semiconductor region (6) is stated, and second bottom surface is by first semiconductor region (5), institute
State the outer surface formation of the second semiconductor region (6) and the third semiconductor region (7).
5. thyristor according to claim 4, which is characterized in that the second bottom surface stretching, extension is until the semiconductor sheet
Body edge (28), and a part for second bottom surface forms the third outer surface of first semiconductor region (5)
(40)。
6. thyristor according to claim 5, which is characterized in that the third appearance of first semiconductor region (5)
Face (40) is planar design.
7. thyristor according to any one of claims 1 to 3, which is characterized in that the semiconductor body (2) is in institute
Stating has first step (20) in the region (26) of recess portion (15), the first step (20) has the first bottom table of spill stretching, extension
Face, first bottom surface be not formed by the outer surface of second semiconductor region (6) and with reach described second
Groove (41) in semiconductor region (6).
8. thyristor according to claim 7, which is characterized in that the third appearance of first semiconductor region (5)
First part surface (40 ') in face (40) forms the part on the groove contact surface of the groove (41).
9. thyristor according to claim 8, which is characterized in that the third appearance of first semiconductor region (5)
The second part surface (40 ") in face (40) is planar design, and the second part surface extends up to the semiconductor body
Edge (28).
10. thyristor according to claim 7, which is characterized in that the third appearance of first semiconductor region (5)
Face (40) has recessed profile, wherein in the semiconductor body fringe region (25), the semiconductor body (2) has cloth
The 5th semiconductor region (9) of the first conduction type on second semiconductor region (6) is put, wherein the geometric form of the recess portion
Shape is designed so that the 5th semiconductor region (9) is arranged to partly lead with first semiconductor region (5) and the third
Body area (7) is physically separated.
11. according to the thyristor described in any one of claim 1-3, which is characterized in that the recess portion (15) is from described
The outer surface (31,32) of three semiconductor regions (7) or the 4th semiconductor region (8) occurs.
12. according to the thyristor described in any one of claim 1-3, which is characterized in that boundary (G1) is from described the second half
Conductor region (6) to the third semiconductor region (7) is reached until the recess portion (15).
13. according to the thyristor described in any one of claim 1-3, which is characterized in that boundary (G2) is from described the first half
Conductor region (5) is reached to second semiconductor region (6) until the recess portion (15).
14. according to the thyristor described in any one of claim 1-3, which is characterized in that the semiconductor body edge
(28) normal direction (N) of first outer surface (10) of first semiconductor region (5) is parallel to lead from described the first half
Body ontology main side (3) to the second semiconductor body main side (4) is stretched.
15. according to the thyristor described in any one of claim 1-3, which is characterized in that the semiconductor body (2) has
The outer surface (33,34,35,40) of the recess portion (15) is defined, wherein the semiconductor body (2) defines the recess portion (15)
At least part of the outer surface (33,34,35,40) be respectively formed as the silicon oxide layers of each semiconductor region (5,6,7,9)
(22) what outer surface or silicon oxide layer was disposed in the semiconductor body (2) defines the described outer of the recess portion (15)
In at least part on surface (33,34,35,40).
16. thyristor according to claim 15, which is characterized in that be disposed with polyimide layer on the silicon oxide layer
(23)。
17. according to the thyristor described in any one of claim 1-3, which is characterized in that the semiconductor body (2) has
The outer surface (33,34,35,40) of the recess portion (15) is defined, wherein polyimide layer (23) is disposed in the semiconductor sheet
In at least part of the outer surface (33,34,35,40) for defining the recess portion (15) of body (2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102016124669.7A DE102016124669B3 (en) | 2016-12-16 | 2016-12-16 | Thyristors with a respective semiconductor body |
| DE102016124669.7 | 2016-12-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108206207A true CN108206207A (en) | 2018-06-26 |
| CN108206207B CN108206207B (en) | 2022-04-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711351368.2A Active CN108206207B (en) | 2016-12-16 | 2017-12-15 | Thyristor with semiconductor body |
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| Country | Link |
|---|---|
| CN (1) | CN108206207B (en) |
| DE (1) | DE102016124669B3 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102019105727B4 (en) * | 2019-03-07 | 2020-10-15 | Semikron Elektronik Gmbh & Co. Kg | Thyristor or diode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3628106A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
| US4047196A (en) * | 1976-08-24 | 1977-09-06 | Rca Corporation | High voltage semiconductor device having a novel edge contour |
| CN104934464A (en) * | 2014-09-03 | 2015-09-23 | 安徽省祁门县黄山电器有限责任公司 | Junction termination structure of thyristor chip |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1110993A (en) | 1967-01-09 | 1968-04-24 | Standard Telephones Cables Ltd | Semiconductors |
| US3644801A (en) | 1971-01-21 | 1972-02-22 | Gary S Sheldon | Semiconductor passivating process and product |
| JPS4974486A (en) | 1972-11-17 | 1974-07-18 | ||
| GB1499845A (en) | 1975-03-26 | 1978-02-01 | Mullard Ltd | Thyristors |
| JPS55133569A (en) | 1979-04-06 | 1980-10-17 | Hitachi Ltd | Semiconductor device |
| DE3832709A1 (en) | 1988-09-27 | 1990-03-29 | Asea Brown Boveri | THYRISTOR |
-
2016
- 2016-12-16 DE DE102016124669.7A patent/DE102016124669B3/en active Active
-
2017
- 2017-12-15 CN CN201711351368.2A patent/CN108206207B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3628106A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
| US4047196A (en) * | 1976-08-24 | 1977-09-06 | Rca Corporation | High voltage semiconductor device having a novel edge contour |
| CN104934464A (en) * | 2014-09-03 | 2015-09-23 | 安徽省祁门县黄山电器有限责任公司 | Junction termination structure of thyristor chip |
Non-Patent Citations (1)
| Title |
|---|
| 沈文正: "《实用集成电路工艺手册》", 31 October 1989 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108206207B (en) | 2022-04-08 |
| DE102016124669B3 (en) | 2018-05-17 |
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