CN108206207B - Thyristor with semiconductor body - Google Patents
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- CN108206207B CN108206207B CN201711351368.2A CN201711351368A CN108206207B CN 108206207 B CN108206207 B CN 108206207B CN 201711351368 A CN201711351368 A CN 201711351368A CN 108206207 B CN108206207 B CN 108206207B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 363
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 239000004642 Polyimide Substances 0.000 claims description 14
- 229920001721 polyimide Polymers 0.000 claims description 14
- 230000005684 electric field Effects 0.000 description 13
- 238000001465 metallisation Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The invention relates to a thyristor having a semiconductor body with a first semiconductor body main side, a second semiconductor body main side and a semiconductor body edge which surrounds the semiconductor body and connects the first and second semiconductor body main sides, the semiconductor body having: a first semiconductor region which extends in the semiconductor body edge region up to the second semiconductor body main side, a second outer surface of the first semiconductor region forming the semiconductor body edge, a third outer surface of the first semiconductor region adjoining the semiconductor body edge forming the first surface region of the second semiconductor body main side; a second semiconductor region arranged on the first semiconductor region and not extending to an edge of the semiconductor body; a third semiconductor region arranged on the second semiconductor region and a fourth semiconductor region arranged in the third semiconductor region; a recess emerges from the first surface of the second semiconductor body main side and runs parallel to the semiconductor body edge and reaches the second semiconductor region.
Description
Technical Field
The invention relates to a thyristor having a semiconductor body.
Background
In particular in the case of thyristors, it is often necessary to reduce the electric field strength generated at the edge regions of the semiconductor body of the thyristor in order to prevent electrical breakdown.
DE3832709a1 discloses a thyristor having a semiconductor body with a first semiconductor body main side, a second semiconductor body main side arranged opposite the first semiconductor body main side, and a semiconductor body edge surrounding the semiconductor body and connecting the first semiconductor body main side and the second semiconductor body main side, wherein the semiconductor body has a p-doped first semiconductor region, wherein an outer surface of the first semiconductor region forms the first semiconductor body main side, wherein the first semiconductor region extends in a semiconductor body edge region up to the second semiconductor body main side. The semiconductor body is here arranged with a p-doped field ring to reduce the electric field strength generated at the edge region of the semiconductor body of the thyristor. However, the fabrication of the field rings requires efforts in the manufacture of thyristors, since the field rings have to be fabricated in the semiconductor body by means of a suitable doping process.
Disclosure of Invention
It is an object of the invention to provide a thyristor with a semiconductor body which does not require any field ring to reduce the electric field strength generated at the edge regions of the semiconductor body of the thyristor.
The object is achieved by a thyristor having a semiconductor body with a first semiconductor body main side, a second semiconductor body main side arranged opposite the first semiconductor body main side, and a semiconductor body edge surrounding the semiconductor body and connecting the first semiconductor body main side and the second semiconductor body main side, wherein the semiconductor body has a first semiconductor region of a first conductivity type, wherein a first outer surface of the first semiconductor region forms the first semiconductor body main side, wherein the first semiconductor region extends in a semiconductor body edge region up to the second semiconductor body main side, a second outer surface of the first semiconductor region forms the semiconductor body edge, and a third outer surface of the first semiconductor region adjoining the semiconductor body edge forms a first surface region of the second semiconductor body main side, wherein the semiconductor body has a first surface region which is arranged on the first semiconductor region in an inner region of the semiconductor body and does not extend straight A second semiconductor region of the second conductivity type to an edge of the semiconductor body, wherein the semiconductor body has a third semiconductor region of the first conductivity type arranged on the second semiconductor region and a fourth semiconductor region of the second conductivity type arranged in the third semiconductor region, wherein the semiconductor body has a recess which emerges from the first surface of the second semiconductor body main side and runs parallel to the semiconductor body edge and reaches into the second semiconductor region.
Advantageous refinements of the invention emerge from the dependent claims.
It has proven to be advantageous if the entire first semiconductor body main side is of planar design. The semiconductor body therefore has no further recesses which emerge from the first main semiconductor body side and enter the semiconductor body. The thyristor can thus be easily connected in contact with a substrate (for example a DCB substrate) by means of, for example, a sintered connection, since the pressure applied to the thyristor necessary to produce the sintered connection does not lead to a destruction of the edge facing the semiconductor body.
Furthermore, it has proven to be advantageous if the recess extends up to the edge of the semiconductor body, since the electric field strength generated in the edge region of the semiconductor body is thereby significantly reduced.
Furthermore, it has proven to be advantageous if the semiconductor body has a first step and a second step in the region of the recess, the first step having a concavely running first bottom surface and the second step having a concavely running second bottom surface, wherein the first step is arranged closer to the center of the semiconductor body than the second step in a direction perpendicular to the normal direction of the first outer surface of the first semiconductor region, wherein the first bottom surface is not formed by the outer surfaces of the second semiconductor region and the second bottom surface is formed by the outer surfaces of the first, second and third semiconductor regions. In the design of such a semiconductor body, the electric field strength generated at the edge region of the semiconductor body is particularly significantly reduced.
In this connection, it has proven to be advantageous if the second bottom surface extends up to the edge of the semiconductor body and a portion of the second bottom surface forms the third outer surface of the first semiconductor region, since the electric field strength generated at the edge region of the semiconductor body is thus particularly significantly reduced.
In this connection, it has proven to be advantageous if the third outer surface of the first semiconductor region is of planar design, since the third outer surface is therefore of particularly simple design.
Furthermore, it has proven to be advantageous if the semiconductor body has a first step in the region of the recess, which first step has a concavely running first bottom surface which is not formed by the outer surface of the second semiconductor region and has a trench which reaches into the second semiconductor region. In the design of such a semiconductor body, the electric field strength generated at the edge region of the semiconductor body is particularly significantly reduced.
In this connection, it has proven to be advantageous if the first partial surface of the third outer surface of the first semiconductor region forms part of the trench junction surface of the trench, since the electric field strength generated at the edge region of the semiconductor body is thus particularly significantly reduced.
In this connection, it has proven to be advantageous if a second partial surface of the third outer surface of the first semiconductor region, which extends up to the edge of the semiconductor body, has a planar design, since the electric field strength generated at the edge region of the semiconductor body is thus particularly significantly reduced.
It has further proved advantageous if the third outer surface of the first semiconductor region has a concave contour, wherein in a semiconductor body edge region the semiconductor body has a fifth semiconductor region of the first conductivity type arranged on the second semiconductor region, wherein the geometry of the recess is designed such that the fifth semiconductor region is arranged physically separated from the first semiconductor region and the third semiconductor region. In the design of such a semiconductor body, the electric field strength generated at the edge region of the semiconductor body is particularly significantly reduced.
It has further proved advantageous if the recess emerges from an outer surface of the third semiconductor region or the fourth semiconductor region. The recess may arise from a preferably flat outer surface of the third semiconductor region and from a preferably flat outer surface of the fourth semiconductor region.
Furthermore, it proves to be advantageous if the boundary reaches the recess from the second semiconductor region to the third semiconductor region, since the electric field strength generated at the edge region of the semiconductor body is thus particularly significantly reduced.
It has further proved advantageous if the boundary reaches the recess from the first semiconductor region to the second semiconductor region, since the electric field strength generated at the edge region of the semiconductor body is thus particularly significantly reduced.
Furthermore, it has proven to be advantageous if the semiconductor body edge runs parallel to the normal direction of the first outer surface of the first semiconductor region from the first semiconductor body main side to the second semiconductor body main side, since the semiconductor body edge is therefore of particularly simple design.
Furthermore, it has proven to be advantageous if the semiconductor body has an outer surface which defines a recess, wherein at least a part of the outer surface of the semiconductor body which delimits the recess is formed as an outer surface of the silicon oxide layer of the respective semiconductor region, respectively, or the silicon oxide layer is arranged on at least a part of the outer surface of the semiconductor body which delimits the recess.
In this connection, it has proven to be advantageous if a polyimide layer is arranged on the silicon oxide layer.
Furthermore, it has proven to be advantageous if the semiconductor body has an outer surface which delimits the recess, wherein the polyimide layer is arranged on at least a part of the outer surface of the semiconductor body which delimits the recess.
Optionally, the polyimide layer used in combination with the silicon oxide layer instead of the glass passivation as is conventional in the field of thyristors may prevent or at least significantly temporarily delay the formation of a conductive inversion channel running from the first semiconductor region along the edge of the semiconductor body to the third semiconductor region.
It should generally be noted in this connection that the semiconductor region of the first conductivity type is preferably designed as a p-doped semiconductor region (p-conductivity type) and the semiconductor region of the second conductivity type is preferably designed as an n-doped semiconductor region (n-conductivity type). Alternatively, the semiconductor region of the first conductivity type can be designed as an n-doped semiconductor region (n-conductivity type) and the semiconductor region of the second conductivity type can be designed as a p-doped semiconductor region (p-conductivity type).
Drawings
Exemplary embodiments of the invention are described below with reference to the accompanying drawings, in which:
figure 1 shows a cross-sectional view of one design of a thyristor according to the invention,
figure 2 shows a top plan view of the thyristor of figure 1,
fig. 3 shows a cross-sectional view of another design of a thyristor according to the invention, an
Fig. 4 shows a cross-sectional view of another design of a thyristor according to the invention.
It should be noted that these figures are schematic diagrams. In the drawings, like elements have like reference numerals.
Detailed Description
Fig. 1 shows a cross-sectional view of one design of a thyristor 1 according to the invention, and fig. 2 shows a top plan view of the thyristor 1, wherein the thyristor 1 is shown in fig. 2 on a reduced scale compared to fig. 1, and the polyimide layer 23 of the thyristor 1 is not shown.
The thyristor 1 according to the invention has a semiconductor body 2, the semiconductor body 2 having a first semiconductor body main side 3, a second semiconductor body main side 4 arranged opposite the first semiconductor body main side 3, and a semiconductor body edge 28 which surrounds the semiconductor body 2 and connects the first and second semiconductor body main sides 3 and 4. The semiconductor material of the semiconductor body 2 preferably consists of silicon or silicon carbide.
The semiconductor body 2 has a first semiconductor region 5 of the first conductivity type, wherein a first outer surface 10 of the first semiconductor region 5 forms a first semiconductor body main side 3. The entire first semiconductor body main side 3 is preferably of planar design. In a semiconductor body edge region 25 of the semiconductor body 2, the first semiconductor region 5 extends as far as the second semiconductor body main side 4. The second outer surface of the first semiconductor region 5 forms a semiconductor body edge 28, and a third outer surface 40 of the first semiconductor region 5 adjoining the semiconductor body edge 28 forms a first surface region of the second semiconductor body main side 4.
The semiconductor body 2 has a second semiconductor region 6 of the second conductivity type which is arranged on the first semiconductor region 5 in the inner region IB of the semiconductor body 2 and does not extend as far as the semiconductor body edge 28. The semiconductor body 2 has a third semiconductor region 7 of the first conductivity type arranged on the second semiconductor region 6 and a fourth semiconductor region 8 of the second conductivity type arranged in the third semiconductor region 7. The fourth semiconductor region 8 forms trenches arranged in the third semiconductor region 7.
Furthermore, the semiconductor body 2 has a recess 15 which emerges from the preferably planar first surface 16 of the second semiconductor body main side 4, runs parallel to the semiconductor body edge 28, preferably parallel to the entire semiconductor body edge 28, and reaches into the second semiconductor region 6. The first surface 16 of the second semiconductor body main side 4 is arranged in an inner region 51 of the second semiconductor body main side 4. The recess 15 preferably extends in a closed manner around an inner region 51 of the second semiconductor body main side 4.
In the present invention, the recess 15 reduces the electric field strength generated at the edge region of the semiconductor body 2 of the thyristor during operation of the thyristor.
For the purpose of electrical connection, the thyristor 1 has a first metallization 12 arranged on the outer surface 10 of the first semiconductor region 5, a second metallization 14 arranged on the fourth semiconductor region 8 and a third metallization 24 arranged on the third semiconductor region 7. The first metallization 12 preferably forms an anodic metallization, the second metallization 14 preferably forms a cathodic metallization, and the third metallization 24 preferably forms a gate metallization. It should be noted that the third metallization 24 does not necessarily have to be arranged close to the semiconductor body edge 28 as shown, but may also be arranged in the region of the center M of the semiconductor body 2, for example in a corresponding design of the fourth semiconductor region 8.
The recess 15 preferably extends as far as the semiconductor body edge 28. The recess 15 preferably emerges from a preferably planar outer surface 31 of the third semiconductor region 7 or from a preferably planar outer surface 32 of the fourth semiconductor region 8. The first surface 16 of the second semiconductor body main side 4 is therefore preferably in the form of a preferably planar outer surface 31 of the third semiconductor region 7 or in the form of a preferably planar outer surface 32 of the fourth semiconductor region 8.
The boundary G1 from the second semiconductor region 6 to the third semiconductor region 7 preferably reaches the recess 15. The boundary G2 from the first semiconductor region 5 to the second semiconductor region 6 preferably reaches the recess 15.
The semiconductor body edge 28 preferably runs parallel to the normal direction N of the first outer surface 10 of the first semiconductor region 5 from the first semiconductor body main side 3 to the second semiconductor body main side 4. However, the semiconductor body edge 28 can also run obliquely from the first semiconductor body main side 3 to the second semiconductor body main side 4.
In the normal direction N of the first outer surface 10 of the first semiconductor region 5, the first semiconductor region 5 may have, for example, 10 μm to 1A thickness of 20 μm, in particular from 10 μm to 60 μm. In the normal direction N of the first outer surface 10 of the first semiconductor region 5, the third semiconductor region 7 may have a thickness of, for example, from 10 μm to 120 μm, in particular from 80 μm to 120 μm. In the context of the exemplary embodiment, the first semiconductor region 5 and the third semiconductor region 7 are p-doped, wherein the p-doping may be formed, for example, by diffusing boron, aluminum and/or gallium into the semiconductor material (e.g. silicon or silicon carbide) of the semiconductor body 2. The first, third and fifth semiconductor regions 5, 7 and 9 (see fig. 4) may each have, for example, 1 × 1015cm-3To 1X 1020cm-3Wherein the first, third and fifth semiconductor regions 5, 7 and 9 may have different doping concentrations. In the normal direction N of the first outer surface 10 of the first semiconductor region 5, in the inner region IB of the semiconductor body 2, the second semiconductor region 6 may have a thickness of, for example, 240 μm to 300 μm, in particular 230 μm to 250 μm, the second semiconductor region 6 may have a thickness of 1 × 1013cm-3To 1X 1014cm-3The doping concentration of (c). The fourth semiconductor region 8 may have a thickness of 5 μm to 40 μm, in particular 10 μm to 20 μm, in the normal direction N of the first outer surface 10 of the first semiconductor region 5. The fourth semiconductor region 8 may have, for example, a1 × 1019cm-3To 1X 1021cm-3The doping concentration of (c). Since the doping concentration of the fourth semiconductor region 8 is preferably higher than the doping concentration of the second semiconductor region 6, in the figures and the exemplary embodiments in which the second and fourth semiconductor regions 6 and 8 have an n-doping, the doping of the fourth semiconductor region 8 is denoted as n +, and the doping of the second semiconductor region 6 is denoted as n-. For example, an n-doped semiconductor region can be formed by diffusing phosphorus into the semiconductor material (for example silicon or silicon carbide) of the semiconductor body 2. The thickness T of the preferably planar first surface 16 of the recess 15 with respect to the second semiconductor body main side 4 is greater than the thickness of the third semiconductor region 7 and can be, for example, 121 μm to 150 μm, in particular, for example, 135 μm. It should be noted that the above specified values and value ranges are exemplary values and values that depend strongly on the desired reverse voltage and the desired characteristics of the thyristor 1, for exampleRanges, and thus significant deviations from the values and value ranges specified above are also possible. The thyristor 1 may have a reverse voltage of, for example, 1600V.
In the case of the exemplary embodiment according to fig. 1 and 2, the semiconductor body 2 has a first step 20 and a second step 20 'in the region 26 of the recess 15, the first step 20 having a first bottom surface running concavely and the second step 20' having a second bottom surface running concavely. The first step 20 is arranged closer to the center M of the semiconductor body 2 than the second step 20' in a direction perpendicular to the normal direction N of the first outer surface 10 of the first semiconductor region 5, wherein the first bottom surface is not formed by the outer surface of the second semiconductor region 6 and the second bottom surface is formed by the outer surfaces of the first, second and third semiconductor regions 5, 6 and 7. The second step 20' is preferably arranged adjacent to the first step 20. The second bottom surface preferably extends up to the semiconductor body edge 28 and a portion of the second bottom surface forms a third outer surface 40 of the first semiconductor region 5. The third outer surface 40 of the first semiconductor region 5 is preferably of planar design.
Fig. 3 shows a cross-sectional view of another design of a thyristor 1 according to the invention, which comprises possible advantageous designs, variants, dimensions and doping concentrations corresponding to the design of the thyristor 1 according to fig. 1 and 2, in addition to the differences described below. In the case of the exemplary embodiment according to fig. 3, as in the exemplary embodiment according to fig. 1 and 2, the semiconductor body 2 has a first step 20 in the region 26 of the recess 15, which first step 20 has a concavely running first bottom surface which is not formed by the outer surface of the second semiconductor region 6, wherein, in contrast to the exemplary embodiment according to fig. 1 and 2, the semiconductor body 2 has, in the region 26 of the recess 15, a preferably U-shaped trench 41 into the second semiconductor region 6. The first partial surface 40' of the third outer surface 40 of the first semiconductor region 5 preferably forms here a part of the trench-bonding surface of the trench 41. A second partial surface 40 ″ of the third outer surface 40 of the first semiconductor region 5, which extends up to the semiconductor body edge 28, is preferably of planar design.
Fig. 4 shows a cross-sectional view of another design of a thyristor 1 according to the invention, which comprises possible advantageous designs, variants, dimensions and doping concentrations corresponding to the design of the thyristor 1 according to fig. 1 and 2, in addition to the differences described below. In the case of the exemplary embodiment according to fig. 4, the third outer surface 40 of the first semiconductor region 5 has a concave contour, wherein, in contrast to the exemplary embodiment according to fig. 1 and 2, the semiconductor body 2 has, in the semiconductor body edge region 25, a fifth semiconductor region 9 of the first conductivity type arranged on the second semiconductor region 6, wherein the geometry of the recess is designed such that the fifth semiconductor region 9 is arranged physically separated from the first and third semiconductor regions 5 and 7.
In all exemplary embodiments, the semiconductor material of the semiconductor body 2 is preferably composed of silicon or silicon carbide, wherein at least a part of the outer surfaces 33, 34, 35 and 40 of the semiconductor body 2 delimiting the recess 15 can be designed as an outer surface of the silicon oxide layer 22 of the respective semiconductor region 5, 6, 7 and 9, respectively. The entire surface of the semiconductor body 2 which delimits the outer surface 33, 34, 35 and 40 of the recess 15 can be designed as an outer surface of the silicon oxide layer 22 of the respective semiconductor region 5, 6, 7 and 9, respectively.
In the exemplary embodiment, if the semiconductor material of the semiconductor body 2 consists of silicon or silicon carbide, the respective silicon oxide layer 22 is produced by oxidizing a respective outer surface region of the semiconductor body 2, with the result that, in the exemplary embodiment, the respective silicon oxide layer 22 is an integral part of the semiconductor body 2 and of a respective semiconductor region, the respective outer surface of which has been oxidized for the purpose of producing the silicon oxide layer. It should furthermore be noted that, in the context of the present invention, a layer, in particular a non-conductive layer, which is produced by a chemical reaction (for example oxidation) in a surface region of a semiconductor region of the semiconductor body 2 is a constituent of the relevant semiconductor region. The silica of each silica layer may be, for example, in the form of silicon monoxide or silicon dioxide, or in the form of a mixture of silicon monoxide and silicon dioxide. If the semiconductor material of the semiconductor body 2 consists of silicon carbide, the corresponding silicon oxide layer may also contain carbon.
The corresponding silicon oxide layer can also be produced by coating the corresponding semiconductor region with a suitable silicon oxide layer by means of a coating method, for example plasma coating. In this case, a silicon oxide layer is arranged on at least a part of the outer surface 33, 34, 35, 40 of the semiconductor body 2 delimiting the recess 15. A polyimide layer may be disposed on the silicon oxide layer.
The polyimide layer 23 is preferably arranged at least on a part of the outer surface 33, 34, 35 and 40 of the semiconductor body 2 delimiting the first recess 15. The polyimide layer 23 is preferably arranged on the entire surface of the outer surface 33, 34, 35 and 40 of the semiconductor body 2 delimiting the recess 15. In all exemplary embodiments, the outer surfaces 33, 34, 35 and 40 of the semiconductor body 2 which delimit the recess 15 may also not be designed as outer surfaces (not shown in the figures) of the silicon oxide layer 22 of the respective semiconductor region 5, 6, 7 or 9. In all exemplary embodiments, the polyimide layer 23 may also not be arranged on a non-conductive layer, in particular on a silicon oxide layer, in the region 26 of the recess 15.
The outer surfaces 33, 34, 35 and 40 delimiting the recess 15 respectively form the outer surfaces of the respective semiconductor regions.
If a polyimide layer is disposed on the silicon oxide layer, the polyimide layer is in mechanical contact with the silicon oxide layer.
The polyimide layer and the silicon oxide layer, if present, act as passivation layers. A conductive inversion channel running along the edge 28 of the semiconductor body can be formed due to the presence of the charges, which inversion channel leads to a conductive connection between the first and third semiconductor regions 5 and 7 of the semiconductor body 2. Using a polyimide layer as described above, optionally in combination with a silicon oxide layer, instead of glass passivation as is conventional in the field of thyristors, can prevent or at least significantly temporarily delay the formation of a conductive inversion channel running from the first semiconductor region 5 along the semiconductor body edge 28 to the third semiconductor region 7 and thus increase the lifetime of the thyristor.
It should be noted that the features of the different exemplary embodiments of the invention (provided that the features are not mutually exclusive) may of course be combined with each other in any desired manner in the present invention.
Claims (9)
1. Thyristor with a semiconductor body (2), the semiconductor body (2) having a first semiconductor body main side (3), a second semiconductor body main side (4) arranged opposite to the first semiconductor body main side (3) and a semiconductor body edge (28) which surrounds the semiconductor body (2) and connects the first semiconductor body main side (3) and the second semiconductor body main side (4), wherein the semiconductor body (2) has a first semiconductor region (5) of a first conductivity type, wherein a first outer surface (10) of the first semiconductor region (5) forms the first semiconductor body main side (3), wherein the first semiconductor region (5) extends in a semiconductor body edge region (25) up to the second semiconductor body main side (4), a second outer surface of the first semiconductor region (5) forms the semiconductor body edge (28), and a third outer surface (40) of the first semiconductor region (5) adjoining the semiconductor body edge (28) forms a first surface region of the second semiconductor body main side (4), wherein the semiconductor body (2) has a second semiconductor region (6) of the second conductivity type which is arranged on the first semiconductor region (5) in an inner region (IB) of the semiconductor body (2) and does not extend as far as the semiconductor body edge (28), wherein the semiconductor body (2) has a third semiconductor region (7) of the first conductivity type which is arranged on the second semiconductor region (6) and a fourth semiconductor region (8) of the second conductivity type which is arranged on the third semiconductor region (7), wherein the semiconductor body (2) has a recess (15), which recess (15) emerges from a first surface (16) of the second semiconductor body main side (4), runs parallel to the semiconductor body edge (28) and reaches into the second semiconductor region (6),
wherein the semiconductor body (2) has a first step (20) in a region (26) of the recess (15), which first step has a concavely running first bottom surface, and wherein the first bottom surface is not formed by an outer surface of the second semiconductor region (6),
wherein the semiconductor body (2) further has a trench (41) in the region (26) of the recess (15) into the second semiconductor region (6), and
wherein the third outer surface (40) of the first semiconductor region (5) has a concave contour, wherein in the semiconductor body edge region (25) the semiconductor body (2) has a fifth semiconductor region (9) of the first conductivity type arranged on the second semiconductor region (6), wherein the geometry of the recess is designed such that the fifth semiconductor region (9) is arranged physically separated from the first semiconductor region (5) and the third semiconductor region (7).
2. The thyristor according to claim 1, characterized in that the entire first semiconductor body main side (3) is of planar design.
3. A thyristor according to claim 1 or 2, characterized in that the recess (15) emerges from an outer surface (31, 32) of the third semiconductor region (7) or the fourth semiconductor region (8).
4. The thyristor according to claim 1 or 2, characterized in that a boundary (G1) reaches from the second semiconductor region (6) to the third semiconductor region (7) up to the recess (15).
5. The thyristor according to claim 1 or 2, characterized in that a boundary (G2) reaches from the first semiconductor region (5) to the second semiconductor region (6) up to the recess (15).
6. The thyristor according to claim 1 or 2, characterized in that the semiconductor body edge (28) extends parallel to a normal direction (N) of the first outer surface (10) of the first semiconductor region (5) from the first semiconductor body main side (3) to the second semiconductor body main side (4).
7. Thyristor according to claim 1 or 2, characterized in that the semiconductor body (2) has an outer surface (33, 34, 35, 40) delimiting the recess (15), wherein at least a part of the outer surface (33, 34, 35, 40) of the semiconductor body (2) delimiting the recess (15) is formed as an outer surface of a silicon oxide layer (22) of the respective semiconductor region (5, 6, 7, 9), respectively, or a silicon oxide layer is arranged on at least a part of the outer surface (33, 34, 35, 40) of the semiconductor body (2) delimiting the recess (15).
8. The thyristor according to claim 7, characterized in that a polyimide layer (23) is arranged on the silicon oxide layer.
9. Thyristor according to claim 1 or 2, characterized in that the semiconductor body (2) has an outer surface (33, 34, 35, 40) delimiting the recess (15), wherein a polyimide layer (23) is arranged on at least a part of the outer surface (33, 34, 35, 40) of the semiconductor body (2) delimiting the recess (15).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102016124669.7A DE102016124669B3 (en) | 2016-12-16 | 2016-12-16 | Thyristors with a respective semiconductor body |
| DE102016124669.7 | 2016-12-16 |
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| Publication Number | Publication Date |
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| CN108206207A CN108206207A (en) | 2018-06-26 |
| CN108206207B true CN108206207B (en) | 2022-04-08 |
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| CN201711351368.2A Active CN108206207B (en) | 2016-12-16 | 2017-12-15 | Thyristor with semiconductor body |
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| CN (1) | CN108206207B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102019105727B4 (en) * | 2019-03-07 | 2020-10-15 | Semikron Elektronik Gmbh & Co. Kg | Thyristor or diode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3628106A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
| US4047196A (en) * | 1976-08-24 | 1977-09-06 | Rca Corporation | High voltage semiconductor device having a novel edge contour |
| CN104934464A (en) * | 2014-09-03 | 2015-09-23 | 安徽省祁门县黄山电器有限责任公司 | Junction termination structure of thyristor chip |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1110993A (en) | 1967-01-09 | 1968-04-24 | Standard Telephones Cables Ltd | Semiconductors |
| US3644801A (en) | 1971-01-21 | 1972-02-22 | Gary S Sheldon | Semiconductor passivating process and product |
| JPS4974486A (en) | 1972-11-17 | 1974-07-18 | ||
| GB1499845A (en) | 1975-03-26 | 1978-02-01 | Mullard Ltd | Thyristors |
| JPS55133569A (en) | 1979-04-06 | 1980-10-17 | Hitachi Ltd | Semiconductor device |
| DE3832709A1 (en) | 1988-09-27 | 1990-03-29 | Asea Brown Boveri | THYRISTOR |
-
2016
- 2016-12-16 DE DE102016124669.7A patent/DE102016124669B3/en active Active
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2017
- 2017-12-15 CN CN201711351368.2A patent/CN108206207B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3628106A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
| US4047196A (en) * | 1976-08-24 | 1977-09-06 | Rca Corporation | High voltage semiconductor device having a novel edge contour |
| CN104934464A (en) * | 2014-09-03 | 2015-09-23 | 安徽省祁门县黄山电器有限责任公司 | Junction termination structure of thyristor chip |
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|---|---|
| CN108206207A (en) | 2018-06-26 |
| DE102016124669B3 (en) | 2018-05-17 |
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