CN108198783A - Metal interconnection structure and forming method thereof - Google Patents
Metal interconnection structure and forming method thereof Download PDFInfo
- Publication number
- CN108198783A CN108198783A CN201810022867.5A CN201810022867A CN108198783A CN 108198783 A CN108198783 A CN 108198783A CN 201810022867 A CN201810022867 A CN 201810022867A CN 108198783 A CN108198783 A CN 108198783A
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating layer
- contact hole
- conductive layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Technical solution of the present invention discloses a kind of metal interconnection structure and forming method thereof, and wherein forming method includes：Basal layer is provided, contains device architecture in the basal layer；The first insulating layer is formed on the basal layer；The contact hole through its thickness, device architecture described in the contact hole bottom-exposed are formed in first insulating layer；Conductive layer is formed in first surface of insulating layer and contact hole, when the gap opening width in conductive layer described in contact hole is to contact 1st/1/10th~eight of hole width, stopping forms the conducting layer craft；Second insulating layer is formed in the conductive layer surface and the gap；The second insulating layer and the conductive layer are polished to first insulating layer is exposed using polishing fluid, form conductive plunger, wherein the rate that the polishing fluid polishes the second insulating layer is less than the rate for polishing the conductive layer.The metal interconnection structure that the above method is formed effectively reduces dish-like defect, ensures the performance of metal interconnection.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor devices more particularly to metal interconnection structures and forming method thereof.
Background technology
With the rapid development of semiconductor devices manufacturing technology, semiconductor devices has had deep submicron structures.Due to
The quantity of contained device is continuously increased in integrated circuit, and the size of device also constantly reduces due to the promotion of integrated level.In order to
Integrated level is improved, reduces manufacture cost, the critical size of element constantly becomes smaller, and the number of elements in chip unit area constantly increases
Add, plane routing has been difficult to the requirement for meeting the distribution of element high density, can only use polylaminate wiring technique, utilize the vertical of chip
Space further improves the integration density of device.
It is existing in metal interconnection of semiconductor device structure-forming process, when being polished to conductive layer, easily generate it is dish-like lack
It falls into, and in follow-up insulating layer deposition, in dish-like fault location, thickness of insulating layer is partially thick, and the residual of insulating layer is caused after etching technics
It stays, and then causes open circuit, make metal interconnection failure.
Invention content
Technical solution of the present invention technical problems to be solved are to provide a kind of metal interconnection structure and forming method thereof, prevent
Breaking phenomena is generated in metal interconnection structure.
In order to solve the above technical problems, technical solution of the present invention provides a kind of forming method of metal interconnection structure, including：
Basal layer is provided, contains device architecture in the basal layer；The first insulating layer is formed on the basal layer；Described first absolutely
The contact hole through its thickness, device architecture described in the contact hole bottom-exposed are formed in edge layer；In first insulating layer
Conductive layer is formed in surface and contact hole, as ten that the gap opening width in conductive layer described in contact hole is contact hole width
When 1// mono-~eight, stopping forms the conducting layer craft；Is formed in the conductive layer surface and the gap
Two insulating layers；The second insulating layer is polished using polishing fluid and the conductive layer is led to first insulating layer, formation is exposed
Electric plug, wherein the rate that the polishing fluid polishes the second insulating layer is less than the rate for polishing the conductive layer.
Optionally, the material of the conductive layer is tungsten or aluminium, and the technique for forming the conductive layer is chemical vapour deposition technique.
Optionally, first insulating layer and the material of the second insulating layer are silicon nitride or silica.
Optionally, the technique for forming the second insulating layer is atomic layer deposition method.
Optionally, the technique for forming first insulating layer is chemical vapour deposition technique.
Optionally, the polishing fluid material of the second insulating layer and the conductive layer and the conductive are polished
Match.
Optionally, the second insulating layer and the technique of the conductive layer are polished, is included the following steps：First use polishing fluid
The second insulating layer is polished to the conductive layer, makes second insulating layer surface in the gap and the conductive layer surface neat
It is flat；Second insulating layer in the conductive layer and the gap is polished to exposing first insulating layer using polishing fluid.
Optionally, it is 10 that the polishing fluid, which polishes the conductive layer and the speed ratio of the second insulating layer,:1~20:1.
Optionally, before forming the conductive layer in first surface of insulating layer and contact hole, further include as
Lower step：Barrier layer is formed in the contact hole side wall and bottom.
Optionally, the material on the barrier layer is titanium or titanium nitride.
The metal interconnection structure formed using the above method, including：Basal layer contains device architecture in the basal layer；
First insulating layer, on the basal layer；Contact hole, in first insulating layer and through its thickness, the contact
Device architecture described in the bottom-exposed of hole；Conductive layer fills the contact hole；Gap, in conductive layer, and the gap opening
Width is contact hole width 1/1/10th~eight；Second insulating layer fills the full gap.
Compared with prior art, technical solution of the present invention has the advantages that：In first surface of insulating layer and
Conductive layer is formed in contact hole, as 1/10th that the gap opening width in conductive layer described in contact hole is contact hole width
When 1/8, stopping forms the conducting layer craft, and the surface area for making to be subsequently formed in the second insulating layer in gap is remote
Less than the surface area of conductive plunger, into without influencing the contact resistance between subsequent conductive plug and metal interconnecting layer；Then again
The polishing fluid for being less than the rate for polishing the conductive layer with the rate for polishing the second insulating layer is polished, due to polishing fluid
It is low to the polishing speed of second insulating layer, therefore the conductive layer at contact hole center is protected by second insulating layer, polishing speed
Also the conductive layer in other places is will be less than, effectively reduces dish-like defect, prevents generation breaking in interconnection structure, ensures that metal is mutual
Performance even.
Further, the second insulating layer is formed using atom layer deposition process, is formed due to atom layer deposition process
Film layer diffusivity is good, and it is not in very big gap that the second insulating layer can be made, which to deposit to width well, ensure that filling
Validity.
Description of the drawings
Fig. 1 to Fig. 3 is a kind of corresponding structure diagram of each step of metal interconnection structure formation method；
Fig. 4 to Fig. 8 is the corresponding structure diagram of each step of metal interconnection structure formation method in one embodiment of the invention；
Fig. 9 is the metal interconnection structure design sketch that one embodiment of the invention is formed.
Specific embodiment
By background technology it is found that the metal interconnection structure with conductive plunger that is formed of the prior art there are more open circuits
Situation causes the too low problem of semiconductor devices yield.In conjunction with electrical between a kind of metal interconnection structure analysis metal interconnection structure
Can be poor the reason of：
Fig. 1 to Fig. 3 shows the corresponding structure diagram of each step of metal interconnection structure formation method.As shown in Figure 1,
The first insulating layer 103 is formed on basal layer 101 comprising device architectures such as driving circuits, for the isolation between film layer, described
The material of one insulating layer 103 can be silica or silicon nitride；First insulating layer 103 is etched to the exposing basal layer
101 surfaces form contact hole 104.
As shown in Fig. 2, barrier layer 105 is formed in 104 side wall of contact hole of Fig. 1 and bottom, to prevent subsequent touch hole
Interior conductive materials are diffused in the first insulating layer 103；It is formed and led on first insulating layer 103 and the barrier layer 105
Electric layer, and the full contact hole of conductive layer filling；The conductive layer is polished using polishing fluid to insulate to exposing described first
Layer 103 forms conductive plunger 106.Since the material of conductive layer is mostly using tungsten, corresponding polishing fluid in existing polishing process
Also it is Wolfram polishing liquid, the Wolfram polishing liquid is more than the first insulating layer 103 for the polishing speed of conductive layer, therefore causes conductive insert
106 center surfaces are filled in less than edge, form dish-like defect.
As shown in figure 3, forming second insulating layer 107 on first insulating layer 103, the second insulating layer 107 is covered
Lid conductive plunger 106, and be formed in dish-like defect；Etch the second insulating layer 107 to expose the conductive plunger 106 and
103 surface of the first insulating layer of part forms groove, still remains second insulating layer 107 after etching technics in dish-like defect (as schemed
Middle dotted line mark)；Metal interconnecting layer 108 is filled into groove, due to remaining second insulating layer in dish-like defect, leads to metal
Interconnection layer 108 can not be conducted with conductive plunger 106, generate breaking phenomena, influence the electrical property of device.
To solve the technical problem, the present invention provides a kind of metal interconnection structure and forming method thereof, to contact hole
During interior deposition conductive layer, ratio of the gap opening width with contacting hole width in conductive layer is controlled, is made in follow-up gap
The megohmite insulant surface area of deposition is much smaller than the surface area of conductive layer in contact hole, can protect the conduction in contact hole centre position
Layer is not removed by too fast polishing and forms dish-like defect, and megohmite insulant can be made excessively will not to cause to block conductive plunger with after
The connection of continuous metal interconnecting layer.
Technical solution of the present invention is described in detail with reference to embodiment and attached drawing.
Fig. 4 to Fig. 8 is the corresponding structure diagram of each step of metal interconnection structure formation method in one embodiment of the invention.
As shown in figure 4, provide basal layer 201；The first insulating layer 203 is formed on the basal layer 201；Etch described
One insulating layer 203 forms contact hole 204 to the basal layer 201 is exposed.
In the present embodiment, the basal layer 201 includes：Using silicon or germanium etc. as the Semiconductor substrate of material, positioned at partly leading
The device architectures such as capacitor, driving circuit in body substrate.
In the present embodiment, first insulating layer 203 is for being dielectrically separated between film layer；First insulating layer 203
Material can be silica or silicon nitride etc., and formation process can be chemical vapour deposition technique.
In the present embodiment, the detailed step for forming 204 process of contact hole includes：On first insulating layer 203
Photoresist layer is formed, contact hole graph is then defined using exposure technology, is done using photoresist layer as mask along contact hole graph
Method etches first insulating layer 203 to exposing 201 surface of basal layer.In other embodiments, photoetching can formed
Before glue-line, prior to forming etching barrier layer on the first insulating layer 203, to subsequent etching process protect following film layer with
And formed in the first insulating layer of subsequent etching 203 as etch mask in contact hole technique, the material of the etching barrier layer can
To be silicon nitride, silicon oxynitride or polysilicon etc..
As shown in figure 5, form barrier layer 205 in 204 side wall of contact hole of Fig. 4 and bottom；In first insulating layer 203
With conductive layer 206 is formed on the barrier layer 205, and the conductive layer 206 fills the contact hole, passes through technology controlling and process, institute
Stating has gap 210 in the conductive layer 206 in contact hole；Second insulating layer 207, and institute are formed on 206 surface of conductive layer
State the full gap 210 of the filling of second insulating layer 207.
In the present embodiment, the concrete technology for forming the barrier layer 205 is as follows：With chemical vapour deposition technique described first
Barrier layer 205 is formed on insulating layer 203 and contact hole side wall and bottom, to prevent the conductive materials in subsequent touch hole from spreading
Into the first insulating layer 203.The material on the barrier layer 205 is titanium or titanium nitride etc..
In the present embodiment, the material of the conductive layer 206 can be tungsten or aluminium, and the technique for forming the conductive layer 206 is
Using chemical vapour deposition technique.When chemical vapour deposition technique forms the conductive layer 206, in order to have in follow-up polishing process
The conductive layer in the low megohmite insulant protection contact hole centre position of polishing speed, therefore the time control by controlling depositing operation
The conductive layer 206 makes the not completely filled full contact hole of the conductive layer 206 during filling the contact hole, but works as
Gap opening width in the conductive layer 206 is (in the present embodiment, to be stitched when contacting 1st/1/10th~eight of hole width
The width of gap opening refers to the diameter d of gap opening in the metal interconnection structure vertical view indicated in Fig. 9 dotted line frames；And it contacts
Hole width is contact bore dia D), stop depositing operation, the surface area for making to be subsequently formed in the second insulating layer in gap is far small
In the surface area of conductive plunger, the contact resistance between metal interconnection structure is not influenced.
In the present embodiment, the material of the second insulating layer 207 can be silica or silicon nitride etc..Form described second
The technique of insulating layer 207 is Atomic layer deposition method；The atom layer deposition process is formed using the mode repeatedly recycled
207 diffusivity of the second insulating layer it is good, can be good in diffusional deposition to the gap of width very little, ensure that described
Two insulating layers 207 can be filled up completely full gap.
As shown in fig. 6, polishing the second insulating layer 207 to 206 surface of conductive layer is exposed, make to stitch described in Fig. 5
207 surface of the second insulating layer in gap 201 is flushed with 206 surface of conductive layer.
In the present embodiment, the web shaped material of polishing fluid and the conductive layer 206 that the second insulating layer 207 uses is polished
Match, when such as the material of the conductive layer 206 is tungsten, the polishing fluid used is Wolfram polishing liquid；The material of the conductive layer 206 is aluminium
When, the polishing fluid used is aluminium polishing fluid.The polishing fluid polish the rate of the second insulating layer 207 for 100 A/min~
240 A/min.
As shown in fig. 7, the conductive layer 206 in Fig. 6 and the second insulating layer 207 in the gap are polished to exposing institute
The first insulating layer 203 is stated, forms conductive plunger 206a.
In the present embodiment, the polishing fluid of the second insulating layer 207 and the use of the conductive layer 206 and the conduction are polished
The match materials of layer 206.When material such as the conductive layer 206 is tungsten, the polishing fluid used is Wolfram polishing liquid；The conductive layer
When 206 material is aluminium, the polishing fluid used is aluminium polishing fluid.The polishing fluid polishes the conductive layer 206 and described second
The speed ratio of insulating layer 207 is 10:1~20:1.In the present embodiment, the rate that polishing fluid polishes the second insulating layer 207 is
100 A/min~240 A/min, the rate for polishing the conductive layer 206 is 2000 A/min~2400 A/min.Due to polishing fluid pair
It is low for the polishing speed of the second insulating layer 207 of material with silica or silicon nitride etc., thus polish the conductive layer 206 and
During the second insulating layer 207 in gap, the conductive layer 206 at contact hole center is by the second insulating layer 207
Protection, polishing speed will be far below the conductive layer 206 in other places, makes the conductive layer in finally formed conductive plunger 206a
Edge surface with intermediate 207 surface of second insulating layer close to flushing, efficiently solve dish-like defect in existing conductive plunger.
In the present embodiment, during due to the front and continued conductive layer filling contact hole, gap opening in the conductive layer is controlled
Width is with contacting the ratio of hole width within the scope of 1/1/10th~eight so that is deposited in gap after polishing process
The second insulating layer surface area conductive layer in effective protection contact hole centre position will not be unable to because of too small, cause by
Too fast polishing removal forms dish-like defect；Can make again in gap second insulating layer surface area will not be excessive and cause to block conductive insert
Plug is electrically connected with subsequent metal interconnection layer.
As shown in figure 8, third insulating layer 209 is formed on first insulating layer 203, and the third insulating layer 209
Cover the conductive plunger 206a；The third insulating layer 209 is etched, is formed and exposes the conductive plunger 206a surfaces and part
The groove on 203 surface of the first insulating layer；Full metal interconnecting layer 208 is filled in the trench.
In the present embodiment, the material of the third insulating layer 209 is silica or silicon nitride etc., forms the third insulation
The technique of layer 209 is chemical vapour deposition technique.
In the present embodiment, form groove and be as follows：Photoresist layer is formed on the third insulating layer 209,
Then groove figure is defined using exposure technology, insulated by third described in mask along groove figure dry etching of photoresist layer
Layer 209 is to exposing the conductive plunger 206a surfaces and 203 surface of the first insulating layer of part.
In the present embodiment, the material of the metal interconnecting layer 208 is copper or aluminium etc..Form the metal interconnecting layer 208
Technique is related with material for sputtering method or chemical vapour deposition technique or physical vaporous deposition, selected formation process.In other realities
It applies in example, can form diffusion impervious layer before the metal interconnecting layer 208 is formed prior to trenched side-wall, prevent follow-up gold
Belong to interconnection substance to diffuse in insulating layer.
The metal interconnection structure formed by the method for above-mentioned Fig. 4~Fig. 8, including：Basal layer 201, in the basal layer
Contain the device architectures such as capacitor, driving circuit；First insulating layer 203, on the basal layer 201, for film layer
Between be dielectrically separated from；Contact hole, in first insulating layer 203 and through its thickness, the contact hole bottom-exposed institute
State basal layer 201；Barrier layer 205, positioned at the contact hole side wall and bottom, to prevent the conductive materials in subsequent touch hole
It diffuses in the first insulating layer 203；Conductive plunger 206a fills the contact hole；Gap, positioned at the conductive plunger 206a
In, and the gap opening width is contact hole width 1/1/10th~eight；Second insulating layer 207 fills full institute
State gap；Third insulating layer 209, on first insulating layer 203；Groove, in the third insulating layer 209, and
Expose 203 surface of the conductive plunger 206a surfaces and the first insulating layer of part；Metal interconnecting layer 208 fills the full groove,
And it is electrically connected with conductive plunger 206a realizations.
Fig. 9 is the metal interconnection structure design sketch that one embodiment of the invention is formed.As shown in figure 9, pass through Fig. 4 to Fig. 8 institutes
In the metal interconnection structure that the formation process stated obtains, the surface area of the second insulating layer in conductive plunger in gap, which is much smaller than, leads
The surface area (shown in phantom in figure) of electric plug, therefore second insulating layer can be among effective protection contact hole in polishing process
The conductive tungsten layer of position is not removed by too fast polishing and forms dish-like defect, and will not influence conductive insert because surface area is excessive
Plug and being electrically connected between metal interconnecting layer, improve the electrical property of metal interconnection structure, ensure that the yield of semiconductor devices.
Although the present invention discloses as above in a preferred embodiment thereof, it is not for limiting the present invention, any ability
Field technique personnel without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this
Inventive technique scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to this hair
Any simple modifications, equivalents, and modifications that bright technical spirit makees embodiment of above, belong to the technology of the present invention
The protection domain of scheme.
Claims (11)
1. a kind of forming method of metal interconnection structure, which is characterized in that including：
Basal layer is provided, contains device architecture in the basal layer；
The first insulating layer is formed on the basal layer；
The contact hole through its thickness, device architecture described in the contact hole bottom-exposed are formed in first insulating layer；
Conductive layer is formed in first surface of insulating layer and contact hole, the gap opening in conductive layer described in contact hole
Width is when contacting 1st/1/10th~eight of hole width, and stopping forms the conducting layer craft；
Second insulating layer is formed in the conductive layer surface and the gap；
The second insulating layer and the conductive layer are polished to first insulating layer is exposed using polishing fluid, form conductive insert
Plug, wherein the rate that the polishing fluid polishes the second insulating layer is less than the rate for polishing the conductive layer.
2. the forming method of metal interconnection structure as described in claim 1, which is characterized in that the material of the conductive layer for tungsten or
Aluminium, the technique for forming the conductive layer are chemical vapour deposition technique.
3. the forming method of metal interconnection structure as described in claim 1, which is characterized in that first insulating layer and described
The material of two insulating layers is silicon nitride or silica.
4. the forming method of metal interconnection structure as claimed in claim 3, which is characterized in that form the work of the second insulating layer
Skill is atomic layer deposition method.
5. the forming method of metal interconnection structure as claimed in claim 3, which is characterized in that form the work of first insulating layer
Skill is chemical vapour deposition technique.
6. the forming method of metal interconnection structure as described in claim 1, which is characterized in that polish the second insulating layer and institute
The polishing fluid material for stating conductive layer is matched with the conductive.
7. the forming method of metal interconnection structure as claimed in claim 6, which is characterized in that polish the second insulating layer and institute
The technique for stating conductive layer, includes the following steps：
The second insulating layer is first polished to the conductive layer using polishing fluid, make second insulating layer surface in the gap with
The conductive layer surface flushes；
Second insulating layer in the conductive layer and the gap is polished to exposing first insulating layer using polishing fluid.
8. the forming method of metal interconnection structure as claimed in claim 7, which is characterized in that the polishing fluid polishes the conduction
Layer and the speed ratio of the second insulating layer are 10:1~20:1.
9. the forming method of metal interconnection structure as described in claim 1, which is characterized in that in first surface of insulating layer and
It is formed before the conductive layer in contact hole, further includes following steps：
Barrier layer is formed in the contact hole side wall and bottom.
10. the forming method of metal interconnection structure as claimed in claim 9, which is characterized in that the material on the barrier layer is titanium
Or titanium nitride.
11. a kind of metal interconnection structure formed such as claim 1~10 any one of them method, which is characterized in that including：
Basal layer contains device architecture in the basal layer；
First insulating layer, on the basal layer；
Contact hole, in first insulating layer and through its thickness, device architecture described in the contact hole bottom-exposed；
Conductive layer fills the contact hole；
Gap, in conductive layer, and the gap opening width is contact hole width 1/1/10th~eight；
Second insulating layer fills the full gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810022867.5A CN108198783B (en) | 2018-01-10 | 2018-01-10 | Metal interconnection structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810022867.5A CN108198783B (en) | 2018-01-10 | 2018-01-10 | Metal interconnection structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108198783A true CN108198783A (en) | 2018-06-22 |
| CN108198783B CN108198783B (en) | 2020-03-31 |
Family
ID=62588690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810022867.5A Active CN108198783B (en) | 2018-01-10 | 2018-01-10 | Metal interconnection structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108198783B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146932A (en) * | 1999-08-02 | 2000-11-14 | Hyundai Microelectronics Co., Ltd. | Method for fabricating metal-oxide-semiconductor field effect transistor device |
| CN101330042A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and preparation method thereof |
| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN103497688A (en) * | 2013-09-30 | 2014-01-08 | 上海新安纳电子科技有限公司 | Chemical mechanical polishing method for phase-change material |
| CN105449101A (en) * | 2014-09-01 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of forming phase change random access memory (PCRAM) cell |
-
2018
- 2018-01-10 CN CN201810022867.5A patent/CN108198783B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146932A (en) * | 1999-08-02 | 2000-11-14 | Hyundai Microelectronics Co., Ltd. | Method for fabricating metal-oxide-semiconductor field effect transistor device |
| CN101330042A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and preparation method thereof |
| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN103497688A (en) * | 2013-09-30 | 2014-01-08 | 上海新安纳电子科技有限公司 | Chemical mechanical polishing method for phase-change material |
| CN105449101A (en) * | 2014-09-01 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of forming phase change random access memory (PCRAM) cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108198783B (en) | 2020-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100640662B1 (en) | Semiconductor device having a barrier metal spacer and method of fabricating the same | |
| JP2003017558A (en) | Semiconductor device and method of manufacturing same | |
| WO2010017162A1 (en) | Through silicon via and method of fabricating same | |
| KR20020068746A (en) | Semiconductor device with contact plug and method for manufacturing the same | |
| JPH05206290A (en) | Method for formation of via for multilayer interconnection integrated circuit use | |
| JP2003197623A (en) | Semiconductor device | |
| KR19990030228A (en) | Double damask processing method to provide dielectric layer between metal layer and organic metal | |
| KR100266749B1 (en) | A method of forming contact plug of semiconductor device | |
| CN102856247A (en) | Back silicon through hole making method | |
| TWI244160B (en) | Method for manufacturing dual damascene structure with a trench formed first | |
| KR100393967B1 (en) | method for forming metal line of semiconductor device | |
| CN108198783A (en) | Metal interconnection structure and forming method thereof | |
| JPH09246375A (en) | Method of forming interconnection and manufacture of semiconductor device | |
| JPS62229959A (en) | Method of filling passage or contact hole in layer insulatorin multilayer metal covered very large scale integrated circuit | |
| US6977216B2 (en) | Method for forming metal wire in semiconductor device | |
| US6563221B1 (en) | Connection structures for integrated circuits and processes for their formation | |
| KR100800823B1 (en) | Method for forming via hole of semiconductor device with mim type capacitor | |
| WO2022104972A1 (en) | Semiconductor device and manufacturing method therefor | |
| KR20120008337A (en) | Semiconductor device and method for forming the same | |
| KR100485391B1 (en) | Method for forming metal wiring in semiconductor manufacturing process | |
| KR100548527B1 (en) | Method for forming interconnection | |
| KR100632042B1 (en) | Method for forming metal layer of semiconductor device | |
| KR20030089569A (en) | Method for forming mim capacitor | |
| KR20080061168A (en) | Method of manufacturing a metal line in semiconductor device | |
| KR100579856B1 (en) | Metal line formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230714 Address after: 223001 Room 318, Building 6, east of Zhenda Steel Pipe Company, south of Qianjiang Road, Huaiyin District, Huai'an City, Jiangsu Province Patentee after: Huaian Xide Industrial Design Co.,Ltd. Address before: 223300 no.599, East Changjiang Road, Huaiyin District, Huai'an City, Jiangsu Province Patentee before: HUAIAN IMAGING DEVICE MANUFACTURER Corp. |