CN108196953B - A kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data - Google Patents
A kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data Download PDFInfo
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- CN108196953B CN108196953B CN201711456225.8A CN201711456225A CN108196953B CN 108196953 B CN108196953 B CN 108196953B CN 201711456225 A CN201711456225 A CN 201711456225A CN 108196953 B CN108196953 B CN 108196953B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
The invention discloses a kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data, which is realized using the ZYNQ-7000SoC chip of Xilinx company, including：The data of collected distinct device are buffered in outside different offset address and the piece of size in DDR by the isomerous multi-source big data parallel acquisition module based on FPGA, the module respectively in a manner of DMA, and through the port HP in piece；DDR outside piece is mounted in piece in AXI bus by design point machine simultaneously.Parallel data processing module based on heterogeneous polynuclear builds multiple MicroBlaze cores in the module, and forms heterogeneous polynuclear framework with ARM core；Different MicroBlaze core is responsible for handling different device datas；ARM core completes the performance monitoring to multiple MicroBlaze cores, operation of the different data processing algorithm of dynamic dispatching on multiple MicroBlaze cores, to guarantee the load balancing of core.The present invention can be realized the efficient parallel processing for manufacturing live distinct device big data, can effectively support intelligence manufacture upper layer decision.
Description
Technical field
The invention belongs to electronic engineering and computer science, and in particular to a kind of towards the different of isomerous multi-source big data
Structure multi-core parallel concurrent processing unit and method.
Background technique
With the proposition of national strategy " made in China 2025 ", intelligence manufacture has become the hot spot noun of contemporary China.But
It is to realize that intelligence manufacture be unable to do without data, these data more specifically show as the data at manufacture scene, and miscellaneous set
It is standby to constitute manufacture scene, for example supporting industry Ethernet interface, RS232 interface, asynchronous RS422 interface, asynchronous RS485 connect
Mouth, synchronous RS485 interface, SPI interface, I2C interface, the equipment of CAN interface, MTConnect interface and OPC UA interface.For
Realize the effective monitoring to manufacture scene, realizing just seems to the data parallel acquisition of the various equipment in scene and processing and especially must
It wants, and traditional method mostly uses greatly multiple processor/embedded microprocessors to acquire, handle different number of devices respectively
According to then these processor/embedded microprocessors carry out data interaction by way of piece external bus again, and this traditional
Mode certainly will increase the quantity of collection in worksite, processing unit, increase cost, also increase the difficulty of field layout wiring, together
When the data interaction based on piece external bus also increase time delay, reduce data transmission, processing real-time.So needing to seek
It is a kind of to can be realized the method for parallel processing and device for manufacturing live heterogeneous device, and this method and device are able to use quantity very
The data acquisition and procession of numerous equipment can be completed in few processor/embedded microprocessor, while reducing data interaction
Time delay.
SoC (System on Chip, system on chip) is a kind of system-level microprocessor, be generally integrated with including
The processors such as FPGA, ARM, Microblaze, DSP, FPGA have the hardware concurrent characteristic of height, can be realized plurality of devices number
According to parallel acquisition, by building multiple Microblaze cores, the data processing task of each core operation distinct device, in conjunction with
The dynamic dispatching of task, a kind of method for realizing heterogeneous device big data parallel processing of can yet be regarded as.Therefore, the present invention proposes one kind
Heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data, the device and method can be realized manufacture scene not
Efficient parallel with equipment big data is handled, and can effectively support intelligence manufacture upper layer decision.
Summary of the invention
The technical problem to be solved in the present invention is：A kind of heterogeneous polynuclear parallel processing towards isomerous multi-source big data is provided
Device and method, the device and method can be realized the efficient parallel processing to heterogeneous device big data.
The present invention solves its technical problem and adopts the following technical solutions to achieve：It is a kind of towards isomerous multi-source big data
Heterogeneous polynuclear parallel processing apparatus, including：
Isomerous multi-source big data parallel acquisition module based on FPGA,
1. being somebody's turn to do the isomerous multi-source big data parallel acquisition module based on FPGA has 10 kinds of data-interfaces, can be realized to 10
The data acquisition of kind different agreement, and then realize and the data of distinct device are acquired, specific data-interface includes industrial
Ethernet interface, RS232 interface, asynchronous RS422 interface, asynchronous RS485 interface, synchronous RS485 interface, SPI interface, I2C
Interface, CAN interface, MTConnect interface and OPC UA Server interface；The isomerous multi-source big data based on FPGA is simultaneously
The data for the distinct device that row acquisition module arrives parallel acquisition are buffered in respectively in a manner of DMA, and through the port HP in piece
In different offset address and the outer DDR of the piece of size；
2. design point machine should be passed through based on the isomerous multi-source big data parallel acquisition module of FPGA to complete to DDR outside piece
DDR outside piece is mounted in piece in AXI bus by AXI interface encapsulation, realization；
Parallel data processing module based on heterogeneous polynuclear,
1. 15 MicroBlaze cores are built in the parallel data processing module based on heterogeneous polynuclear, and with ARM core
Heterogeneous polynuclear framework is formed, these cores are all mounted in piece in AXI bus, while being distinct device point in AXI bus in piece
With different memory address, the communication between core and core, between core and the outer DDR of piece is realized；
2. different MicroBlaze core is responsible for handling different device datas, it is buffered in outside piece in DDR including reading
Data execute different Processing Algorithms, specially：MicroBlaze-1 core is responsible for industrial Eternet data, MicroBlaze-
2 cores are responsible for RS232 data, MicroBlaze-3 core is responsible for asynchronous RS422 data, MicroBlaze-4 core is responsible for asynchronous RS485
Data, MicroBlaze-5 core are responsible for synchronous RS485 data, MicroBlaze-6 core is responsible for SPI data, MicroBlaze-7 core
Be responsible for I2C data, MicroBlaze-8 core is responsible for CAN data, MicroBlaze-9 core is responsible for MTConnect data,
MicroBlaze-10 core is responsible for OPC UA data；MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13
Core, MicroBlaze-14 core, MicroBlaze-15 core wouldn't execute any task as spare；
3. ARM core completes the performance monitoring to multiple MicroBlaze cores, the different data processing algorithm of dynamic dispatching exists
Operation on multiple MicroBlaze cores, to guarantee the load balancing of core, ARM core is by monitoring each MicroBlaze core and piece
The data exchange rate of interior AXI bus judges the processor resource utilization rate of each MicroBlaze core, when any one
When the processor resource utilization rate of MicroBlaze core is excessively high, the dynamic dispatching of ARM core is temporarily not carried out any task
MicroBlaze core shares executing on the MicroBlaze core for task, is not carried out the MicroBlaze of any task here
Core not only include 2. in build MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core also include remaining the MicroBlaze core for being temporarily not carried out any task.
A kind of heterogeneous polynuclear parallel processing apparatus towards isomerous multi-source big data that the present invention designs is public using Xilinx
ZYNQ-7000SoC chip is taken charge of to realize.
A kind of heterogeneous polynuclear method for parallel processing towards isomerous multi-source big data, includes the following steps：
Step 1：Isomerous multi-source big data parallel acquisition module based on FPGA, is implemented as follows：
1. being somebody's turn to do the isomerous multi-source big data parallel acquisition module based on FPGA has 10 kinds of data-interfaces, can be realized to 10
The data acquisition of kind different agreement, and then realize and the data of distinct device are acquired, specific data-interface includes industrial
Ethernet interface, RS232 interface, asynchronous RS422 interface, asynchronous RS485 interface, synchronous RS485 interface, SPI interface, I2C
Interface, CAN interface, MTConnect interface and OPC UA Server interface；The isomerous multi-source big data based on FPGA is simultaneously
The data for the distinct device that row acquisition module arrives parallel acquisition are buffered in respectively in a manner of DMA, and through the port HP in piece
In different offset address and the outer DDR of the piece of size；
2. design point machine should be passed through based on the isomerous multi-source big data parallel acquisition module of FPGA to complete to DDR outside piece
DDR outside piece is mounted in piece in AXI bus by AXI interface encapsulation, realization；
Step 2：Parallel data processing module based on heterogeneous polynuclear, is implemented as follows：
1. 15 MicroBlaze cores are built in the parallel data processing module based on heterogeneous polynuclear, and with ARM core
Heterogeneous polynuclear framework is formed, these cores are all mounted in piece in AXI bus, while being distinct device point in AXI bus in piece
With different memory address, the communication between core and core, between core and the outer DDR of piece is realized；
2. different MicroBlaze core is responsible for handling different device datas, it is buffered in outside piece in DDR including reading
Data execute different Processing Algorithms, specially：MicroBlaze-1 core is responsible for industrial Eternet data, MicroBlaze-
2 cores are responsible for RS232 data, MicroBlaze-3 core is responsible for asynchronous RS422 data, MicroBlaze-4 core is responsible for asynchronous RS485
Data, MicroBlaze-5 core are responsible for synchronous RS485 data, MicroBlaze-6 core is responsible for SPI data, MicroBlaze-7 core
Be responsible for I2C data, MicroBlaze-8 core is responsible for CAN data, MicroBlaze-9 core is responsible for MTConnect data,
MicroBlaze-10 core is responsible for OPC UA data；MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13
Core, MicroBlaze-14 core, MicroBlaze-15 core wouldn't execute any task as spare；
3. ARM core completes the performance monitoring to multiple MicroBlaze cores, the different data processing algorithm of dynamic dispatching exists
Operation on multiple MicroBlaze cores, to guarantee the load balancing of core, ARM core is by monitoring each MicroBlaze core and piece
The data exchange rate of interior AXI bus judges the processor resource utilization rate of each MicroBlaze core, when any one
When the processor resource utilization rate of MicroBlaze core is excessively high, the dynamic dispatching of ARM core is temporarily not carried out any task
MicroBlaze core shares executing on the MicroBlaze core for task, is not carried out the MicroBlaze of any task here
Core not only include 2. in build MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core also include remaining the MicroBlaze core for being temporarily not carried out any task.
A kind of heterogeneous polynuclear method for parallel processing towards isomerous multi-source big data that the present invention designs is public using Xilinx
ZYNQ-7000SoC chip is taken charge of to realize.
The advantages of the present invention over the prior art are that：
(1) it by the interconnection of AXI bus in piece, can reduce between each core and between each core and piece external equipment
Communication delay improves the real-time of isomeric data interaction；
(2) by constructing multiple MicroBlaze cores, each core executes different data processing tasks, can be realized a variety of
The parallel processing of data, while the monitoring and dynamic dispatching to multiple MicroBlaze nuclearity energy based on ARM core are different
Operation of the data processing algorithm on multiple MicroBlaze cores can realize data while guaranteeing each core load balancing
Process resource is distributed rationally, and the efficiency of isomerous multi-source big data parallel processing is promoted.
Detailed description of the invention
Fig. 1 is a kind of structural block diagram of the heterogeneous polynuclear parallel processing apparatus towards isomerous multi-source big data of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to the accompanying drawing.
The present invention relates to a kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data, the device and
Method is realized using the ZYNQ-7000SoC chip of Xilinx company, including the isomerous multi-source big data parallel acquisition based on FPGA
Module and parallel data processing module based on heterogeneous polynuclear.For parallel acquisition, the place for manufacturing live heterogeneous device big data
Reason needs, and the present invention is able to ascend the efficiency of isomerous multi-source big data parallel processing.
Structural block diagram of the invention is as shown in Figure 1, specific embodiment is as follows：
(1) 2 in Fig. 1 are the isomerous multi-source big data parallel acquisition modules based on FPGA, are implemented as follows：
1. being somebody's turn to do the isomerous multi-source big data parallel acquisition module based on FPGA has 10 kinds of data-interfaces, can be realized to 10
The data acquisition of kind different agreement, and then realize and the data of distinct device are acquired, as shown in 1 in attached drawing 1：It can specifically adopt
The data-interface of collection includes industrial Eternet interface, RS232 interface, asynchronous RS422 interface, asynchronous RS485 interface, synchronization
RS485 interface, SPI interface, I2C interface, CAN interface, MTConnect interface and OPC UA Server interface；FPGA is called
DDR (attached drawing 1 outside the HP port transmission to piece that collected isomeric data is passed through ZYNQ-7000SoC chip interior by DMA IP kernel
In 4), these data are respectively stored in different offset address and size memory space；
2. since DDR device cannot be directly mounted in piece in AXI bus outside piece, so should the isomerous multi-source based on FPGA
Big data parallel acquisition module design state machine is packaged ddr interface outside piece, and the outer DDR of the piece after encapsulation can be assisted with AXI
View transmission data, also can serve as equipment and are mounted in piece in AXI bus；
(2) 3 in Fig. 1 are the parallel data processing modules based on heterogeneous polynuclear, are implemented as follows：
1. 15 MicroBlaze cores are built in the parallel data processing module based on heterogeneous polynuclear, and with ARM core
Heterogeneous polynuclear framework is formed, these cores are all mounted in piece in AXI bus, while being distinct device point in AXI bus in piece
With different memory address, the communication between core and core, between core and the outer DDR of piece is realized；
2. different MicroBlaze core is responsible for handling different device datas, it is buffered in outside piece in DDR including reading
Data execute different Processing Algorithms.Specially：MicroBlaze-1 core is responsible for industrial Eternet data, MicroBlaze-
2 cores are responsible for RS232 data, MicroBlaze-3 core is responsible for asynchronous RS422 data, MicroBlaze-4 core is responsible for asynchronous RS485
Data, MicroBlaze-5 core are responsible for synchronous RS485 data, MicroBlaze-6 core is responsible for SPI data, MicroBlaze-7 core
Be responsible for I2C data, MicroBlaze-8 core is responsible for CAN data, MicroBlaze-9 core is responsible for MTConnect data,
MicroBlaze-10 core is responsible for OPC UA data；MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13
Core, MicroBlaze-14 core, MicroBlaze-15 core wouldn't execute any task as spare；
3. ARM core completes the performance monitoring to multiple MicroBlaze cores, the different data processing algorithm of dynamic dispatching exists
Operation on multiple MicroBlaze cores, to guarantee the load balancing of core.ARM core is by monitoring each MicroBlaze core and piece
The data exchange rate of interior AXI bus judges the processor resource utilization rate of each MicroBlaze core：When one
MicroBlaze core and the data exchange rate of AXI bus in piece are higher, illustrate the task that the MicroBlaze core is carrying out
Data volume to be treated is bigger, then the processor resource utilization rate of the MicroBlaze core just necessarily will increase, simultaneously
It is reference with the maximum data exchange rate of AXI bus in piece, so that it may the processor money of the MicroBlaze core be calculated
Source utilization rate.When the processor resource utilization rate of any one MicroBlaze core is excessively high, ARM core dynamic dispatching does not have temporarily
The MicroBlaze core of any task is executed to share executing on the MicroBlaze core for task.Here it is not carried out any
The MicroBlaze core of business not only include 2. in build MicroBlaze-11 core, MicroBlaze-12 core,
MicroBlaze-13 core, MicroBlaze-14 core, MicroBlaze-15 core also include temporarily being not carried out any task
Remaining MicroBlaze core：MicroBlaze-1 core, MicroBlaze-2 core, MicroBlaze-3 core, MicroBlaze-4 core,
MicroBlaze-5 core, MicroBlaze-6 core, MicroBlaze-7 core, MicroBlaze-8 core, MicroBlaze-9 core,
MicroBlaze-10 core.
In conclusion the invention discloses a kind of heterogeneous polynuclear parallel processing apparatus towards isomerous multi-source big data, packet
Include the isomerous multi-source big data parallel acquisition module based on FPGA and the parallel data processing module based on heterogeneous polynuclear.The present invention
It is able to ascend the efficiency of isomerous multi-source big data parallel processing, can effectively support intelligence manufacture upper layer decision.
The content that description in the present invention is not described in detail belongs to the prior art well known to professional and technical personnel in the field.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (4)
1. a kind of heterogeneous polynuclear parallel processing apparatus towards isomerous multi-source big data, it is characterised in that including：
Isomerous multi-source big data parallel acquisition module based on FPGA,
1. being somebody's turn to do the isomerous multi-source big data parallel acquisition module based on FPGA has 10 kinds of data-interfaces, can be realized to 10 kinds not
Data with agreement acquire, and then realize and acquire to the data of distinct device, and specific data-interface includes that industrial Eternet connects
Mouth, RS232 interface, asynchronous RS422 interface, asynchronous RS485 interface, synchronous RS485 interface, SPI interface, I2C interface, CAN connect
Mouth, MTConnect interface and OPC UA Server interface；The isomerous multi-source big data parallel acquisition module based on FPGA
The data for the distinct device that parallel acquisition is arrived are buffered in the outer DDR of piece not in a manner of DMA, and through the port HP in piece respectively
With in offset address and size memory space；
2. the completion of design point machine should be passed through based on the isomerous multi-source big data parallel acquisition module of FPGA to the AXI of DDR outside piece
DDR outside piece is mounted in piece in AXI bus by interface encapsulation, realization；
Parallel data processing module based on heterogeneous polynuclear,
1. building 15 MicroBlaze cores in the parallel data processing module based on heterogeneous polynuclear, and formed with ARM core
Heterogeneous polynuclear framework, these cores are all mounted in piece in AXI bus, while not for distinct device distribution in AXI bus in piece
Same memory address realizes the communication between core and core, between core and the outer DDR of piece；
2. different MicroBlaze core is responsible for handling different device datas, including reading the data being buffered in outside piece in DDR,
Different Processing Algorithms is executed, specially：It is negative that MicroBlaze-1 core is responsible for industrial Eternet data, MicroBlaze-2 core
Blame RS232 data, MicroBlaze-3 core is responsible for asynchronous RS422 data, MicroBlaze-4 core is responsible for asynchronous RS485 data,
MicroBlaze-5 core is responsible for synchronous RS485 data, MicroBlaze-6 core is responsible for SPI data, MicroBlaze-7 core is responsible for
I2C data, MicroBlaze-8 core are responsible for CAN data, MicroBlaze-9 core is responsible for MTConnect data, MicroBlaze-
10 cores are responsible for OPC UA data；MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core wouldn't execute any task as spare；
3. ARM core completes the performance monitoring to multiple MicroBlaze cores, the different data processing algorithm of dynamic dispatching is multiple
Operation on MicroBlaze core, to guarantee the load balancing of core, ARM core is by monitoring in each MicroBlaze core and piece
The data exchange rate of AXI bus judges the processor resource utilization rate of each MicroBlaze core, when any one
When the processor resource utilization rate of MicroBlaze core is excessively high, the dynamic dispatching of ARM core is temporarily not carried out any task
MicroBlaze core shares executing on the MicroBlaze core for task, is not carried out the MicroBlaze of any task here
Core not only include 2. in build MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core also include remaining the MicroBlaze core for being temporarily not carried out any task.
2. a kind of heterogeneous polynuclear parallel processing apparatus towards isomerous multi-source big data as described in claim 1, feature exist
In：The device is realized using the ZYNQ-7000SoC chip of Xilinx company.
3. a kind of heterogeneous polynuclear method for parallel processing towards isomerous multi-source big data, it is characterised in that：Include the following steps：
Step 1：Isomerous multi-source big data parallel acquisition module based on FPGA, is implemented as follows：
1. being somebody's turn to do the isomerous multi-source big data parallel acquisition module based on FPGA has 10 kinds of data-interfaces, can be realized to 10 kinds not
Data with agreement acquire, and then realize and acquire to the data of distinct device, and specific data-interface includes that industrial Eternet connects
Mouth, RS232 interface, asynchronous RS422 interface, asynchronous RS485 interface, synchronous RS485 interface, SPI interface, I2C interface, CAN connect
Mouth, MTConnect interface and OPC UA Server interface；The isomerous multi-source big data parallel acquisition module based on FPGA
The data for the distinct device that parallel acquisition is arrived are buffered in the outer DDR of piece not in a manner of DMA, and through the port HP in piece respectively
With in offset address and size memory space；
2. the completion of design point machine should be passed through based on the isomerous multi-source big data parallel acquisition module of FPGA to the AXI of DDR outside piece
DDR outside piece is mounted in piece in AXI bus by interface encapsulation, realization；
Step 2：Parallel data processing module based on heterogeneous polynuclear, is implemented as follows：
1. building 15 MicroBlaze cores in the parallel data processing module based on heterogeneous polynuclear, and formed with ARM core
Heterogeneous polynuclear framework, these cores are all mounted in piece in AXI bus, while not for distinct device distribution in AXI bus in piece
Same memory address realizes the communication between core and core, between core and the outer DDR of piece；
2. different MicroBlaze core is responsible for handling different device datas, including reading the data being buffered in outside piece in DDR,
Different Processing Algorithms is executed, specially：It is negative that MicroBlaze-1 core is responsible for industrial Eternet data, MicroBlaze-2 core
Blame RS232 data, MicroBlaze-3 core is responsible for asynchronous RS422 data, MicroBlaze-4 core is responsible for asynchronous RS485 data,
MicroBlaze-5 core is responsible for synchronous RS485 data, MicroBlaze-6 core is responsible for SPI data, MicroBlaze-7 core is responsible for
I2C data, MicroBlaze-8 core are responsible for CAN data, MicroBlaze-9 core is responsible for MTConnect data, MicroBlaze-
10 cores are responsible for OPC UA data；MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core wouldn't execute any task as spare；
3. ARM core completes the performance monitoring to multiple MicroBlaze cores, the different data processing algorithm of dynamic dispatching is multiple
Operation on MicroBlaze core, to guarantee the load balancing of core, ARM core is by monitoring in each MicroBlaze core and piece
The data exchange rate of AXI bus judges the processor resource utilization rate of each MicroBlaze core, when any one
When the processor resource utilization rate of MicroBlaze core is excessively high, the dynamic dispatching of ARM core is temporarily not carried out any task
MicroBlaze core shares executing on the MicroBlaze core for task, is not carried out the MicroBlaze of any task here
Core not only include 2. in build MicroBlaze-11 core, MicroBlaze-12 core, MicroBlaze-13 core,
MicroBlaze-14 core, MicroBlaze-15 core also include remaining the MicroBlaze core for being temporarily not carried out any task.
4. a kind of heterogeneous polynuclear method for parallel processing towards isomerous multi-source big data as claimed in claim 3, feature exist
In：The method is realized using the ZYNQ-7000SoC chip of Xilinx company.
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| CN113126569B (en) * | 2021-04-19 | 2022-03-08 | 北京航空航天大学 | Digital twin equipment construction method and system |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194403A (en) * | 2010-03-17 | 2011-09-21 | 上海仰邦软件科技有限公司 | Microblaze soft core technology-based LED (Light Emitting Diode) large-screen asynchronous control system |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN103941619A (en) * | 2014-04-16 | 2014-07-23 | 南京国电南自美卓控制系统有限公司 | Reconfigurable microcomputer protection development platform based on FPGA |
| CN105242594A (en) * | 2015-09-23 | 2016-01-13 | 成都乐维斯科技有限公司 | Logic control system based on Microblaze soft core processor |
| CN105260164A (en) * | 2015-09-25 | 2016-01-20 | 北京航空航天大学 | Multi-core SoC architecture design method supporting multi-task parallel execution |
| CN105260339A (en) * | 2015-08-17 | 2016-01-20 | 中南大学 | Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology |
| CN106650411A (en) * | 2016-11-24 | 2017-05-10 | 天津津航计算技术研究所 | Verification system for cryptographic algorithms |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339492A (en) * | 2008-08-11 | 2009-01-07 | 湖南源科创新科技股份有限公司 | Native SATA solid-state hard disk controller |
| US9495295B1 (en) * | 2015-04-23 | 2016-11-15 | PhotonIC International Pte. Ltd. | Photonics-optimized processor system |
-
2017
- 2017-12-28 CN CN201711456225.8A patent/CN108196953B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194403A (en) * | 2010-03-17 | 2011-09-21 | 上海仰邦软件科技有限公司 | Microblaze soft core technology-based LED (Light Emitting Diode) large-screen asynchronous control system |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN103941619A (en) * | 2014-04-16 | 2014-07-23 | 南京国电南自美卓控制系统有限公司 | Reconfigurable microcomputer protection development platform based on FPGA |
| CN105260339A (en) * | 2015-08-17 | 2016-01-20 | 中南大学 | Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology |
| CN105242594A (en) * | 2015-09-23 | 2016-01-13 | 成都乐维斯科技有限公司 | Logic control system based on Microblaze soft core processor |
| CN105260164A (en) * | 2015-09-25 | 2016-01-20 | 北京航空航天大学 | Multi-core SoC architecture design method supporting multi-task parallel execution |
| CN106650411A (en) * | 2016-11-24 | 2017-05-10 | 天津津航计算技术研究所 | Verification system for cryptographic algorithms |
Non-Patent Citations (4)
| Title |
|---|
| ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq;Kizheppatt Vipin，Suhaib A. Fahmy;《IEEE Embedded Systems Letters》;20140930;第6卷(第3期);第41-44页 * |
| 一种支持OpenCL的异构多核可重构片上系统硬件架构研究与设计;边育心;《中国优秀硕士学位论文全文数据库 信息科技辑》;20170515;第2017年卷(第05期);第I135-117页 * |
| 基于AXI总线的MicroBlaze双核SoPC系统设计;杨定定，施慧彬;《电子产品世界》;20120131;第2012年卷(第1期);第76-77页 * |
| 基于Xilinx MicroBlaze多核嵌入式系统的设计;何宾，王瑜;《电子设计工程》;20110731;第19卷(第13期);第141-144页 * |
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