CN110674078B - Digital twin system complex task heterogeneous multi-core parallel efficient solving method and system - Google Patents

Digital twin system complex task heterogeneous multi-core parallel efficient solving method and system Download PDF

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CN110674078B
CN110674078B CN201910947700.4A CN201910947700A CN110674078B CN 110674078 B CN110674078 B CN 110674078B CN 201910947700 A CN201910947700 A CN 201910947700A CN 110674078 B CN110674078 B CN 110674078B
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陶飞
邹孝付
左颖
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Beihang University
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip

Abstract

The invention discloses a heterogeneous multi-core parallel efficient solving method and a heterogeneous multi-core parallel efficient solving system for complex tasks of a digital twin system, wherein the method is suitable for a ZYNQ-7000SoC chip of Xilinx company and comprises the following steps: step 1, designing a digital twin system complex task heterogeneous multi-core architecture and a digital description module, wherein the module firstly builds a heterogeneous multi-core architecture for running a digital twin system complex task, and then completes digital description of the heterogeneous multi-core architecture based on a multivariate array model; and 2, designing a heterogeneous multi-core parallel efficient solving decision module for the complex task of the digital twin system, determining an idle core in the current heterogeneous multi-core architecture based on the digital description of the heterogeneous multi-core architecture, and scheduling the arrived digital twin complex task to the idle core for solving operation. The invention can solve the requirement of the complex task of the digital twin system on parallel solution to a certain extent and improve the solution efficiency of the complex task of the digital twin system.

Description

Digital twin system complex task heterogeneous multi-core parallel efficient solving method and system
Technical Field
The invention belongs to the field of electronic engineering and computer science, and particularly relates to a method and a system for efficiently solving complex task heterogeneous multi-core parallel of a digital twin system.
Background
The device health management and control, process simulation analysis and production line running state monitoring based on digital twin driving show strong vitality in intelligent manufacturing, the physical workshop/production line can be simulated and predicted while the real state of the physical workshop/production line is reflected through linkage of a physical entity and a virtual scene, the prediction can cover equipment level, production line level and workshop level, and simulation prediction with the scale of seconds, minutes, hours and the like can be realized, and the complexity of the simulation prediction can be completely referred to as a complex task in a digital twin system. The invention discloses a heterogeneous multi-core parallel high-efficiency solving method and system for complex tasks of a digital twin system, which are suitable for ZYNQ-7000SoC chips of Xilinx company, can solve the requirement of the complex tasks of the digital twin system on parallel solving to a certain extent and improve the solving efficiency of the complex tasks of the digital twin system.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method covers the design of a digital twin system complex task heterogeneous multi-core architecture and a digital description module and the design of a digital twin system complex task heterogeneous multi-core parallel efficient solution decision module, can solve the requirement of the digital twin system complex task on parallel solution to a certain extent, and improves the solving efficiency of the digital twin system complex task.
The technical problem to be solved by the invention is realized by adopting the following technical scheme: a digital twin system complex task heterogeneous multi-core parallel efficient solving method comprises the following steps:
designing a digital twin system complex task heterogeneous multi-core architecture and a digital description module, wherein the module firstly builds a heterogeneous multi-core architecture for running a digital twin system complex task, and then completes digital description of the heterogeneous multi-core architecture based on a multivariate array model, and the specific implementation is as follows:
firstly, constructing a complex task heterogeneous multi-core architecture of a digital twin system: the built heterogeneous multi-core architecture for the complex task operation of the digital twin system comprises 1 FPGA and 4 MicroBlaze cores for parallel solution, wherein the 4 MicroBlaze cores are respectively represented as MicroBlaze _1, MicroBlaze _2, MicroBlaze _3, MicroBlaze _4 and 2 ARM cores and are respectively represented as ARM _1 and ARM _2, BRAM, MailBox and OCM for inter-core communication, and DDR and Flash for program storage and data caching; the FPGA, the MicroBlaze core, the ARM core and the DDR complete interaction through an AXI bus;
secondly, digital description of complex task heterogeneous multi-core architecture of the digital twin system: defining an octant array model to represent the digital description of the complex task heterogeneous multi-core architecture of the digital twin system, namely S _ SoC ═ { S _ FPGA, S _ MicroBlaze, S _ ARM, S _ AXI, S _ MailBox, S _ OCM, S _ DDR, S _ Flash }, wherein:
i S _ FPGA is a digital description set of FPGA, including a quaternion set of FPGA performance index, namely S _ FPGA { S _ FPGA _ clb, S _ FPGA _ bram _ clb, S _ FPGA _ clock, S _ FPGA _ rate }, S _ FPGA _ clb represents the size of hardware resource in FPGA; s _ FPGA _ BRAM _ clb describes the size of a BRAM cache in the FPGA; s _ FPGA _ clock describes the FPGA clock dominant frequency in unit MHz; the S _ FPGA _ rate describes the rate of loading the configuration file from the Flash by the FPGA, namely the read-write rate of the Flash in bps;
ii, S _ MicroBlaze is a digital description set of the MicroBlaze core, and includes a binary number of a performance index of the MicroBlaze core, that is, S _ MicroBlaze ═ { S _ MicroBlaze _ AXIs, S _ MicroBlaze _ clock }, where S _ MicroBlaze _ AXIs represents a bandwidth rate of interaction of the MicroBlaze core with the AXI bus in bps; s _ MicroBlaze _ clock describes MicroBlaze core clock dominant frequency in MHz; the digital description sets of each MicroBlaze core are the same;
iii, the S _ ARM is a digital description set of the ARM core, and includes a binary array of ARM core performance indicators, that is, S _ ARM ═ { S _ ARM _ AXIs, S _ ARM _ clock }, where S _ ARM _ AXIs represents a bandwidth rate of ARM core and AXI bus interaction, in bps; the S _ ARM _ clock describes ARM core clock dominant frequency in unit of MHz; the digital description sets of each ARM core are the same;
iv S _ AXI is a digital description set of the AXI bus, including an unary array of AXI bus performance indicators, i.e., S _ AXI ═ { S _ AXI _ AXIs }, where S _ AXI _ AXIs represents the maximum bandwidth rate of the AXI bus;
v S _ MailBox is a digital description set of MailBox, and includes a unary array of MailBox performance indicators, namely S _ MailBox ═ { S _ MailBox _ size }, S _ MailBox _ size indicates the space size of MailBox, and the indicators affect the single communication volume when the MicroBlaze cores communicate;
vi S _ OCM is a set of digitized descriptions of OCM, and includes a unary array of OCM performance indicators, i.e., S _ OCM ═ { S _ OCM _ size }, S _ OCM _ size indicates the size of space of OCM, and the indicators affect the single traffic during the ARM inter-core communication;
vii S _ DDR is a digital description set of DDR, and includes a binary array of DDR main performance indicators, i.e., S _ DDR ═ { S _ DDR _ rate, S _ DDR _ size }, where S _ DDR _ rate represents the read-write rate of DDR, in bps; s _ DDR _ size represents the space size of DDR;
viii S _ Flash is a digital description set of Flash, and includes a binary array of Flash performance indexes, i.e., S _ Flash ═ { S _ Flash _ rate, S _ Flash _ size }, where S _ Flash _ rate represents the read-write rate of Flash in bps; s _ Flash _ size represents the space size of Flash;
step (2), designing a digital twin system complex task heterogeneous multi-core parallel efficient solving decision module, finishing the determination of an idle core in the current heterogeneous multi-core architecture based on the digital description of the heterogeneous multi-core architecture, and scheduling the arrived digital twin complex task to the idle core for solving operation, wherein the specific implementation is as follows:
an embedded Linux system is transplanted into ARM _1, the ARM _1 runs a digital twin system complex task heterogeneous multi-core parallel solution decision module in a multithreading mode to improve the efficiency of multi-task parallel solution decision, and digital description of a digital twin system complex task heterogeneous multi-core architecture is used as input of the module;
② defining the number of attempted solution operation of task i as CiWhen task i arrives, C is initializediIs 0;
scheduling the task i to the FPGA for solving operation and returning to step two when the sum of the FPGA hardware resource and the FPGA hardware resource required by the task i is less than S _ FPGA _ clb; otherwise, executing the fourth step;
when the S _ MicroBlaze _ index of the MicroBlaze _1 is equal to 0 at the moment, indicating that the MicroBlaze _1 is idle, scheduling the task i to the MicroBlaze _1 for solving operation, and returning to the step two; otherwise, executing the fifth step;
fifthly, when the S _ MicroBlaze _ index of the MicroBlaze _2 is equal to 0 at the moment, indicating that the MicroBlaze _2 is idle, scheduling the task i to the MicroBlaze _2 for solving operation, and returning to the step two; otherwise, executing the step (c);
when the S _ MicroBlaze _ index of the MicroBlaze _3 is equal to 0 at the moment, indicating that the MicroBlaze _3 is idle, scheduling the task i to the MicroBlaze _3 for solving operation, and returning to the step two; otherwise, carrying out the operation;
when the S _ MicroBlaze _ index of the MicroBlaze _4 is equal to 0 at the moment, indicating that the MicroBlaze _4 is idle, scheduling the task i to the MicroBlaze _4 for solution operation, and returning to the step two; otherwise, executing the step b;
when the S _ ARM _ axirate of the ARM _2 is equal to 0 at the moment, the ARM _2 is idle, a task i is dispatched to the ARM _2 to carry out solving operation, and the task i returns to the second step; otherwise, C is addediAdding 1 and performing ninthly;
ninthly if CiIf the number of the solution operation attempts of the task i exceeds the set value, the task i is discarded and returned to the step two, otherwise, the task i is returned to the step three.
The invention designs a heterogeneous multi-core parallel efficient solving method for complex tasks of a digital twin system, which is suitable for ZYNQ-7000SoC chips of Xilinx company.
The invention also provides a complex task heterogeneous multi-core parallel efficient solving system of the digital twin system, which comprises the following steps: the system comprises a digital twin system complex task heterogeneous multi-core architecture, a digital description module and a digital twin system complex task heterogeneous multi-core parallel efficient solution decision module; wherein the content of the first and second substances,
the digital twin system complex task heterogeneous multi-core architecture and the digital description module are realized by firstly building the heterogeneous multi-core architecture for running the digital twin system complex task, and then completing the digital description of the heterogeneous multi-core architecture based on a multi-element array model as follows:
firstly, constructing a complex task heterogeneous multi-core architecture of a digital twin system: the built heterogeneous multi-core architecture for the complex task operation of the digital twin system comprises 1 FPGA and 4 MicroBlaze cores for parallel solution, wherein the 4 MicroBlaze cores are respectively represented as MicroBlaze _1, MicroBlaze _2, MicroBlaze _3, MicroBlaze _4 and 2 ARM cores and are respectively represented as ARM _1 and ARM _2, BRAM, MailBox and OCM for inter-core communication, and DDR and Flash for program storage and data caching; the FPGA, the MicroBlaze core, the ARM core and the DDR complete interaction through an AXI bus;
secondly, digital description of complex task heterogeneous multi-core architecture of the digital twin system: defining an octant array model to represent the digital description of the complex task heterogeneous multi-core architecture of the digital twin system, namely S _ SoC ═ { S _ FPGA, S _ MicroBlaze, S _ ARM, S _ AXI, S _ MailBox, S _ OCM, S _ DDR, S _ Flash }, wherein:
i S _ FPGA is a digital description set of FPGA, including a quaternion set of FPGA performance index, namely S _ FPGA { S _ FPGA _ clb, S _ FPGA _ bram _ clb, S _ FPGA _ clock, S _ FPGA _ rate }, S _ FPGA _ clb represents the size of hardware resource in FPGA; s _ FPGA _ BRAM _ clb describes the size of a BRAM cache in the FPGA; s _ FPGA _ clock describes the FPGA clock dominant frequency in unit MHz; the S _ FPGA _ rate describes the rate of loading the configuration file from the Flash by the FPGA, namely the read-write rate of the Flash in bps;
ii, S _ MicroBlaze is a digital description set of the MicroBlaze core, and includes a binary number of a performance index of the MicroBlaze core, that is, S _ MicroBlaze ═ { S _ MicroBlaze _ AXIs, S _ MicroBlaze _ clock }, where S _ MicroBlaze _ AXIs represents a bandwidth rate of interaction of the MicroBlaze core with the AXI bus in bps; s _ MicroBlaze _ clock describes MicroBlaze core clock dominant frequency in MHz; the digital description sets of each MicroBlaze core are the same;
iii, the S _ ARM is a digital description set of the ARM core, and includes a binary array of ARM core performance indicators, that is, S _ ARM ═ { S _ ARM _ AXIs, S _ ARM _ clock }, where S _ ARM _ AXIs represents a bandwidth rate of ARM core and AXI bus interaction, in bps; the S _ ARM _ clock describes ARM core clock dominant frequency in unit of MHz; the digital description sets of each ARM core are the same;
iv S _ AXI is a digital description set of the AXI bus, including an unary array of AXI bus performance indicators, i.e., S _ AXI ═ { S _ AXI _ AXIs }, where S _ AXI _ AXIs represents the maximum bandwidth rate of the AXI bus;
v S _ MailBox is a digital description set of MailBox, and includes a unary array of MailBox performance indicators, namely S _ MailBox ═ { S _ MailBox _ size }, S _ MailBox _ size indicates the space size of MailBox, and the indicators affect the single communication volume when the MicroBlaze cores communicate;
vi S _ OCM is a set of digitized descriptions of OCM, and includes a unary array of OCM performance indicators, i.e., S _ OCM ═ { S _ OCM _ size }, S _ OCM _ size indicates the size of space of OCM, and the indicators affect the single traffic during the ARM inter-core communication;
vii S _ DDR is a digital description set of DDR, and includes a binary array of DDR main performance indicators, i.e., S _ DDR ═ { S _ DDR _ rate, S _ DDR _ size }, where S _ DDR _ rate represents the read-write rate of DDR, in bps; s _ DDR _ size represents the space size of DDR;
viii S _ Flash is a digital description set of Flash, and includes a binary array of Flash performance indexes, i.e., S _ Flash ═ { S _ Flash _ rate, S _ Flash _ size }, where S _ Flash _ rate represents the read-write rate of Flash in bps; s _ Flash _ size represents the space size of Flash;
the heterogeneous multi-core parallel efficient solution decision module for the complex task of the digital twin system finishes determination of an idle core in a current heterogeneous multi-core architecture based on digital description of the heterogeneous multi-core architecture, dispatches an arriving digital twin complex task to the idle core for solution operation, and specifically realizes the following steps:
an embedded Linux system is transplanted into ARM _1, the ARM _1 runs a digital twin system complex task heterogeneous multi-core parallel solution decision module in a multithreading mode to improve the efficiency of multi-task parallel solution decision, and digital description of a digital twin system complex task heterogeneous multi-core architecture is used as input of the module;
② defining the number of attempted solution operation of task i as CiWhen task i arrives, C is initializediIs 0;
scheduling the task i to the FPGA for solving operation and returning to step two when the sum of the FPGA hardware resource and the FPGA hardware resource required by the task i is less than S _ FPGA _ clb; otherwise, executing the fourth step;
when the S _ MicroBlaze _ index of the MicroBlaze _1 is equal to 0 at the moment, indicating that the MicroBlaze _1 is idle, scheduling the task i to the MicroBlaze _1 for solving operation, and returning to the step two; otherwise, executing the fifth step;
fifthly, when the S _ MicroBlaze _ index of the MicroBlaze _2 is equal to 0 at the moment, indicating that the MicroBlaze _2 is idle, scheduling the task i to the MicroBlaze _2 for solving operation, and returning to the step two; otherwise, executing the step (c);
when the S _ MicroBlaze _ index of the MicroBlaze _3 is equal to 0 at the moment, indicating that the MicroBlaze _3 is idle, scheduling the task i to the MicroBlaze _3 for solving operation, and returning to the step two; otherwise, carrying out the operation;
when the S _ MicroBlaze _ index of the MicroBlaze _4 is equal to 0 at the moment, indicating that the MicroBlaze _4 is idle, scheduling the task i to the MicroBlaze _4 for solution operation, and returning to the step two; otherwise, executing the step b;
when the S _ ARM _ axirate of the ARM _2 is equal to 0 at the moment, the ARM _2 is idle, a task i is dispatched to the ARM _2 to carry out solving operation, and the task i returns to the second step; otherwise, C is addediAdding 1 and performing ninthly;
ninthly if CiIf the number of the solution operation attempts of the task i exceeds the set value, the task i is discarded and returned to the step two, otherwise, the task i is returned to the step three.
Compared with the prior art, the invention has the advantages that:
(1) the heterogeneous multi-core architecture described based on the multi-element array model can more comprehensively realize the digital description of the heterogeneous multi-core architecture and improve the digital description fineness of the heterogeneous multi-core architecture;
(2) the digital description of the heterogeneous multi-core architecture is used as the input of the parallel solution decision module, so that the states of all operation units in the current heterogeneous multi-core architecture can be more accurately determined, and the scheduling and parallel solution of multiple tasks on heterogeneous cores are facilitated.
Drawings
FIG. 1 is a block diagram of the system architecture of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawings.
The invention relates to a method and a system for parallel efficient solution of complex task heterogeneous multi-core of a digital twin system, which are suitable for ZYNQ-7000SoC chips of Xilinx company. The key technology of the digital twin is represented by reflecting the real state of a physical workshop/production line through the linkage of a physical entity and a virtual scene, and simultaneously realizing the simulation prediction of the physical workshop/production line, wherein the prediction can cover equipment level, production line level and workshop level, and can realize the simulation prediction with the scale of seconds, minutes, hours and the like, and the complexity of the simulation prediction can be completely referred to as a complex task in a digital twin system. The functions which can be realized in the application of the digital twin technology all need to realize solving operation through a certain operation unit, the efficiency of the solving operation is closely related to the performance of the operation unit, and for tasks with different characteristics, the solving efficiency can be improved if the corresponding operation unit can meet the operation requirements. The method disclosed by the invention comprises a digital twin system complex task heterogeneous multi-core architecture and digital description module design and a digital twin system complex task heterogeneous multi-core parallel efficient solution decision module design, can solve the requirement of the digital twin system complex task on parallel solution to a certain extent, and improves the digital twin system complex task solution efficiency.
The system structure block diagram of the invention is shown in fig. 1, and the specific implementation mode is as follows:
(1) fig. 1 shows a digital twin system complex task heterogeneous multi-core architecture and a digital description module, which are specifically implemented as follows:
firstly, constructing a complex task heterogeneous multi-core architecture of a digital twin system: the built heterogeneous multi-core architecture for the complex task operation of the digital twin system comprises 1 FPGA, 4 MicroBlaze cores (respectively represented as MicroBlaze _1, MicroBlaze _2, MicroBlaze _3 and MicroBlaze _4), 2 ARM cores (respectively represented as ARM _1 and ARM _2), a BRAM (Block Random Access Memory) for inter-core communication, a MailBox (MailBox), an OCM (On Chip Memory), and DDR and Flash for program storage and data cache; the FPGA, the MicroBlaze core, the ARM core and the DDR complete interaction through an AXI bus;
secondly, digital description of complex task heterogeneous multi-core architecture of the digital twin system: defining an octant array model to represent the digital description of the complex task heterogeneous multi-core architecture of the digital twin system, namely S _ SoC ═ { S _ FPGA, S _ MicroBlaze, S _ ARM, S _ AXI, S _ MailBox, S _ OCM, S _ DDR, S _ Flash }, wherein:
i. the S _ FPGA is a digital description set of the FPGA and is composed of a quaternion group containing main performance indexes of the FPGA, that is, S _ FPGA is { S _ FPGA _ CLB, S _ FPGA _ bram _ CLB, S _ FPGA _ clock, S _ FPGA _ rate }, and S _ FPGA _ CLB represents the size of hardware resources in the FPGA (the interior of the FPGA includes various resources, most of which are CLBs (programmable logic blocks), and programs of users run on the CLBs, so the number of CLBs in the FPGA is referred to herein); s _ FPGA _ BRAM _ clb describes the size of a BRAM cache in the FPGA; s _ FPGA _ clock describes the FPGA clock dominant frequency in unit MHz; the S _ FPGA _ rate describes the rate of loading the configuration file from the Flash by the FPGA, namely the read-write rate of the Flash in bps;
ii. The S _ MicroBlaze is a digital description set of the MicroBlaze core and is composed of a binary array containing main performance indexes of the MicroBlaze core, that is, S _ MicroBlaze ═ { S _ MicroBlaze _ AXIs, S _ MicroBlaze _ clock }, and S _ MicroBlaze _ AXIs represents a bandwidth rate of interaction between the MicroBlaze core and the AXI bus, in bps; s _ MicroBlaze _ clock describes MicroBlaze core clock dominant frequency in MHz; the digital description sets of each MicroBlaze core are the same;
iii, the S _ ARM is a digital description set of the ARM core, and is composed of a binary array containing main performance indexes of the ARM core, that is, S _ ARM ═ { S _ ARM _ AXIs, S _ ARM _ clock }, where S _ ARM _ AXIs represents a bandwidth rate of interaction between the ARM core and the AXI bus, in bps; the S _ ARM _ clock describes ARM core clock dominant frequency in unit of MHz; the digital description sets of each ARM core are the same;
iv, S _ AXI is a digital description set of the AXI bus, and is composed of an unary array containing main performance indexes of the AXI bus, that is, S _ AXI ═ { S _ AXI _ AXIs }, where S _ AXI _ AXIs represents the maximum bandwidth rate of the AXI bus;
v and S _ MailBox are a digital description set of the MailBox and are composed of a unary array containing main performance indexes of the MailBox, namely S _ MailBox ═ { S _ MailBox _ size }, and S _ MailBox _ size represents the space size of the MailBox, and the indexes affect single communication volume during communication between MicroBlaze cores; the MailBox realizes the communication among MicroBlaze cores in the Xilinx FPGA/SoC and is a communication medium.
vi, S _ OCM is a digitized description set of OCM, and is composed of a unary array including a main performance index of OCM, i.e., S _ OCM ═ { S _ OCM _ size }, S _ OCM _ size indicates the space size of OCM, and the index affects single traffic during communication between ARM cores; the OCM realizes communication among ARM cores in the Xilinx SoC and is a communication medium.
vii, S _ DDR is a digital description set of DDR, and is composed of a binary array including main performance indicators of DDR, that is, { S _ DDR _ rate, S _ DDR _ size }, S _ DDR _ rate represents the read-write rate of DDR, in bps; s _ DDR _ size represents the space size of DDR;
viii and S _ Flash are digital description sets of Flash, and are composed of binary arrays containing main performance indexes of Flash, that is, S _ Flash is { S _ Flash _ rate, S _ Flash _ size }, and S _ Flash _ rate represents the read-write rate of Flash in units of bps; s _ Flash _ size represents the space size of Flash;
(2) fig. 1 shows a decision module for parallel efficient solution of heterogeneous multi-core complex tasks of a digital twin system at 2, which is specifically implemented as follows:
an embedded Linux system is transplanted into ARM _1, the ARM _1 runs a digital twin system complex task heterogeneous multi-core parallel solution decision module in a multithreading mode to improve the efficiency of multi-task parallel solution decision, and digital description of a digital twin system complex task heterogeneous multi-core architecture is used as input of the module;
② defining the number of attempted solution operation of task i as CiWhen task i arrives, C is initializediIs 0;
scheduling the task i to the FPGA for solving operation and returning to step two when the sum of the FPGA hardware resource and the FPGA hardware resource required by the task i is less than S _ FPGA _ clb; otherwise, executing the fourth step;
when the S _ MicroBlaze _ index of the MicroBlaze _1 is equal to 0 at the moment, indicating that the MicroBlaze _1 is idle, scheduling the task i to the MicroBlaze _1 for solving operation, and returning to the step two; otherwise, executing the fifth step;
fifthly, when the S _ MicroBlaze _ index of the MicroBlaze _2 is equal to 0 at the moment, indicating that the MicroBlaze _2 is idle, scheduling the task i to the MicroBlaze _2 for solving operation, and returning to the step two; otherwise, executing the step (c);
when the S _ MicroBlaze _ index of the MicroBlaze _3 is equal to 0 at the moment, indicating that the MicroBlaze _3 is idle, scheduling the task i to the MicroBlaze _3 for solving operation, and returning to the step two; otherwise, carrying out the operation;
when the S _ MicroBlaze _ index of the MicroBlaze _4 is equal to 0 at the moment, indicating that the MicroBlaze _4 is idle, scheduling the task i to the MicroBlaze _4 for solution operation, and returning to the step two; otherwise, executing the step b;
when the S _ ARM _ axirate of the ARM _2 is equal to 0 at the moment, the ARM _2 is idle, a task i is dispatched to the ARM _2 to carry out solving operation, and the task i returns to the second step; otherwise, C is addediAdding 1 and performing ninthly;
ninthly if CiIf the number of the solution operation attempts of the task i exceeds the set value, the task i is discarded and returned to the step two, otherwise, the task i is returned to the step three.
In summary, the invention discloses a digital twin system complex task heterogeneous multi-core parallel efficient solving method and system, which comprises a digital twin system complex task heterogeneous multi-core architecture and digital description module design and a digital twin system complex task heterogeneous multi-core parallel efficient solving decision module design, and can solve the requirement of the digital twin system complex task on parallel solving to a certain extent and improve the solving efficiency of the digital twin system complex task.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (4)

1. A digital twin system complex task heterogeneous multi-core parallel efficient solving method is characterized by comprising the following steps:
designing a digital twin system complex task heterogeneous multi-core architecture and a digital description module, wherein the module firstly builds a heterogeneous multi-core architecture for running a digital twin system complex task, and then completes digital description of the heterogeneous multi-core architecture based on a multivariate array model, and the specific implementation is as follows:
firstly, constructing a complex task heterogeneous multi-core architecture of a digital twin system: the built heterogeneous multi-core architecture for the complex task operation of the digital twin system comprises 1 FPGA and 4 MicroBlaze cores for parallel solution, wherein the 4 MicroBlaze cores are respectively represented as MicroBlaze _1, MicroBlaze _2, MicroBlaze _3, MicroBlaze _4 and 2 ARM cores and are respectively represented as ARM _1 and ARM _2, BRAM, MailBox and OCM for inter-core communication, and DDR and Flash for program storage and data caching; the FPGA, the MicroBlaze core, the ARM core and the DDR complete interaction through an AXI bus;
secondly, digital description of complex task heterogeneous multi-core architecture of the digital twin system: defining an octant array model to represent the digital description of the complex task heterogeneous multi-core architecture of the digital twin system, namely S _ SoC ═ { S _ FPGA, S _ MicroBlaze, S _ ARM, S _ AXI, S _ MailBox, S _ OCM, S _ DDR, S _ Flash }, wherein:
i S _ FPGA is a digital description set of FPGA, including a quaternion set of FPGA performance index, namely S _ FPGA { S _ FPGA _ clb, S _ FPGA _ bram _ clb, S _ FPGA _ clock, S _ FPGA _ rate }, S _ FPGA _ clb represents the size of hardware resource in FPGA; s _ FPGA _ BRAM _ clb describes the size of a BRAM cache in the FPGA; s _ FPGA _ clock describes the FPGA clock dominant frequency in unit MHz; the S _ FPGA _ rate describes the rate of loading the configuration file from the Flash by the FPGA, namely the read-write rate of the Flash in bps;
ii, S _ MicroBlaze is a digital description set of the MicroBlaze core, and includes a binary number of a performance index of the MicroBlaze core, that is, S _ MicroBlaze ═ { S _ MicroBlaze _ AXIs, S _ MicroBlaze _ clock }, where S _ MicroBlaze _ AXIs represents a bandwidth rate of interaction of the MicroBlaze core with the AXI bus in bps; s _ MicroBlaze _ clock describes MicroBlaze core clock dominant frequency in MHz; the digital description sets of each MicroBlaze core are the same;
iii, the S _ ARM is a digital description set of the ARM core, and includes a binary array of ARM core performance indicators, that is, S _ ARM ═ { S _ ARM _ AXIs, S _ ARM _ clock }, where S _ ARM _ AXIs represents a bandwidth rate of ARM core and AXI bus interaction, in bps; the S _ ARM _ clock describes ARM core clock dominant frequency in unit of MHz; the digital description sets of each ARM core are the same;
iv S _ AXI is a digital description set of the AXI bus, including an unary array of AXI bus performance indicators, i.e., S _ AXI ═ { S _ AXI _ AXIs }, where S _ AXI _ AXIs represents the maximum bandwidth rate of the AXI bus;
v S _ MailBox is a digital description set of MailBox, and includes a unary array of MailBox performance indicators, namely S _ MailBox ═ { S _ MailBox _ size }, S _ MailBox _ size indicates the space size of MailBox, and the indicators affect the single communication volume when the MicroBlaze cores communicate;
vi S _ OCM is a set of digitized descriptions of OCM, and includes a unary array of OCM performance indicators, i.e., S _ OCM ═ { S _ OCM _ size }, S _ OCM _ size indicates the size of space of OCM, and the indicators affect the single traffic during the ARM inter-core communication;
vii S _ DDR is a digital description set of DDR, and includes a binary array of DDR main performance indicators, i.e., S _ DDR ═ { S _ DDR _ rate, S _ DDR _ size }, where S _ DDR _ rate represents the read-write rate of DDR, in bps; s _ DDR _ size represents the space size of DDR;
viii S _ Flash is a digital description set of Flash, and includes a binary array of Flash performance indexes, i.e., S _ Flash ═ { S _ Flash _ rate, S _ Flash _ size }, where S _ Flash _ rate represents the read-write rate of Flash in bps; s _ Flash _ size represents the space size of Flash;
step (2), designing a digital twin system complex task heterogeneous multi-core parallel efficient solving decision module, finishing the determination of an idle core in the current heterogeneous multi-core architecture based on the digital description of the heterogeneous multi-core architecture, and scheduling the arrived digital twin complex task to the idle core for solving operation, wherein the specific implementation is as follows:
an embedded Linux system is transplanted into ARM _1, the ARM _1 runs a digital twin system complex task heterogeneous multi-core parallel solution decision module in a multithreading mode to improve the efficiency of multi-task parallel solution decision, and digital description of a digital twin system complex task heterogeneous multi-core architecture is used as input of the module;
② defining the number of attempted solution operation of task i as CiWhen task i arrives, C is initializediIs 0;
scheduling the task i to the FPGA for solving operation and returning to step two when the sum of the FPGA hardware resource and the FPGA hardware resource required by the task i is less than S _ FPGA _ clb; otherwise, executing the fourth step;
when the S _ MicroBlaze _ index of the MicroBlaze _1 is equal to 0 at the moment, indicating that the MicroBlaze _1 is idle, scheduling the task i to the MicroBlaze _1 for solving operation, and returning to the step two; otherwise, executing the fifth step;
fifthly, when the S _ MicroBlaze _ index of the MicroBlaze _2 is equal to 0 at the moment, indicating that the MicroBlaze _2 is idle, scheduling the task i to the MicroBlaze _2 for solving operation, and returning to the step two; otherwise, executing the step (c);
when the S _ MicroBlaze _ index of the MicroBlaze _3 is equal to 0 at the moment, indicating that the MicroBlaze _3 is idle, scheduling the task i to the MicroBlaze _3 for solving operation, and returning to the step two; otherwise, carrying out the operation;
when the S _ MicroBlaze _ index of the MicroBlaze _4 is equal to 0 at the moment, indicating that the MicroBlaze _4 is idle, scheduling the task i to the MicroBlaze _4 for solution operation, and returning to the step two; otherwise, executing the step b;
when the S _ ARM _ axirate of the ARM _2 is equal to 0 at the moment, the ARM _2 is idle, a task i is dispatched to the ARM _2 to carry out solving operation, and the task i returns to the second step; otherwise, C is addediAdding 1 and performing ninthly;
ninthly if CiIf the number of the solution operation attempts of the task i exceeds the set value, the task i is discarded and returned to the step two, otherwise, the task i is returned to the step three.
2. The method for parallel efficient solution of heterogeneous multi-core of complex task of digital twin system as claimed in claim 1, wherein the method is applied to Xilinx ZYNQ-7000SoC chip.
3. A digital twin system complex task heterogeneous multi-core parallel efficient solving system is characterized by comprising the following steps: the system comprises a digital twin system complex task heterogeneous multi-core architecture, a digital description module and a digital twin system complex task heterogeneous multi-core parallel efficient solution decision module; wherein the content of the first and second substances,
the digital twin system complex task heterogeneous multi-core architecture and the digital description module are realized by firstly building the heterogeneous multi-core architecture for running the digital twin system complex task, and then completing the digital description of the heterogeneous multi-core architecture based on a multi-element array model as follows:
firstly, constructing a complex task heterogeneous multi-core architecture of a digital twin system: the built heterogeneous multi-core architecture for the complex task operation of the digital twin system comprises 1 FPGA and 4 MicroBlaze cores for parallel solution, wherein the 4 MicroBlaze cores are respectively represented as MicroBlaze _1, MicroBlaze _2, MicroBlaze _3, MicroBlaze _4 and 2 ARM cores and are respectively represented as ARM _1 and ARM _2, BRAM, MailBox and OCM for inter-core communication, and DDR and Flash for program storage and data caching; the FPGA, the MicroBlaze core, the ARM core and the DDR complete interaction through an AXI bus;
secondly, digital description of complex task heterogeneous multi-core architecture of the digital twin system: defining an octant array model to represent the digital description of the complex task heterogeneous multi-core architecture of the digital twin system, namely S _ SoC ═ { S _ FPGA, S _ MicroBlaze, S _ ARM, S _ AXI, S _ MailBox, S _ OCM, S _ DDR, S _ Flash }, wherein:
i S _ FPGA is a digital description set of FPGA, including a quaternion set of FPGA performance index, namely S _ FPGA { S _ FPGA _ clb, S _ FPGA _ bram _ clb, S _ FPGA _ clock, S _ FPGA _ rate }, S _ FPGA _ clb represents the size of hardware resource in FPGA; s _ FPGA _ BRAM _ clb describes the size of a BRAM cache in the FPGA; s _ FPGA _ clock describes the FPGA clock dominant frequency in unit MHz; the S _ FPGA _ rate describes the rate of loading the configuration file from the Flash by the FPGA, namely the read-write rate of the Flash in bps;
ii, S _ MicroBlaze is a digital description set of the MicroBlaze core, and includes a binary number of a performance index of the MicroBlaze core, that is, S _ MicroBlaze ═ { S _ MicroBlaze _ AXIs, S _ MicroBlaze _ clock }, where S _ MicroBlaze _ AXIs represents a bandwidth rate of interaction of the MicroBlaze core with the AXI bus in bps; s _ MicroBlaze _ clock describes MicroBlaze core clock dominant frequency in MHz; the digital description sets of each MicroBlaze core are the same;
iii, the S _ ARM is a digital description set of the ARM core, and includes a binary array of ARM core performance indicators, that is, S _ ARM ═ { S _ ARM _ AXIs, S _ ARM _ clock }, where S _ ARM _ AXIs represents a bandwidth rate of ARM core and AXI bus interaction, in bps; the S _ ARM _ clock describes ARM core clock dominant frequency in unit of MHz; the digital description sets of each ARM core are the same;
iv S _ AXI is a digital description set of the AXI bus, including an unary array of AXI bus performance indicators, i.e., S _ AXI ═ { S _ AXI _ AXIs }, where S _ AXI _ AXIs represents the maximum bandwidth rate of the AXI bus;
v S _ MailBox is a digital description set of MailBox, and includes a unary array of MailBox performance indicators, namely S _ MailBox ═ { S _ MailBox _ size }, S _ MailBox _ size indicates the space size of MailBox, and the indicators affect the single communication volume when the MicroBlaze cores communicate;
vi S _ OCM is a set of digitized descriptions of OCM, and includes a unary array of OCM performance indicators, i.e., S _ OCM ═ { S _ OCM _ size }, S _ OCM _ size indicates the size of space of OCM, and the indicators affect the single traffic during the ARM inter-core communication;
vii S _ DDR is a digital description set of DDR, and includes a binary array of DDR main performance indicators, i.e., S _ DDR ═ { S _ DDR _ rate, S _ DDR _ size }, where S _ DDR _ rate represents the read-write rate of DDR, in bps; s _ DDR _ size represents the space size of DDR;
viii S _ Flash is a digital description set of Flash, and includes a binary array of Flash performance indexes, i.e., S _ Flash ═ { S _ Flash _ rate, S _ Flash _ size }, where S _ Flash _ rate represents the read-write rate of Flash in bps; s _ Flash _ size represents the space size of Flash;
the heterogeneous multi-core parallel efficient solution decision module for the complex task of the digital twin system finishes determination of an idle core in a current heterogeneous multi-core architecture based on digital description of the heterogeneous multi-core architecture, dispatches an arriving digital twin complex task to the idle core for solution operation, and specifically realizes the following steps:
an embedded Linux system is transplanted into ARM _1, the ARM _1 runs a digital twin system complex task heterogeneous multi-core parallel solution decision module in a multithreading mode to improve the efficiency of multi-task parallel solution decision, and digital description of a digital twin system complex task heterogeneous multi-core architecture is used as input of the module;
② defining the number of attempted solution operation of task i as CiWhen task i arrives, C is initializediIs 0;
scheduling the task i to the FPGA for solving operation and returning to step two when the sum of the FPGA hardware resource and the FPGA hardware resource required by the task i is less than S _ FPGA _ clb; otherwise, executing the fourth step;
when the S _ MicroBlaze _ index of the MicroBlaze _1 is equal to 0 at the moment, indicating that the MicroBlaze _1 is idle, scheduling the task i to the MicroBlaze _1 for solving operation, and returning to the step two; otherwise, executing the fifth step;
fifthly, when the S _ MicroBlaze _ index of the MicroBlaze _2 is equal to 0 at the moment, indicating that the MicroBlaze _2 is idle, scheduling the task i to the MicroBlaze _2 for solving operation, and returning to the step two; otherwise, executing the step (c);
when the S _ MicroBlaze _ index of the MicroBlaze _3 is equal to 0 at the moment, indicating that the MicroBlaze _3 is idle, scheduling the task i to the MicroBlaze _3 for solving operation, and returning to the step two; otherwise, carrying out the operation;
when the S _ MicroBlaze _ index of the MicroBlaze _4 is equal to 0 at the moment, indicating that the MicroBlaze _4 is idle, scheduling the task i to the MicroBlaze _4 for solution operation, and returning to the step two; otherwise, executing the step b;
when the S _ ARM _ axirate of the ARM _2 is equal to 0 at the moment, the ARM _2 is idle, a task i is dispatched to the ARM _2 to carry out solving operation, and the task i returns to the second step; otherwise, C is addediAdding 1 and performing ninthly;
ninthly if CiIf the number of the solution operation attempts of the task i exceeds the set value, the task i is discarded and returned to the step two, otherwise, the task i is returned to the step three.
4. The system as claimed in claim 3, wherein the system is suitable for Xilinx ZYNQ-7000SoC chips.
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